CN108134525B

CN108134525B - Digital control method without control delay based on DSP

Info

Publication number: CN108134525B
Application number: CN201711356833.1A
Authority: CN
Inventors: 赵毅
Original assignee: Xi'an Yifei Nuclear Energy Equipment Co ltd
Current assignee: Xi'an Yifei Nuclear Energy Equipment Co ltd
Priority date: 2017-12-16
Filing date: 2017-12-16
Publication date: 2020-05-22
Anticipated expiration: 2037-12-16
Also published as: CN108134525A

Abstract

The invention discloses a digital control method without control delay based on DSP. The invention is characterized in that: (1) the sampling timer and the carrier timer are out of phase for a certain time, and the time length depends on the specific current loop calculation time; 2) adjusting the operation sequence of each module in sampling interruption, and calculating a current loop after sampling is completed; 3) the DSP refreshing mode adopts an immediate refreshing mode. Through the adjustment of the three points, the uncontrolled delay of a digital control mode can be realized, and the bandwidth of the equipment is improved to the maximum extent. The invention breaks through the control delay of DSP and has good application prospect; the method has a great promoting effect on the innovation of the digital control field.

Description

Digital control method without control delay based on DSP

Technical Field

The invention belongs to the field of power electronics, and particularly relates to a digital control method of a single-phase PWM rectifier.

Background

With the economic development, the PWM rectifier is more and more widely applied, and the old uncontrollable or phase-controlled rectification mode is gradually replaced due to the characteristics of networking current sine and unit power factor.

With the development of power electronic control technology, no matter a PWM rectifier or other power electronic topologies, the development is moving towards digital control. Compared with analog control, digital control has many advantages, such as the control can be realized by using a processor, the integration of devices is higher, and the problems of temperature drift and null drift of an analog mode are solved. The conventional processor is mostly a DSP processor, because the inherent sequential execution problem of the DSP processor and the shadow register problem of the DSP event manager always have a control delay problem from sampling to refreshing time, which severely restricts the improvement of the system bandwidth, and many scholars study this aspect, and implement the delay manner of half cycle and 1/4 cycle by using the dual refresh mode and the high sampling frequency, but the delay still has an influence on the bandwidth of the PWM rectifier.

Disclosure of Invention

The invention aims to overcome the problems of the digital control implementation method realized by the current DSP, and provides a digital control method without control delay realized based on the DSP, so that the non-control delay of a digital control mode is realized, and the bandwidth of equipment is improved to the maximum extent.

The invention carries out certain time phase dislocation on the sampling timer and the carrier timer (the time depends on the time calculated by the DSP current loop), adjusts the calculation sequence of the current loop, calculates the current loop after the sampling is finished, and the carrier register of the event manager adopts an immediate refresh mode, thereby realizing digital control without delay, increasing the bandwidth of the digital control to the maximum extent and improving the performance of the PWM rectifier.

The technical scheme of the invention is as follows:

the digital control method without control delay based on DSP comprises the following steps:

a. configuring a system clock of the DSP, and configuring an IO port corresponding to hardware;

b. configuring an event manager of the DSP, setting a timing period of a timer T1, setting a timer T1 as a timer for triggering sampling calculation interruption as underflow and overflow double-trigger interruption;

c. configuring an event manager of the DSP, setting a timing period of a timer T3, setting a timer T3 as a carrier timer to be in double refresh of underflow and overflow without triggering interruption, and setting the timer to be in an immediate refresh mode;

d. the sampling calculation is interrupted, and the specific execution sequence is as follows: sampling, current loop calculation, loading a timer T3 register, phase locking, bus voltage loop calculation and ending interruption;

e. measuring the running time of executing sampling, current loop calculation and loading timer T3 register in the sampling calculation interruption, and recording as delta T;

f. configuring an event manager of the DSP, and setting a timer T1 to lead the time of a timer T3 delta T;

d. and a PWM pin corresponding to the timer T3 outputs PWM driving waves.

System of a better adapted single phase PWM rectifier: the voltage type converter adopts IGBT to realize the topology of six three-phase tubes, and the direct current bus adopts electrolytic capacitor. The control of the whole system can be completed by one DSP. The main work of the DSP is realized as a time sequence control, a fault protection and a control algorithm.

The timing cycle of the timer T1 and the timing cycle of the timer T3 are both set to 0.05 us.

The DSP is preferably TMS320F28335 manufactured by Ti company.

The invention has the following beneficial effects:

1) the sampling timer and the carrier timer are out of phase for a certain time, and the time length depends on the specific current loop calculation time; 2) adjusting the operation sequence of each module in sampling interruption, and calculating a current loop after sampling is completed; 3) the DSP refreshing mode adopts an immediate refreshing mode. Through the adjustment of the three points, the uncontrolled delay of a digital control mode can be realized, and the bandwidth of the equipment is improved to the maximum extent. The invention breaks through the control delay of the DSP from the established thinking, has good application prospect and has great promotion effect on the innovation of the digital control field.

Drawings

Fig. 1 is a block diagram of a single-phase rectifier topology and a control system according to the present invention.

Fig. 2 is a timing diagram of a conventional single-cycle control delay.

Fig. 3 is a timing diagram of a conventional half-cycle control delay.

Fig. 4 is a flowchart of a conventional interrupt sequence execution of a long-period control delay.

Fig. 5 is a timing diagram of the present invention without control delay.

FIG. 6 is a flow chart of the present invention for the sequential execution of interrupts without control delay.

Detailed Description

The invention will be described in further detail below with reference to specific embodiments and the attached drawings:

fig. 1 shows a system of single-phase PWM rectifiers: the voltage type converter adopts IGBT to realize the topology of six three-phase pipes, the direct current bus adopts electrolytic capacitor, the control of the whole system is completed by a DSP, and the DSP adopts TMS320F28335 of Ti company. The main work of the DSP is realized as a time sequence control, a fault protection and a control algorithm.

Fig. 2 and 3 show a timing chart of a conventional single-cycle control delay and a timing chart of a conventional half-cycle control delay. FIG. 4 is a flow chart of a conventional long-period control delay for execution of an interrupt sequence. It can be seen from the figure that the sampling timer and the carrier timer are separately counted, in this case, only underflow refresh or overflow and underflow double refresh is adopted, the shadow register inside 28335 is valid, that is, the loaded value needs to be refreshed to the comparison register when the next overflow or underflow occurs, and thus there is a delay from sampling to refreshing. If immediate refresh is forced, there will be lost pulses and there will be sunken pits in the waveform, possibly even causing an over-current failure of the PWM rectifier.

The digital control method without control delay provided by the invention is shown in fig. 5 and 6. The specific implementation part is as follows:

a. configuring a system clock of 28335, configuring an IO port corresponding to hardware, and specifically configuring a PWM wave IO port corresponding to a T3 timer with a multiplexing PWM wave function.

b. Configuring an event manager of 28335, setting a timer period of T1 to 0.05us, specifically configuring T1PR to be 3750, and setting a T1 timer as a timer for triggering sampling computation interrupt to be an underflow and overflow double-trigger interrupt, specifically configuring ACTRLD to be 1.

c. Configuring an event manager of 28335, setting a timer period of T3 to 0.05us, specifically configuring T1PR to 3750, using a T3 timer as a carrier timer, setting to underflow and overflow double refresh, specifically configuring ACTRLD to 1, not triggering an interrupt, and setting to an immediate refresh mode, specifically configuring TCLD10 to 11.

d. The sampling calculation interrupts the specific algorithm implementation sequence: sampling, current loop calculation, loading of a T3 timer register, phase locking, bus voltage loop calculation, other operations and interruption ending.

e. The running time of the algorithm in the interrupt of the measurement sampling calculation is as follows: the 'sampling-current loop calculation-loading of the T3 timer register' results in a running time Δ T.

Specifically, an IO port may be provided, IO is set to high at the sampling start, IO is set to low after a T3 timer register is loaded, an oscilloscope is used to test the time Δ T of the high level, and a formula is used: Δ t 75 gets the delay value N corresponding to the DSP.

f. The event manager of 28335 is configured to set the T1 timer to lead the T3 timer Δ T time.

Specifically setting: t1CNT is 3750-N; t3CNT is 0.

And d, outputting PWM driving waves by a PWM pin corresponding to the T3 timer to drive the IGBT.

Claims

1. A digital control method without control delay based on DSP is characterized by comprising the following steps:

d. and a PWM pin corresponding to the timer T3 outputs PWM driving waves.

2. The DSP-based digital control method without control delay of claim 1, wherein: in the topological structure of the main circuit, a voltage type converter adopts an IGBT, and a direct current bus adopts an electrolytic capacitor.

3. The DSP-based digital control method without control delay of claim 1, wherein: the timing periods of the timer T1 and the timer T3 are both set to 0.05 us.

4. The DSP-based digital control method without control delay of claim 1, wherein: the DSP is TMS320F28335 from Ti company.