CN108121625A - The method that data are obtained during error - Google Patents
The method that data are obtained during error Download PDFInfo
- Publication number
- CN108121625A CN108121625A CN201611083401.3A CN201611083401A CN108121625A CN 108121625 A CN108121625 A CN 108121625A CN 201611083401 A CN201611083401 A CN 201611083401A CN 108121625 A CN108121625 A CN 108121625A
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- CN
- China
- Prior art keywords
- processor
- data
- obtained during
- exception
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
- G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The present invention provides during a kind of error obtain data method in, when first processor exception, by one communicate with the first processor shared drive second processor export the first processor exception when data.Using flexible, and suitable for arbitrary scene.Such as in no hardware interface and in the case of LOG printings can not being carried out.Meanwhile first processor run fly in the case of, can also directly by second processor export first processor run fly when data, and then can be abnormal to first processor the reason for analyze.
Description
Technical field
The present invention relates to the methods that data are obtained during a kind of field of embedded technology, especially error.
Background technology
Intelligent terminal generally comprises application processor (AP cores) and baseband processor (CP cores).In general, the tune of AP sides
Trial work section is enriched, and the debugging method of CP sides is limited.When there is its identifiable mistake in CP sides, such as ABORT, PREFECH
And ASSERT, when exception, usual CP cores can monitor, and be handled into corresponding operating mode.And for CP cores
It is run caused by undetectable exception, such as endless loop and various reasons winged etc..Not only CP can not be detected these exceptions, and
And it can not also be handled by software.
Currently, the method that emulator is debugged or LOG is printed is included for these abnormal common debugging methods.But
When intelligent terminal does not have hardware debugging interface, is, for example, JTag mouthfuls, can not be debugged using emulator (trace32).It is right
It runs and flies caused by various reasons, LOG printings can not also export useful information.
The content of the invention
It is an object of the invention to provide a kind of methods that data are obtained during error, are flown with obtaining the endless loop of CP sides or running
When data.
In order to achieve the above object, the present invention provides a kind of method that data are obtained during error, when a first processor
When abnormal, by it is at least one can control the first processor second processor export the first processor exception when
Data.
Preferably, in the method that data are obtained in above-mentioned error, described first is exported by the second processor
The step of data during processor exception, includes：
One preset debugging routine is write by the second processor；
The second processor resets the first processor, and the first processor is guided to perform the preset debugging
Program, the preset debugging routine export the data during first processor exception.
Preferably, in the method that data are obtained in above-mentioned error, the preset debugging routine is the described first processing
The executable file that can be performed.
Preferably, in the method that data are obtained in above-mentioned error, the preset debugging routine is stored in described first
The specified region of processor.
Preferably, in the method that data are obtained in above-mentioned error, the preset debugging routine passes through a channel unit
Data export during by the first processor exception.
Preferably, in the method that data are obtained in above-mentioned error, the channel unit includes：SPI、USB、UART、
Bridge and shared drive.
Preferably, in the method that data are obtained in above-mentioned error, the first processor is baseband processor.
Preferably, in the method that data are obtained in above-mentioned error, the first processor includes ARM and DSP.
Preferably, in the method that data are obtained in above-mentioned error, at least one second processor is at application
Manage device.
Preferably, in the method that data are obtained in above-mentioned error, the second processor includes ARM and DSP.
In error provided by the invention obtain data method in, when first processor exception, by one with it is described
The second processor of first processor shared drive communication exports the data during first processor exception.Using flexible, and
And suitable for arbitrary scene.Such as in no hardware interface and in the case of LOG printings can not being carried out.Meanwhile at first
It manages in the case that device runs and fly, can also first processor directly be exported by second processor and run data when flying, and then can be with
The reason for abnormal to first processor, is analyzed.
Description of the drawings
Fig. 1 is the flow chart for exporting data when first processor malfunctions in the embodiment of the present invention by second processor.
Specific embodiment
The specific embodiment of the present invention is described in more detail below in conjunction with schematic diagram.According to description below and
Claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is using very simplified form and
Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
An embodiment of the present invention provides a kind of methods that data are obtained during error, when a first processor exception, pass through
The second processor of at least one controllable first processor exports the data during first processor exception.It needs
Exception bright, that the first processor is occurred can not only monitor in itself including the first processor oneself
It is abnormal, further include the exception that the first processor cannot monitor oneself.
Wherein, the first processor is baseband processor CP, including but not limited to ARM (Acorn RISC Machine,
Risc microcontroller) and DSP, the embodiment of the present invention be not limited thereto.The second processor is application processor AP, is wrapped
Include but be not limited to ARM (Acorn RISC Machine, risc microcontroller) and DSP, the embodiment of the present invention not as
Limit.It should be noted that the second processor can control the first processor, specifically, the second processor energy
The first processor is enough controlled to be resetted and be able to access that the memory for storing the first processor startup program.
By the second processor export the first processor exception when data the step of comprise the following steps：It is logical
It crosses the second processor and writes a preset debugging routine；The second processor resets the first processor, and guides institute
It states first processor and performs the preset debugging routine, to export the data during first processor exception.
Specifically, as shown in Figure 1, Fig. 1 malfunctions to export first processor by second processor in the embodiment of the present invention
When data flow chart.
Step S1：One preset debugging routine is write by the second processor.
Specifically, the second processor AP is managed MODEM as peripheral hardware, and behaviour can be written and read to it
Make.Preset debugging code is write on the MODEM by the second processor AP, and is compiled and is connected as a preset tune
Try program.The preset debugging routine is the executable file that the first processor CP can be performed.
The preset debugging routine is downloaded to the specified region of the first processor CP by the second processor AP.I.e.
The preset debugging routine is write by the second processor AP.
Step S2：The second processor resets the first processor, and guides described in the first processor execution
Preset debugging routine, to export the data during first processor exception.
Specifically, the characteristic resetted using the first processor CP, i.e., set, the first processor CP by resetting
Can be reset to a fixed position, the inherent characteristic for being reset to the first processor CP, the fixed position with it is described
The hardware feature of first processor CP is related.And the fixed position is the initial position when first processor starts.Institute
It states second processor AP and the first processor CP is reset to the fixed position, the first processor CP is then guided to hold
The row preset debugging routine, data export when the preset debugging routine is by the first processor CP exceptions.
Further, the preset debugging routine by a channel unit by the first processor CP exceptions when data
Export.The channel unit includes but not limited to SPI, USB, UART, bridge and shared drive.And the embodiment of the present invention not with
This is limited.As long as that is, there is the channel unit that can obtain the first processor CP on the first processor CP
Whether data when abnormal can be achieved without having on tube terminal for the hardware interface of debugging.
Data during the first processor CP exceptions are stored in storage device, and the storage device includes but not limited to
DDR, TCM and ram in slice, the embodiment of the present invention are not limited.
Then follow up again acquisition the first processor CP exceptions when data analyzed, with reach can be to described
The purpose that first processor CP is analyzed extremely.
To sum up, in the method that data are obtained in error provided in an embodiment of the present invention, when first processor exception, lead to
Cross a data when second processor to communicate with the first processor shared drive exports the first processor exception.Make
With flexible, and suitable for arbitrary scene.Such as in no hardware interface and in the case of LOG printings can not being carried out.Meanwhile
In the case where first processor race flies, data when directly can also run winged by second processor export first processor,
And then can be abnormal to first processor the reason for, is analyzed.
The preferred embodiment of the present invention is above are only, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of technical scheme is not departed from, to the invention discloses technical solution and
Technology contents make the variations such as any type of equivalent substitution or modification, belong to the content without departing from technical scheme, still
Within belonging to the scope of protection of the present invention.
Claims (10)
1. during a kind of error obtain data method, which is characterized in that when a first processor exception, by it is at least one can
Control the data during second processor export first processor exception of the first processor.
2. the method for data is obtained during error as described in claim 1, which is characterized in that export by the second processor
The step of data during the first processor exception, includes：
One preset debugging routine is write by the second processor；
The second processor resets the first processor, and the first processor is guided to perform the preset debugging journey
Sequence, the preset debugging routine export the data during first processor exception.
3. the method for data is obtained during error as claimed in claim 2, which is characterized in that the preset debugging routine is described
The executable file that first processing can perform.
4. the method for data is obtained during error as claimed in claim 2, which is characterized in that the preset debugging routine is stored in
The specified region of the first processor.
5. the method for data is obtained during error as claimed in claim 2, which is characterized in that the preset debugging routine passes through one
Data export when channel unit is by the first processor exception.
6. the method for data is obtained during error as claimed in claim 5, which is characterized in that the channel unit includes：SPI、
USB, UART, bridge and shared drive.
7. the method for data is obtained during error as described in claim 1, which is characterized in that the first processor is at base band
Manage device.
8. the method for data is obtained during error as claimed in claim 7, which is characterized in that the first processor includes ARM
And DSP.
9. the method for data is obtained during error as described in claim 1, which is characterized in that at least one second processor
For application processor.
10. the method for data is obtained during error as claimed in claim 9, which is characterized in that the second processor includes ARM
And DSP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611083401.3A CN108121625A (en) | 2016-11-30 | 2016-11-30 | The method that data are obtained during error |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611083401.3A CN108121625A (en) | 2016-11-30 | 2016-11-30 | The method that data are obtained during error |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108121625A true CN108121625A (en) | 2018-06-05 |
Family
ID=62227259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611083401.3A Pending CN108121625A (en) | 2016-11-30 | 2016-11-30 | The method that data are obtained during error |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112147971A (en) * | 2019-06-28 | 2020-12-29 | 比亚迪股份有限公司 | Electronic door controller, debugging method and device thereof, storage medium and vehicle |
| CN113360326A (en) * | 2020-03-06 | 2021-09-07 | Oppo广东移动通信有限公司 | Debugging log obtaining method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101286125A (en) * | 2007-04-13 | 2008-10-15 | 株式会社瑞萨科技 | Processor system and exception handling method |
| CN101882098A (en) * | 2009-07-10 | 2010-11-10 | 威盛电子股份有限公司 | Microprocessor integrated circuit and correlation debug method |
| CN105653384A (en) * | 2015-12-30 | 2016-06-08 | 惠州市伟乐科技股份有限公司 | Soft-core CPU resetting method and master-slave type system |
| CN105740155A (en) * | 2016-03-09 | 2016-07-06 | 惠州Tcl移动通信有限公司 | Debugging realizing method and system for Modem CPU |
-
2016
- 2016-11-30 CN CN201611083401.3A patent/CN108121625A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101286125A (en) * | 2007-04-13 | 2008-10-15 | 株式会社瑞萨科技 | Processor system and exception handling method |
| CN101882098A (en) * | 2009-07-10 | 2010-11-10 | 威盛电子股份有限公司 | Microprocessor integrated circuit and correlation debug method |
| CN105653384A (en) * | 2015-12-30 | 2016-06-08 | 惠州市伟乐科技股份有限公司 | Soft-core CPU resetting method and master-slave type system |
| CN105740155A (en) * | 2016-03-09 | 2016-07-06 | 惠州Tcl移动通信有限公司 | Debugging realizing method and system for Modem CPU |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112147971A (en) * | 2019-06-28 | 2020-12-29 | 比亚迪股份有限公司 | Electronic door controller, debugging method and device thereof, storage medium and vehicle |
| CN113360326A (en) * | 2020-03-06 | 2021-09-07 | Oppo广东移动通信有限公司 | Debugging log obtaining method and device |
| CN113360326B (en) * | 2020-03-06 | 2023-02-28 | Oppo广东移动通信有限公司 | Debugging log obtaining method and device |
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Application publication date: 20180605 Assignee: Shanghai Li Ke Semiconductor Technology Co., Ltd. Assignor: Leadcore Technology Co., Ltd. Contract record no.: 2018990000159 Denomination of invention: The method that data are obtained during error License type: Common License Record date: 20180615 |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180605 |