CN108109665A - A kind of memory operating method - Google Patents
A kind of memory operating method Download PDFInfo
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- CN108109665A CN108109665A CN201810029753.3A CN201810029753A CN108109665A CN 108109665 A CN108109665 A CN 108109665A CN 201810029753 A CN201810029753 A CN 201810029753A CN 108109665 A CN108109665 A CN 108109665A
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The present invention provides a kind of memory operating methods, and in particular to a kind of operating method of MLC NAND flash storage chips.The read method of programmed method including MLC NAND Flash insertions ECC, MLC NAND Flash insertions ECC；ECC coding/decoding modules are embedded in MLC NAND flash storage chips, in MLC NAND flash storage programming operations, are transferred data to after being encoded to the data to be programmed by ECC encoder in MLC NAND flash storage array elements；During to MLC NAND Flsah memory read operations, the data read from the array element of MLC NAND flash storages read out to I/O mouthfuls after ECC decoder decodes.ECC module is embedded in MLC NAND flash storages, possesses the ability of certain correction read-write corrupt data, so as to largely solve the problems, such as that data are error-prone in the programming of MLC NAND flash storages and read operation, the design complexities of external NAND Flash storage controls are reduced, improve the reliability of MLC NAND flash storage chips.
Description
Technical field
The present invention relates to memory areas, and in particular to a kind of MLC NAND Flash (Multi Level Cell, multilayer
Unit flash memory) memory insertion ECC (Error Correcting Code, error checking and correction) operating method.
Background technology
With the rapid development of electronic information technology, the data of intelligent movable equipment, network data center and server are deposited
Explosive growth is presented in reserves.Data storage the demand of capacity of memory device is constantly driven flash memories rapidly to
The more extensive, direction of more high density, higher reliability is developed.NAND flash storages as non-volatile flash memory chip,
It the features such as high density, large capacity in fields such as electronic system, communication system, computer systems by feat of having obtained widely grinding
Study carefully and apply.However, it is constantly reduced with the characteristic size of integrated circuit technology, the continuous expansion of capacity of memory device, chip
Integrated level higher, the NAND flash storages chip of research and development more capacity becomes the power of memory development.It is existing
Stage, the NAND flash storages chip of mainstream include SLC NAND flash storages and MLC NAND flash storages
Two kinds, each device can only store a bit data in SLC NAND flash storage chips, thus be more likely to low capacity,
The small application scenario of error rate.Although the error rate of data is more than SLC NAND in MLC NAND flash storage chips
Flash storage chip, but each device can store two bits of data, institute in MLC NAND flash storage chips
With in the case of equal areas and with quantity device, the memory capacity of MLC NAND flash storage chips is SLC
Twice of NAND flash storage chips.It can be seen that the application scenario of MLC NAND Flash is more extensive.
In MLC NAND Flash, since it is there are four types of threshold value distribution, therefore it is being programmed, is being easy in reading process
There is Data flipping, cause data reading and writing mistake.In addition, answering for the high performance requirement such as field of aerospace, military domain
With field, there is more stringent high reliability request to MLC NAND flash storages chip, therefore, develop high reliability
MLC NAND flash storages chip become memory area important research.Improving the same of memory data reliability
When, there should be certain control to chip area, and need to ensure programming, the efficient execution of read access algorithm, become MLC
The technological difficulties in NAND flash storages field.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of memory operating method, are stored in MLC NAND Flash
Device chip is embedded in ECC coding-decoding circuits, and during to MLC NAND flash storage programming operations, the data to be programmed pass through
It is transferred data to after ECC encoder coding in MLC NAND flash storage arrays；To MLC NAND flash storages
During read operation, the data read from the array of MLC NAND flash storages read out to I/O after ECC decoder for decoding
Mouthful.ECC coding/decoding modules are embedded in MLC NAND flash storages, the ability for possessing certain correction read-write corrupt data,
So as to largely solve the problems, such as that data are error-prone in programming and read operation to MLC NAND flash storages, greatly
The big reliability for improving MLC NAND flash storage chips, reduces the design of external NAND Flash storage controls
Complexity well solves the technical bottleneck of memory data reliability in the prior art.The present invention proposes storage operation side
Method embedded ECC coding-decoding circuits in MLC NAND flash storages, had not only met the requirement to chip area, but also had realized embedding
Enter programming, the efficient execution of read operation algorithm of ECC, solve the problems, such as the compromise of area and reliability to a certain extent.
In order to solve the above technical problems, the technical solution adopted by the present invention is：
A kind of memory operating method is provided, including programmed method, is specifically included：
Send the instruction of period 1 programming operation；
Write the MLC NAND flash storages address to be programmed；
The page data to be programmed is write, the page data of programming is sent to embedded ECC programmed circuits module, using insertion
ECC programmed circuit moulds ECC encoder circuit in the block is completed to encode the page data to be programmed；
Send the instruction of second round programming operation；
Page data after ECC encoder encodes is sent to the caching of page circuit of MLC NAND flash storages, completes
To the caching of page data；
The data stored in caching of page circuit are programmed in MLC NAND flash storage arrays.
The embedded ECC programmed circuits module, including：
ECC encoder circuit is sent to the page data of the MLC of being programmed to NAND flash storage arrays；
ECC encoder circuit encodes page data, and generates data bit and check bit；
Programmed state machine circuit control data is called to be programmed to MLC NAND flash storage arrays.
The data stored in the circuit by caching of page are programmed to MLC NAND flash storage arrays, and programming includes
Low order LSB data program and the programming of high significance bit MSB data：
The programming of low order LSB data is carried out first, by the low order LSB of the page data cached in caching of page circuit
Data are programmed to MLC NAND flash storage arrays；
After treating the programming of low order LSB data, low order LSB data are read；
The data of high significance bit MSB are loaded into from caching of page circuit again, with reference to the low order LSB data of reading, by height
Significance bit MSB data is programmed to MLC NAND flash storage arrays.
The low order LSB data programming includes：
Step 1：The low order LSB data for needing to program are loaded into register, and judge low order LSB data
It is 1 or 0, if 1, then the electricity that the bit line application size of the array device in MLC NAND flash storages is VDD
Source voltage；If 0, then the voltage that the bit line application size of the array device in MLC NAND flash storages is 0V；
Step 2：Apply initial programming voltage in the wordline of MLC NAND flash storage array devices, treat MLC NAND
After the completion of the wordline initial voltage and bit-line voltage of array device in flash storage all apply, to MLC NAND Flash
The wordline of memory array device applies staged pulse voltage；
Step 3：Apply a staged pulse voltage, after a complete step pulse voltage to be applied, carry out one-time programming
Verification operation；
Step 4：Until judging whether low order LSB data are programmed in the range of low order LSB data thresholds, if compiling
In the range of journey to low order LSB data thresholds, then low order programs successfully, otherwise continues to execute step 3 and its afterwards
Step.
The high significance bit MSB data programming includes：
Step 1：Low order LSB data are read, with reference to the low order LSB data of reading, are loaded into what is programmed
High significance bit MSB data；
Step 2：Apply staged pulse voltage in the wordline of MLC NAND flash storage array devices；
Step 3：Often apply a staged pulse voltage and carry out one-time programming verification operation, until completing to high significance bit
Until MSB data is programmed in supreme significance bit MSB data threshold range.
The programming verification operation includes：
Step 1：Apply verifying voltage VVFY；
Step 2：Programming validation status machine circuit is called to verify the data of programming；
Step 3：Judge whether data reach the threshold value state to be programmed；
Step 4：If reaching the threshold value state scope of programming, success is programmed, if the not up to threshold value state scope of programming, is compiled
Journey fails.
A kind of memory operating method including read method, specifically includes：
Period 1 reading order is sent, read operation is in units of page；
Write-in needs to read the address of MLC NAND flash storage arrays；
Send the reading order of second period；
The data in MLC NAND flash storage arrays are read to caching of page circuit；
The page data read out is sent to ECC decoder circuit modules by caching of page circuit；
ECC decoders decode page data；
Judge whether the data after decoding are wrong, if wrong, ECC decoder circuits if error-free, hold page data error correction
Row is in next step；
Data after decoding are sent to MLC NAND flash storage interfaces.The reading MLC NAND Flash are deposited
Data in memory array include reading low order LSB data and high significance bit MSB data to caching of page circuit：
Low order LSB data are read first, apply initial voltage VREAD1Voltage read erasing E states and D1 states it is low effectively
Position LSB data；
Apply VREAD3Voltage reads the low order LSB data of D2 states and D3 states；
Judge whether to read high significance bit MSB data at this time, if only needing to read low order LSB data, complete MLC
NAND flash storage read operations；To read high significance bit MSB data, then V is added inREAD3Voltage reads high significance bit
MSB data.
Compared with prior art, the beneficial effects of the invention are as follows：MLC NAND flash storages are being programmed and are being read
During operation, embedded ECC coding/decoding module circuits are meeting certain hardware circuit expense, possess certain correction and read
The ability of corrupt data is write, so as to largely solve that MLC NAND flash storages are counted in programming and read operation
According to it is error-prone the problem of, substantially increase the reliability of MLC NAND flash storage chips, reduce external NAND
The design complexities of Flash storage controls.MLC NAND Flash proposed by the present invention are embedded in ECC operation method in MLC
Not only met the requirement to chip area in NAND flash storages, but realize embedded ECC to program, read operation algorithm
It efficiently performs, so as to solve the problems, such as the compromise of area and reliability to a certain extent.
Description of the drawings
Fig. 1 MLC NAND flash storages insertion ECC installation drawings according to an embodiment of the invention.
Fig. 2 MLC NAND flash storages threshold value distribution maps according to an embodiment of the invention.
Fig. 3 MLC NAND flash storages insertion ECC programming operation Organization Charts according to an embodiment of the invention.
Fig. 4 MLC NAND flash storages insertion ECC programming operation flow charts according to an embodiment of the invention.
The LSB programming operation flows of Fig. 5 MLC NAND flash storages insertion ECC according to an embodiment of the invention
Figure.
The MSB programming operation flows of Fig. 6 MLC NAND flash storages insertion ECC according to an embodiment of the invention
Figure.
Fig. 7 MLC NAND flash storages insertion ECC read operation Organization Charts according to an embodiment of the invention.
Fig. 8 MLC NAND flash storages LSB according to an embodiment of the invention and MSB data threshold value distribution map.
Fig. 9 MLC NAND flash storages insertion ECC read operation flow charts according to an embodiment of the invention.
The erasing operation flow of Figure 10 MLC NAND flash storages insertion ECC according to an embodiment of the invention
Figure.
Specific embodiment
Specific embodiment below represents exemplary embodiment of the present invention, and substantially merely illustrative explanation rather than
Limitation.In the description, refer to that " one embodiment " or " embodiment " means to combine the described specific spy of the embodiment
Sign, structure or characteristic are included at least one embodiment of the present invention.In addition, those of ordinary skill in the art should manage
It solves, the memory particle used in the embodiment of the present invention is MLC NAND flash storages.MLC NAND Flash(Multi-
Level Cell, multi-layered unit flash memory) device cell in memory in memory area refers to a NAND Flash array
Storage can store two bits, i.e., threshold value is distributed there are four types of it.Memory operating method of the present invention is included to storage
The programmed method and read method of device.In MLC NAND flash storages chip internal insertion ECC (Error Correcting
Code, error checking and correction) circuit, for NAND flash storages program and read operation in it is error-prone the characteristics of,
ECC circuit can be corrected in the data for programming with malfunctioning in read operation, on the premise of hardware area requirement is met so as to very
Big degree improves the reliability of MLC NAND flash storage chips.Technical solution proposed by the present invention using the present embodiment as
Example illustrates, which not just limits MLC NAND flash storage chips, for other kinds of
NAND flash storages such as SLC (Single Level Cell, single layer cell flash memory) NAND Flash flash chips and TLC
(Triple-Level Cell) NAND Flash flash chips are equally applicable.
The present invention is further illustrated with reference to the accompanying drawings and detailed description.
The operating method of the MLC NAND flash storages insertion ECC of the present invention includes MLC NAND flash storages
The programmed method of embedded ECC realizes that the read method of MLC NAND flash storages insertion ECC is realized.MLC NAND
During flash storage programming operation, data to be programmed are encoded by ECC by the insertion ECC programmed circuits module of the present invention
After device coding, generate data bit and check bit is sent to caching of page circuit jointly, then the data in caching of page are programmed to MLC
In NAND flash storage arrays, programming operation is realized.It is embedding by the present invention during MLC NAND flash storage read operations
Enter ECC reading circuits module and realize the data read from array to caching of page circuit, caching of page circuit by the data bit of reading and
Check bit is sent to ECC decoder circuits jointly, is decoded by ECC decoder circuits, and decoded data are sent to IO
Mouthful.The characteristics of for MLC NAND Flash random error easily occurs for embedded ECC coding/decoding modules, is compiled using BCH code
Decoding, realize every 4096 data can 8 data of error correction, and hardware circuit is smaller, so as to largely solve pair
MLC NAND flash storages are programming the problem of error-prone with data in read operation, improve MLC NAND Flash and deposit
The reliability of reservoir flash chip reduces the design difficulty of NAND Flash peripheral controllers circuits.Details are as follows：
Referring to Fig. 1, it is the installation drawing that MLC NAND flash storages are embedded in ECC, is stored including MLC NAND Flash
Device array circuit, for the medium as storage data.The left and right connection row respectively of MLC NAND flash storage array circuits
Decoder circuit and column decoder circuitry, for programming, reading, the row ground of erasing operation to MLC NAND flash storages
Location, column address are sent to the specified region of MLC NAND flash storage arrays into row decoding；In MLC NAND Flash
Caching of page circuit is connected to below memory array circuit, caching of page circuit is used in programming operation, through ECC coding modules
Generated data bit and check bit carry out data buffer storage, final page buffer circuit after middle encoder circuit encodes programming data
The data bit of whole page and check bit one are removed into brush into MLC NAND flash storage arrays, realize that data are stored to MLC
In NAND Flash flash memories；In read operation, data are read in units of page from MLC NAND flash storage arrays
Position and check bit are cached into caching of page circuit, then, the page of data position cached in caching of page and check bit are sent to embedding
Enter the reading circuit module of ECC, the page of data (including data bit and check bit) of caching of page is translated through ECC decoder circuits
Code, and reading state electromechanics road is called to realize that data read out to the algorithm control of I/O port whole process simultaneously, most read at last
Data are sent to I/O interfaces.The memory array cell circuit, row decoder circuits, column decoder circuitry, caching of page
Circuit, logic control circuit and I/O interface are all made of integrated circuit.The programmed circuit module of embedded ECC includes in Fig. 1：
ECC encoder circuit, programmed state machine circuit, wherein, ECC encoder circuit is for encoding programming data, coding production
Raw data bit and check bit are sent to together in caching of page circuit；Programmed state machine circuit control data are programmed to from I/O port
All operationss algorithm control in MLC NAND Flash array circuits；The reading circuit module of embedded ECC includes in Fig. 1：ECC
Decoder circuit, reading state electromechanics road, wherein ECC decoder circuits are read for being decoded to the data in caching of page
State machine circuit controls all operationss algorithm control of the data from MLC NAND flash storages arrays to I/O port.It is patrolled in Fig. 1
It collects control circuit and further includes peripheral high-voltage control circuit, erase status electromechanics road.Peripheral high-voltage control circuit is used for MLC
When NAND Flash programmings, reading and erasing operation, the required control for applying high pressure to MLC NAND Flash arrays.Fig. 1
In erase status electromechanics road realize to the block region of specified MLC NAND flash storage arrays carry out erasing control behaviour
Make.
It is MLC NAND flash storage threshold value distribution maps, programming operation is substantially exactly to store a charge in referring to Fig. 2
In floating boom, so that threshold voltage increases, since each device of MLC NAND flash storages can store 2 bit numbers
According to, therefore with 4 kinds of threshold values shown in Fig. 2 distribution.As shown in Fig. 2, E states for erasing state, D1, D2, D3 states be respectively three kinds not
Same programming thresholds state.Homomorphism has not divided MLC NAND Flash threshold regions to E states, D1 states, D2 states, D3 states this four.By
Different verifying voltage V is needed in different programmed threshold voltage rangesVFY1, VVFY2, VVFY3To verify whether to be programmed into setting
Threshold value state, the V in Fig. 2READ1Voltage, VREAD2Voltage, VREAD3Voltage is respectively to read the voltage that different data is applied.MLC ratios
SLC capacity is big, but its narrower threshold value distribution also proposes its reliability harsh requirement, therefore is directed to the problem,
ECC coding-decoding circuits are embedded in MLC NAND flash storage flash chips by a kind of memory operating method of the present embodiment
In have high reliability.
Referring to Fig. 3, ECC programming operation Organization Charts are embedded in for MLC NAND flash storages, what is be sequentially connected in Fig. 3 is
NAND Flash arrays, caching of page circuit, programmed state machine circuit, I/O interface, wherein NAND Flash arrays or so respectively connect
Row decoding circuit, array decoding circuit, the peripheral high-voltage control circuit of programmed state machine circuit connection.Programmed state machine circuit includes compiling
Journey verifies circuit, and programming verification circuit is used to verify whether different programmed state data are programmed in corresponding threshold range.MLC
NAND flash storages are programmed in units of page, and page of data to be programmed is sent to embedded ECC and programmed by I/O interface circuit
In circuit module, the size of page of data is 2KB, and generation data are encoded by ECC encoder circuit module per 512Byte data
Position and check bit by the coding of 4 512Byte data, then complete the data encoding of one page, meanwhile, pass through and call embedded ECC
Programmed circuit mould programmed state machine circuit control programmed algorithm flow in the block is effectively carried out the coding and programmed algorithm of data
Operation.Its peripheral high-tension circuit is supplied to MLC NAND flash storage array word line voltages for required in programming operation
Control.Meanwhile the data bit and check bit generated after ECC encoder encodes is sent to together in caching of page circuit, is being incited somebody to action
The address location specified into MLC NAND flash storage arrays is brushed under page of data in caching of page circuit, completes programming
Operation.ECC coding modules are embedded in programmed algorithm shown in Fig. 3 to improve the reliability of programming data.Programming state is electromechanical
The control of entire programmed algorithm is realized on road, is called in a manner that programmed algorithm is nested come implementation levelization, so design the advantages of
It is to make whole system orderliness clear and efficiency can be improved.
Referring to Fig. 4, ECC programming operation flow charts, MLC NAND Flash are embedded in for MLC NAND flash storages
Memory programming method includes：
Step 1：Send the instruction of period 1 programming operation；
Step 2：Write the MLC NAND flash storages address to be programmed；
Step 3：The page data to be programmed is write, the page data of programming is sent to embedded ECC programmed circuits module, is adopted
It completes to encode the page data to be programmed with embedded ECC programmed circuit moulds ECC encoder circuit in the block；
Step 4：Send the instruction of second round programming operation；
Step 5：Page data after ECC encoder encodes is sent to the caching of page electricity of MLC NAND flash storages
The caching to page data is completed on road；
Step 6：The data stored in caching of page circuit are programmed in MLC NAND flash storage arrays.Wherein,
The embedded ECC programmed circuits module is as shown in figure 3, specifically include：
1st, ECC encoder circuit is sent to the page data of the MLC of being programmed to NAND flash storage arrays；
2nd, ECC encoder circuit encodes page data, and generates data bit and check bit；
3rd, the coding and data for calling programmed state machine circuit control data are programmed to MLC NAND flash storage battle arrays
Row.
Shown in Figure 8, MLC NAND Flash are programmed with 4 kinds of threshold value states, write low order LSB data first, will
Brush is treated to MLC NAND flash storage arrays under the low order LSB data of the page data cached in caching of page circuit
After low order LSB data program, low order LSB data are read out；It is loaded into again from caching of page circuit high effectively
The data of position MSB, that completes high significance bit MSB data is programmed to MLC NAND flash storage arrays, is finally completed MLC
The programming operation of NAND flash storages.Referring to Fig. 3, the data that are issued to instructed from a cycle programming operation are programmed to
In MLC NAND flash storage arrays, all algorithms have the programmed circuit mould programmed state machine in the block of embedded ECC
Circuit control is realized.After the data stored in the circuit by caching of page are programmed to MLC NAND flash storage arrays,
Programming includes the programming of low order LSB data and the programming of high significance bit MSB data, specifically includes：
1st, the programming of low order LSB data is carried out first, by the low order of the page data cached in caching of page circuit
LSB data are programmed to MLC NAND flash storage arrays；
2nd, after treating the programming of low order LSB data, low order LSB data are read；
3rd, the data of high significance bit MSB are loaded into from caching of page circuit again, it, will with reference to the low order LSB data of reading
High significance bit MSB data is programmed to MLC NAND flash storage arrays.
Referring to Fig. 5, the LSB programming operation flow charts of ECC are embedded in for MLC NAND flash storages, as shown in Figure 4, are treated
Programming data is stored in caching of page circuit after ECC module encodes, and caching of page circuit splits data into low order LSB data
Programming and high significance bit MSB are programmed in MLC NAND flash storage arrays, and wherein low order LSB programmings include：
Step 1：The low order LSB data for needing to program are loaded into register, and judge low order LSB data
It is 1 or 0, if 1, then the electricity that the bit line application size of the array device in MLC NAND flash storages is VDD
Source voltage；If 0, then the voltage that the bit line application size of the array device in MLC NAND flash storages is 0V；
Step 2：Apply initial programming voltage in the wordline of MLC NAND flash storage array devices, treat MLC NAND
After the completion of the wordline initial voltage and bit-line voltage of array device in flash storage all apply, to MLC NAND Flash
The wordline of memory array device applies staged pulse voltage；
Step 3：Apply a staged pulse voltage, after a complete step pulse voltage to be applied, carry out one-time programming
Verification operation；
Step 4：Until judging whether low order LSB data are programmed in the range of low order LSB data thresholds, if compiling
In the range of journey to low order LSB data thresholds, then low order programs successfully, otherwise continues to execute step 3 and its afterwards
Step.
Referring to Fig. 6, the MSB programming operation flow charts of ECC are embedded in for MLC NAND flash storages, treat low order
After the completion of LSB programmings, high significance bit MSB data programming is performed, including：
Step 1：Low order LSB data are read, with reference to the low order LSB data of reading, are loaded into what is programmed
High significance bit MSB data；
Step 2：Apply staged pulse voltage in the wordline of MLC NAND flash storage array devices, wherein, rank
The ladder step value of ladder type pulse voltage is controlled by STEP_CNT；
Step 3：Often apply a staged pulse voltage and carry out one-time programming verification operation, until completing to high significance bit
MSB data programs.MLC NAND flash storage read operations are carried out in units of page, as shown in Fig. 2, MLC NAND
One device of flash storage can store two bits of data, and wherein E is erasing state, and D1, D2, D3 is three kinds of different programmings
State due to read four kinds of different threshold value states, then needs to apply three reading voltage VREAD1, VREAD2, VREAD3Four could be read
The corresponding threshold value state of kind.MLC NAND flash storages are in read operation due to reading interference and NAND flash storage battle arrays
The influence of row, it is easy to Data flipping occur, cause corrupt data.Therefore in order to solve this problem, in MLC NAND
Embedded ECC algorithm module in Flash read operations, realizes that every 4096 bit data corrects 8 bit datas.
It is shown in Figure 7, it is embedded in ECC read operation Organization Charts, MLC NAND for MLC NAND flash storages
Flash storage array circuit is left and right to connect row decoder circuits and column decoder circuitry respectively, for MLC NAND
Flash storage programming, reading, the row address of erasing operation, column address are sent to MLC NAND Flash and deposit into row decoding
The specified region of memory array；The then caching of page circuit in succession below MLC NAND flash storage array circuits, is used for
In resume studies extract operation, the page of data of MLC NAND flash storage arrays is kept in caching of page circuit.Phase successively
What is connected is embedded ECC reading circuits, and the reading circuit of embedded ECC includes ECC decoder circuits, for being carried out to the data of reading
Decoding realizes that every 4096 bit data can correct 8 bit datas and reading state electromechanics road, and reading behaviour is realized for controlling
Make algorithm.Peripheral high-tension circuit reads required high pressure for providing.During read operation, when sending reading order, embedded ECC
The reading state electromechanics road of reading circuit calls and accordingly reads algorithm, and page of data in MLC NAND Flash arrays is read
Into caching of page circuit, the page of data in caching of page circuit is divided 4 times and is sent to the decoding of ECC decoder circuit module, this is translated
Code module can realize the correcting data error to reading, error correcting capability 8bits/4096bits, the data transmission after most decoding at last
To I/O mouthfuls of output terminal.Complete the read operation of MLC NAND Flash.
Referring to Fig. 9, ECC read operation flow charts are embedded in for MLC NAND flash storages, MLC NAND Flash's
Read operation includes reading low order LSB data and high significance bit MSB data, has referring to Fig. 8 for MLC NAND Flash are low
Position LSB and the distribution of high significance bit MSB data are imitated, it is specific as follows：
Read operation sends period 1 reading order in units of page；
Write-in needs to read the address of MLC NAND flash storage arrays；
After being write after address, the reading order of second period is sent, MLC NAND flash storages, which are called, reads shape
The data read operation in MLC NAND flash storage arrays is completed on state electromechanics road；State machine circuit to be read will be read
After operative algorithm is finished, data from array under brush and cached in caching of page circuit；
The page data read out is sent to ECC decoder circuits module and completes decoding by caching of page circuit, after decoding
Data be sent to MLC NAND flash storage interfaces, be finally completed the read operation of MLC NAND flash storages.
Data are read in the wherein described NAND flash storage arrays from MLC to be included reading low order LSB data and high significance bit
MSB data：Low order LSB data are read first, apply initial voltage VREAD1Voltage read erasing E states and D1 states it is low effectively
Position LSB data, then apply VREAD3Voltage reads the low order LSB data of D2 states and D3 states, completes low order LSB data
Reading；Judge whether to read high significance bit MSB data at this time, if only needing to read low order LSB data, complete MLC
NAND flash storage read operations；To read high significance bit MSB data, then V is added inREAD2Voltage reads high significance bit
MSB data completes the read operation of MLC NAND flash storages；
Referring to Figure 10, the erasing operation flow chart of ECC is embedded in for MLC NAND flash storages, details are as follows：
Erasing operation sends period 1 erasing order in units of block；
Write-in needs to wipe the block address of MLC NAND flash storage arrays；
Send second period erasing order；
Using FN tunneling mechanisms, the erasing block in MLC NAND flash storage arrays is chosen, starts erase status machine
Circuit；Wherein, the erase status electromechanics road realizes that method for deleting includes：
Step 1：Apply 0V voltages in the word line end of MLC NAND flash storage array devices, in MLC NAND
The substrate terminal of flash storage array device applies initial erasing voltage；
Step 2：Carry out block erasing；
Step 3：Erasing operation is verified；
Step 3：Judge erasing whether by if by completing erasing operation；Continue if not passing through in MLC NAND
The substrate terminal of flash storage array applies stairstepping pulse voltage and carries out erasing operation, often increases staged pulse electricity
Pressure, erasing staged pulse voltage step value control ERS_CNT add 1；
Step 4：Into whether be wipe staged pulse voltage step value ERS_CNT maximums judgement, if ERS_CNT reaches
To maximum, then this erasing operation failure；If ERS_CNT is not up to maximum, step 2 and its later step are continued to execute
Suddenly.Complete the erasing operation of MLC NAND flash storages insertion ECC.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention rather than is limited,
Although the present invention is described in detail with reference to preferred embodiments, it will be understood by those of ordinary skill in the art that：Its according to
Technical scheme can be so modified or replaced equivalently, and these modifications or equivalent substitution cannot also make to repair
Technical solution after changing departs from the spirit and scope of technical scheme.
Claims (8)
1. a kind of memory operating method, including programmed method, which is characterized in that the programmed method specifically includes：
Send the instruction of period 1 programming operation；
Write the MLC NAND flash storages address to be programmed；
The page data to be programmed is write, the page data of programming is sent to embedded ECC programmed circuits module, using embedded ECC
Programmed circuit mould ECC encoder circuit in the block is completed to encode the page data to be programmed；
Send the instruction of second round programming operation；
Page data after ECC encoder encodes is sent to the caching of page circuit of MLC NAND flash storages, completes to page
The caching of data；
The data stored in caching of page circuit are programmed in MLC NAND flash storage arrays.
2. memory operating method as described in claim 1, which is characterized in that the embedded ECC programmed circuits module, bag
It includes：
ECC encoder circuit is sent to the page data of the MLC of being programmed to NAND flash storage arrays；
ECC encoder circuit encodes page data, and generates data bit and check bit；
Programmed state machine circuit control data is called to be programmed to MLC NAND flash storage arrays.
3. memory operating method as described in claim 1, which is characterized in that the data stored in the circuit by caching of page
MLC NAND flash storage arrays are programmed to, programming includes the programming of low order LSB data and high significance bit MSB data
Programming：
The programming of low order LSB data is carried out first, by the low order LSB data of the page data cached in caching of page circuit
It is programmed to MLC NAND flash storage arrays；
After treating the programming of low order LSB data, low order LSB data are read；
The data of high significance bit MSB are loaded into from caching of page circuit again, it, will be high effectively with reference to the low order LSB data of reading
Position MSB data is programmed to MLC NAND flash storage arrays.
4. the operating method of memory as claimed in claim 3, which is characterized in that the low order LSB data programming bag
It includes：
Step 1：The low order LSB data for needing to program are loaded into register, and judge that low order LSB data are 1
Or 0, if 1, then the power supply electricity that the bit line application size of the array device in MLC NAND flash storages is VDD
Pressure；If 0, then the voltage that the bit line application size of the array device in MLC NAND flash storages is 0V；
Step 2：Apply initial programming voltage in the wordline of MLC NAND flash storage array devices, treat MLC NAND
After the completion of the wordline initial voltage and bit-line voltage of array device in flash storage all apply, to MLC NAND Flash
The wordline of memory array device applies staged pulse voltage；
Step 3：Apply a staged pulse voltage, after a complete step pulse voltage to be applied, carry out one-time programming verification
Operation；
Step 4：Until judging whether low order LSB data are programmed in the range of low order LSB data thresholds, if being programmed to
In the range of low order LSB data thresholds, then low order programs successfully, otherwise continue to execute step 3 and its afterwards the step of.
5. memory operating method as claimed in claim 3, which is characterized in that the high significance bit MSB data programming includes：
Step 1：Low order LSB data are read, with reference to the low order LSB data of reading, being loaded into the height to be programmed has
Imitate position MSB data；
Step 2：Apply staged pulse voltage in the wordline of MLC NAND flash storage array devices；
Step 3：Often apply a staged pulse voltage and carry out one-time programming verification operation, until completing to high significance bit MSB
Until data are programmed in supreme significance bit MSB data threshold range.
6. the operating method of memory as described in claim 4 or 5, which is characterized in that the programming verification operation includes：
Step 1：Apply verifying voltage VVFY；
Step 2：Programming validation status machine circuit is called to verify the data of programming；
Step 3：Judge whether data reach the threshold value state to be programmed；
Step 4：If reaching the threshold value state scope of programming, success is programmed, if the not up to threshold value state scope of programming, programs mistake
It loses.
7. a kind of memory operating method, including read method, which is characterized in that the read method specifically includes：
Period 1 reading order is sent, read operation is in units of page；
Write-in needs to read the address of MLC NAND flash storage arrays；
Send the reading order of second period；
The data in MLC NAND flash storage arrays are read to caching of page circuit；
The page data read out is sent to ECC decoder circuit modules by caching of page circuit；
ECC decoders decode page data；
Judge whether the data after decoding are wrong, if wrong, ECC decoder circuits are to page data error correction, if error-free, under performing
One step；
Data after decoding are sent to MLC NAND flash storage interfaces.
8. memory operating method as claimed in claim 7, which is characterized in that the reading MLC NAND flash storages
Data in array are to caching of page circuit, including reading low order LSB data and high significance bit MSB data：
Low order LSB data are read first, apply initial voltage VREAD1Voltage reads the low order of erasing E states and D1 states
LSB data；
Apply VREAD3Voltage reads the low order LSB data of D2 states and D3 states；
Judge whether to read high significance bit MSB data at this time, if only needing to read low order LSB data, complete MLC
NAND flash storage read operations；To read high significance bit MSB data, then V is added inREAD3Voltage reads high significance bit
MSB data.
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