CN108092704B - Multi-sub-band variable bandwidth repeater - Google Patents
Multi-sub-band variable bandwidth repeater Download PDFInfo
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- CN108092704B CN108092704B CN201611026722.XA CN201611026722A CN108092704B CN 108092704 B CN108092704 B CN 108092704B CN 201611026722 A CN201611026722 A CN 201611026722A CN 108092704 B CN108092704 B CN 108092704B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/155—Ground-based stations
- H04B7/15507—Relay station based processing for cell extension or control of coverage area
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention provides a multi-sub-band variable bandwidth repeater.A baseband signal processing unit of the multi-sub-band variable bandwidth repeater comprises a plurality of processing channels, each processing channel comprises a receiving processing part and an emitting processing part, the receiving processing part comprises a receiving frequency mixing module, a down-sampling module and a signal forming module which are sequentially connected, and the down-sampling module comprises a down-sampling filter or a plurality of down-sampling filters which are connected in cascade; the transmitting and processing part comprises an up-sampling module and a transmitting and frequency mixing module which are sequentially connected, the up-sampling module comprises an up-sampling filter or a plurality of up-sampling filters which are connected in a cascade mode, the number of the up-sampling filters is the same as that of the down-sampling filters, and the up-sampling factors of the up-sampling filters are the same as those of the down-sampling filters. The multi-subband variable bandwidth repeater can process signals of multiple frequency bands, and filters can be multiplexed.
Description
Technical Field
The invention relates to mobile communication, in particular to a multi-sub-band variable bandwidth repeater for mobile communication.
Background
With the rapid development of mobile communication, at present, mobile communication devices need to realize multiband, multi-system and variable bandwidth more and more, if traditional analog hardware is still used to realize multi-system and variable bandwidth communication, the difficulty is increased, the requirement on hardware is higher, and the universality is not strong, for example, hardware circuits need to be changed for frequency conversion.
Therefore, it is desirable to provide a multi-subband variable bandwidth apparatus for communication relay, which can implement multi-system arbitrary variable bandwidth communication without changing hardware circuit.
Disclosure of Invention
The invention aims to provide a multi-subband variable bandwidth repeater, which can realize multi-system communication with any variable bandwidth under the condition of not changing a hardware circuit.
The multi-subband variable bandwidth repeater comprises a baseband signal processing unit, a frequency conversion unit and a frequency conversion unit, wherein the baseband signal processing unit is used for processing a digital signal output from an analog-to-digital conversion circuit and outputting the processed signal to the digital-to-analog conversion circuit for conversion and final emission, the baseband signal processing unit comprises a plurality of processing channels, each processing channel is used for processing a signal with a set frequency and a set bandwidth, each processing channel comprises a receiving processing part and an emitting processing part, the receiving processing part comprises a receiving frequency mixing module, a downsampling module and a signal forming module which are sequentially connected, the receiving frequency mixing module mixes a receiving local oscillator signal of the processing channel with an input signal of the processing channel to generate a zero intermediate frequency signal, and the downsampling module comprises a downsampling filter or a plurality of downsampling filters which are connected in a cascade; the transmission processing part comprises an up-sampling module and a transmission frequency mixing module which are sequentially connected, the up-sampling module comprises an up-sampling filter or a plurality of up-sampling filters which are in cascade connection, the number of the up-sampling filters is the same as that of the down-sampling filters, the up-sampling factors of the up-sampling filters are the same as those of the down-sampling filters, and the transmission frequency mixing module mixes the transmission local oscillation signal of the processing channel with the received signal to generate the output signal of the processing channel.
Further, in order to save space logic resources, the up-sampling factor and the down-sampling factor are both 2, when the down-sampling module includes a plurality of down-sampling filters connected in cascade, at most 2^ (n-1) processing channels with the same sampling rate can multiplex an nth stage of the down-sampling filter, and a plurality of processing channels corresponding to the reception processing part can multiplex an up-sampling filter, where operation 2^ (n-1) represents the power of n-1 of 2, and n is the number of stages of the down-sampling filter.
Preferably, the upsampling filter and the downsampling filter are both half-band filters. The baseband signal processing unit is implemented in an FPGA.
The multi-subband variable bandwidth repeater realizes the digital filters with variable bandwidths of a plurality of processing channels on the same FPGA, can realize the processing of signals of a plurality of frequency bands, and has flexible structure; and a plurality of digital filters can be realized in a multiplexing mode, so that the application of the channel filter is more reasonable, the architecture of the whole digital filter is simpler, the space logic resource is effectively saved, and the operation efficiency is higher.
Drawings
FIG. 1 is a schematic diagram of a downlink structure of a multi-subband variable bandwidth repeater according to the present invention;
FIG. 2 is a schematic diagram of the uplink structure of the multi-subband variable bandwidth repeater according to the present invention;
FIG. 3 is a schematic diagram of the structure of the receiving processing part of the processing channel of the baseband signal processing unit of the multi-subband variable bandwidth repeater according to the present invention;
FIG. 4 is a schematic diagram of the structure of the transmission processing part of the processing channel of the baseband signal processing unit of the multi-subband variable bandwidth repeater according to the present invention;
FIG. 5 is a schematic diagram illustrating an exemplary structure of a receiving processing portion of a processing channel of a baseband signal processing unit of the multi-subband variable bandwidth repeater according to the present invention;
FIG. 6 is a schematic diagram of an exemplary structure of a transmission processing part of a processing channel of a baseband signal processing unit of the multi-subband variable bandwidth repeater according to the present invention.
Detailed Description
The following describes the multi-subband variable bandwidth repeater with reference to the attached drawings and the detailed description, but the present invention is not limited thereto.
FIG. 1 is a schematic diagram of a downlink structure of a multi-subband variable bandwidth repeater according to the present invention. In the downlink, a BS port coupling space multi-system wireless signal enters the medium multi-frequency combiner 101 for signal separation (i.e., separating signals with different bandwidths and different frequencies), then enters the radio frequency analog front-end circuit 102 for signal amplification and filtering, then enters the analog-to-digital conversion circuit 103 for a/D signal conversion, the converted digital signal is sent to the baseband signal processing unit 104 for signal processing, the processed digital signal enters the digital-to-analog conversion circuit 105 for D/a signal conversion, and finally is combined by the radio frequency analog back-end circuit 106 and the medium multi-frequency combiner 107 and then is transmitted and output from an MS port. In the uplink, as shown in fig. 2, a signal received by the MS port sequentially passes through the medium multi-frequency combiner 207, the radio frequency analog front-end circuit 206, and the analog-to-digital conversion circuit 205, and then enters the baseband signal processing unit 204, and a processed digital signal sequentially enters the digital-to-analog conversion circuit 203, the radio frequency analog back-end circuit 202, and the medium multi-frequency combiner 201, and then is transmitted and output from the BS port.
The analog-to- digital conversion circuits 103 and 205 located in the receiving part sample the intermediate frequency signal, and the sampled signal enters the baseband signal processing units 104 and 204 to be processed by digital down-conversion, I/Q demodulation, extraction, filtering and the like; the processed signal is sent to a sending part, and the baseband signal is converted into an intermediate frequency analog signal through digital-to- analog conversion circuits 105 and 203 after interpolation, filtering and I/Q modulation.
The baseband signal processing units 104 and 204 implement functions such as a half-band filter (HBF), a finite-length single-bit impulse response Filter (FIR), and a Numerically Controlled Oscillator (NCO). The filter effectively filters out-of-band signals to meet the index requirement of out-of-band rejection; the digitally controlled oscillator can achieve the purpose of bandwidth conversion by changing the oscillation signal.
Referring to fig. 3 to fig. 6, which are schematic structural diagrams of a baseband signal processing unit of the multi-subband variable bandwidth repeater of the present invention, wherein fig. 3 and 5 show a receiving processing part, and fig. 4 and 6 show a transmitting processing part. Preferably, the baseband signal processing unit is implemented in an FPGA. As shown, the baseband signal processing unit includes a plurality of processing channels (e.g., CH1 to CH14 in fig. 5 and 6), each processing channel being configured to process a signal having a set frequency and a set bandwidth. Each of the processing channels includes a reception processing section (shown in fig. 3 and 5) for processing digital signals output from analog-to-digital conversion circuits (for example, ADC1 to ADC3 in fig. 5) and a transmission processing section (shown in fig. 4 and 6) for outputting signals processed by the reception processing section to digital-to-analog conversion circuits (for example, DAC1 to DAC3 in fig. 6).
The baseband signal processing unit shown in fig. 5 and 6 includes 14 processing channels (CH 1 to CH 14), but those skilled in the art will understand that the baseband signal processing unit may also include any other number of processing channels.
As shown in fig. 3 and 5, the receiving processing section includes a receiving mixing module 41, a down-sampling module 42, and a signal shaping module 43, which are connected in sequence. Taking the first processing channel CH1 as an example, the receiving and mixing module 41 mixes the receiving local oscillation signal RNCO1 of the processing channel CH1 with the input signal of the processing channel CH1 to generate a zero intermediate frequency signal, and then the down-sampling module 42 down-samples the signal; the signal shaping module 43 is constituted by a signal shaping filter RFIR1 to perform signal shaping.
The down-sampling module 42 comprises a down-sampling filter or a plurality of down-sampling filters connected in cascade, preferably a half-band filter. For example, as shown in fig. 5, each processing channel CH1 to CH8 includes 4 cascade-connected down-sampling filters RHBFi _1, RHBFi _2, RHBFi _3, and RHBFi _4; in the processing channels CH 9-CH 12, each processing channel CHi comprises 3 cascaded connected downsampling filters RHFBi _1, RHFBi _2 and RHFBi _3; each processing channel CH13 and CH14 includes 2 down-sampling filters RHBFi _1 and RHBFi _2 connected in cascade, where i is the sequence number of the processing channel. Although not shown in the figure, it will be understood by those skilled in the art that the down-sampling module of each processing channel may include only one down-sampling filter, or may include a different number of down-sampling filters than those shown in the figure, as long as the sampling rate of the signal input to the signal shaping module is sufficient.
As shown in fig. 4 and 6, the transmission processing section includes an up-sampling module 44 and a transmission mixing module 45 connected in sequence. Taking the first processing channel CH1 as an example, the transmit frequency mixing module 45 mixes the transmit local oscillation signal TNCO1 of the processing channel CH1 with the received signal to generate an output signal of the processing channel CH 1.
The upsampling module 44 includes an upsampling filter or a plurality of upsampling filters connected in cascade, and the number of the upsampling filters in a processing channel is the same as the number of the downsampling filters in the processing channel, and the upsampling factor of the upsampling filter is the same as the downsampling factor of the downsampling filter of the processing channel, so as to ensure that the sampling rate of the transmitting processing part and the receiving processing part in each processing channel is matched. Preferably, the upsampling filter is a half band filter.
For example, as shown in fig. 6, each processing channel CH1 to CH8 is the same as its corresponding receiving processing part, and includes 4 cascade-connected upsampling filters THBFi _1, THBFi _2, THBFi _3, and THBFi _4; in the processing channels CH9 to CH12, each processing channel CHi is the same as its corresponding receiving processing part, and includes 3 cascade-connected up-sampling filters THBFi _1, THBFi _2, and THBFi _3; in the processing channels CH13 and CH14, each processing channel CHi is the same as its corresponding receiving processing part, and includes 2 cascade-connected upsampling filters THBFi _1 and THBFi _2, where i is a sequence number of the processing channel. Although not shown in the figure, it will be understood by those skilled in the art that the up-sampling module of each processing channel may include only one up-sampling filter, or may include a different number of up-sampling filters from those shown in the figure, as long as the sampling rate of the signal input to the transmit mixing module is sufficient.
In the example shown in fig. 5, the analog-to-digital conversion circuit includes ADC1, ADC2, and ADC3, and in the example shown in fig. 6, the digital-to-analog conversion circuit includes DAC1, DAC2, and DAC3. It will be appreciated by those skilled in the art that the analog-to-digital conversion circuit may also include any other number of ADCs and the digital-to-analog conversion circuit may also include any other number of DACs.
Although fig. 5 shows an example in which the signal output by the ADC1 enters the processing channels CH 1-CH 5, the signal output by the ADC2 enters the processing channels CH 6-CH 9, and the signal output by the ADC3 enters the processing channels CH 10-CH 14, it will be understood by those skilled in the art that the signal output by any one of the ADC1, ADC2, or ADC3 may be processed by arbitrarily selecting the processing channel (i.e., may be selected to enter any one of the processing channels CH 1-CH 14), different processing channels may be used for processing signals with different bandwidths and different frequencies, and different processing channels may also be used for processing signals with the same bandwidth and the same frequency. The frequency and bandwidth available for each processing channel may be set by setting the frequency and bandwidth of the local oscillator signals (receive local oscillator signals and transmit local oscillator signals) as desired. Similarly, although the output signals of the processing channels CH 1-CH 5 are shown in fig. 6 as entering ADC1, the output signals of the processing channels CH 6-CH 9 entering ADC2, and the output signals of the processing channels CH 10-CH 14 entering ADC3, it will be understood by those skilled in the art that the signal output by any of the processing channels CH 1-CH 14 can be selected to enter any of ADC 1-ADC 3.
The operation process of each processing channel of the baseband signal processing module will be described with reference to fig. 5 and 6 by taking the first processing channel CH1 as an example. In the examples shown in fig. 5 and 6, the upsampling factor of the upsampling filter and the downsampling factor of the downsampling filter are both 2.
The signal entering the receiving processing part of the processing channel CH1 is mixed with a receiving local oscillation signal RNCO1 to generate a zero intermediate frequency signal, and the sampling rate is 107.52MHz; the signal is sent to a 1 st-stage downsampling filter RHBF1_1 for downsampling, and the sampling rate after downsampling is reduced to 53.76MHz; then entering a 2 nd-level down-sampling filter RHBF1_2 for down-sampling, and reducing the sampling rate after down-sampling to 26.88MHz; then the signal is sent to a 3 rd-level down-sampling filter RHBF1_3 for down-sampling, and the sampling rate after down-sampling is reduced to 13.44MHz; then the signal is sent to a 4 th-stage down-sampling filter RHBF1_4 for down-sampling, and the sampling rate after down-sampling is reduced to 6.72MHz; finally, the signal is sent to a signal shaping filter RFIR1 for signal shaping. The signal output from the signal shaping filter enters a transmitting processing part of a processing channel CH1 for up-sampling, the sampling rate of the signal respectively rises from 6.72MHz to 13.44MHz, 26.88MHz, 53.72MHz and 107.52MHz through a 1 st stage up-sampling filter THF1_1, a 2 nd stage up-sampling filter THF1_2, a 3 rd stage up-sampling filter THF1_3 and a 4 th stage up-sampling filter THF1_4, and finally the signal is mixed with a transmitting local oscillation signal TNCO1 to obtain an output signal which is sent to one of DAC1, DAC2 and DAC3 for digital-to-analog conversion. In this way, the baseband signal processing process of the single processing channel is completed.
Based on the architecture of the digital filter in the baseband signal processing unit, the processing of signals of multiple frequency bands can be realized, that is, a multi-subband variable bandwidth digital filter can be realized.
In order to make the filter application of each processing channel more reasonable and save space logic resources, filter multiplexing may be adopted in the filter architecture for baseband signal processing.
In order to make the application of the channel filter more reasonable and save space logic resources, the multiplexing of the filter is adopted in the filter architecture design. When the down-sampling module comprises a plurality of down-sampling filters connected in cascade, at most 2^ (n-1) processing channels with the same sampling rate can multiplex an n-th-stage down-sampling filter, and a plurality of processing channels corresponding to the receiving processing part can multiplex an up-sampling filter, wherein the operation 2^ (n-1) represents the power of n-1 of 2, and n is the stage number of the down-sampling filter.
For example, in the example shown in fig. 5 and 6 (in which the dashed boxes indicate filters having a multiplexing relationship therebetween), in the reception processing section of each processing path, the processing paths CH1 to CH14 each perform down-sampling of the 1 st stage using the respective 1 st stage down-sampling filters RHBF1_1 to RHBF14_ 1.
In the down-sampling process of the 2 nd stage, since the sampling rate of the signal is already 1/2 of the sampling rate before the 1 st stage down-sampling, the same down-sampling filter can be multiplexed by 2 processing channels, for example, the 2 nd down-sampling filters RHBF1_2 and RHBF2_2 of the processing channels CH1 and CH2 can be implemented by the same physical filter, for example, the same physical filter can be multiplexed by means of time division multiplexing. Likewise, the 2 nd-stage downsampling filters RHBF3_2 and RHBF4_2 of the processing channels CH3 and CH4 may multiplex one filter, the 2 nd-stage downsampling filters RHBF5_2 and RHBF6_2 of the processing channels CH5 and CH6 may multiplex one filter, the 2 nd-stage downsampling filters RHBF7_2 and RHBF8_2 of the processing channels CH7 and CH8 may multiplex one filter, the 2 nd-stage downsampling filters RHBF9_2 and RHBF10_2 of the processing channels CH9 and CH10 may multiplex one filter, the 2 nd-stage downsampling filters RHBF11_2 and RHBF12_2 of the processing channels CH11 and CH12 may multiplex one filter, and the 2 nd-stage downsampling filters RHBF13_2 and RHBF14_2 of the processing channels CH13 and CH14 may multiplex one filter.
In the down-sampling process of the 3 rd stage, since the sampling rate of the signal is already 1/2 before the 2 nd stage down-sampling, that is, 1/4 before the 1 st stage down-sampling, the same down-sampling filter can be multiplexed by 4 processing channels, for example, the 3 rd stage down-sampling filters RHBF1_3 to RHBF4_3 of the processing channels CH1 to CH4 can be implemented by the same physical filter, for example, the same physical filter can be multiplexed by time division multiplexing. Similarly, the 3 rd-order downsampling filters RHBF5_3 to RHBF8_3 of the processing paths CH5 to CH8 may multiplex one filter, and the 3 rd-order downsampling filters RHBF9_3 to RHBF12_3 of the processing paths CH9 to CH12 may multiplex one filter.
In particular, the processing channels CH13 and CH14 comprise only two stages of down-sampling filters, connected after the 2 nd stage of down-sampling filters are signal shaping filters RFIR13 and RFIR14, respectively. Since the sampling rate of the signals entering the signal shaping filters RFIR13 and RFIR14 is 1/4 of the sampling rate before entering the 1 st down-sampling filter, at most 4 processing channels containing only two down-sampling filters can multiplex one signal shaping filter. Thus in the example of fig. 5, the signal shaping filters RFIR13 and RFIR14 of the processing channels CH13 and CH14 multiplex the same shaping filter, for example RFIR13 and RFIR14 may be implemented with the same physical filter in a time division multiplexed manner.
Similarly, during the down-sampling of the 4 th stage, since the sampling rate of the signal is already 1/8 of that before the down-sampling of the 1 st stage, the same down-sampling filter can be multiplexed by 8 processing channels. For example, the 4 th-stage downsampling filters RHBF1_4 to RHBF8_4 of the processing channels CH1 to CH8 may be implemented by using the same physical filter, for example, the same physical filter may be multiplexed in a time division multiplexing manner.
In particular, the processing channels CH9 to CH12 only include three stages of down-sampling filters, and signal shaping filters RFIR9 to RFIR12 are connected after the 3 rd stage down-sampling filter, respectively. Since the sampling rate of the signals entering the signal shaping filters RFIR9 to RFIR12 is 1/8 of the sampling rate before entering the 1 st-order down-sampling filter, at most 8 processing channels (i.e. including only three-order down-sampling filters) with the same sampling rate can multiplex one signal shaping filter. Thus, in the example of fig. 5, the signal shaping filters RFIR9 to RFIR12 of the processing channels CH9 to CH12 multiplex the same shaping filter, for example RFIR9 to RFIR12 may be implemented by time division multiplexing with the same physical filter.
After the 4 th stage down-sampling filter, the sampling rate of the signal is reduced to 1/16 of the sampling rate of the input signal of the processing channel, so that 16 processing channels (including four stages of down-sampling filters) with the same sampling rate can multiplex one signal shaping filter. Thus, in the example of fig. 5, the signal shaping filters RFIR1 to RFIR8 of the processing channels CH1 to CH8 multiplex the same shaping filter, for example RFIR1 to RFIR8 may be implemented by time division multiplexing with the same physical filter.
In the transmit processing section shown in fig. 6, the number of up-sampling filters of each processing channel is the same as the number of down-sampling filters of the receive processing section of that processing channel. Similarly, the 1 st stage up-sampling filters THBF1_ 1-THBF 8_1 multiplex the same filter; the 2 nd-stage up-sampling filters THBF1_ 2-THBF 4_2, THBF5_ 2-THBF 8_2 and THBF9_ 2-THBF 12_2 are respectively multiplexed with the same filter; the 3 rd-level up-sampling filter THBF1_ 3-THBF 2_3, THBF3_ 3-THBF 4_3, THBF5_ 3-THBF 6_3, THBF7_ 3-THBF 8_3, THBF9_ 3-THBF 10_3, THBF11_ 3-THBF 12_3 and THBF13_ 3-THBF 14_3 respectively multiplex the same filter; separate filters are used for each processing channel during the up-sampling of stage 4.
Therefore, the multiplexing of a plurality of processing channels to the filter is realized, so that the logic resource is saved, the architecture of the whole digital filter of the baseband processing unit is simpler, and the operation efficiency is higher.
The above embodiments are merely exemplary embodiments of the present invention, which should not be construed as limiting the scope of the present invention, which is defined by the following claims. Various modifications and equivalents of the invention may be made by those skilled in the art within the spirit and scope of the invention, and these modifications and equivalents should also be considered as falling within the scope of the invention.
Claims (4)
1. A multi-sub-band variable bandwidth repeater comprises a baseband signal processing unit, a frequency control unit and a bandwidth control unit, wherein the baseband signal processing unit is used for processing a digital signal output from an analog-to-digital conversion circuit and outputting the processed signal to a digital-to-analog conversion circuit for conversion and final transmission, the baseband signal processing unit comprises a plurality of processing channels, each processing channel is used for processing a signal with a set frequency and a set bandwidth, each processing channel comprises a receiving processing part and a transmitting processing part,
the receiving and processing part comprises a receiving and frequency mixing module, a down-sampling module and a signal shaping module which are connected in sequence, the receiving and frequency mixing module mixes a receiving local oscillation signal of the processing channel with an input signal of the processing channel to generate a zero intermediate frequency signal, and the down-sampling module comprises a down-sampling filter or a plurality of down-sampling filters which are connected in a cascade manner;
the transmission processing part comprises an up-sampling module and a transmission frequency mixing module which are sequentially connected, the up-sampling module comprises an up-sampling filter or a plurality of up-sampling filters which are in cascade connection, the number of the up-sampling filters is the same as that of the down-sampling filters, the up-sampling factors of the up-sampling filters are the same as those of the down-sampling filters, and the transmission frequency mixing module mixes the transmission local oscillation signals of the processing channel with the received signals to generate the output signals of the processing channel.
2. The multi-subband variable bandwidth repeater according to claim 1, wherein the up-sampling factor and the down-sampling factor are both 2, when the down-sampling module comprises a plurality of down-sampling filters connected in cascade, at most 2^ (n-1) processing channels with the same sampling rate can multiplex one nth stage of the down-sampling filter, and a plurality of processing channels corresponding to the receiving processing part can multiplex one up-sampling filter, wherein the operation 2^ (n-1) represents the power of 2 to the power of n-1, and n is the number of stages of the down-sampling filter.
3. The multi-subband variable bandwidth repeater according to claim 1, wherein the up-sampling filter and the down-sampling filter are half-band filters.
4. The multi-subband variable bandwidth repeater according to claim 1, wherein the baseband signal processing unit is implemented in an FPGA.
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| CN108092704A (en) | 2018-05-29 |
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