CN108074609B - Write tracking followability detection method and circuit, and memory including the circuit - Google Patents
Write tracking followability detection method and circuit, and memory including the circuit Download PDFInfo
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- CN108074609B CN108074609B CN201611026642.4A CN201611026642A CN108074609B CN 108074609 B CN108074609 B CN 108074609B CN 201611026642 A CN201611026642 A CN 201611026642A CN 108074609 B CN108074609 B CN 108074609B
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The invention provides a write tracking followability detection method and circuit and a memory including the circuit. The write tracking followability detection method includes: providing a write tracking unit, a delay unit and a virtual storage unit; detecting whether the virtual storage unit fails to write; and when the virtual storage unit fails to write, outputting the output of the write tracking unit as a write feedback signal; and when the virtual storage unit fails in writing, the output of the writing tracking unit is delayed by the delay unit and then is output as a writing feedback signal. The write tracking followability detection method and circuit and the memory comprising the circuit can detect the followability of write tracking, and delay is added into a write tracking path when the write tracking path is faster than actual write, so that the word line can be ensured to have enough starting time, and the write failure of a memory cell is avoided.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a write tracking followability detection method and circuit and a memory comprising the circuit.
Background
As manufacturing processes continue to advance, semiconductor memory devices become smaller and faster in size, and power consumption is significantly reduced. In modern nanoscale semiconductor devices, due to adverse factors such as manufacturing process, voltage, temperature (PVT), and the like, transistors originally designed in the same manner have different degrees of deviation, and process deviation and the like have significant influence on circuit performance, and increase difficulty in simulation of the entire circuit. Due to the existence of process variations, different memory cells have different data writing and reading speeds, and thus timing inconsistency occurs. In addition to the voltage and temperature variations, these timing differences may cause the data to be incorrectly read or written in the memory.
As a volatile memory, the SRAM is widely used in electronic products such as computers and mobile phones. Generally, the data read speed of the SRAM is slower than the write speed, and therefore, timing tracking on the read path is more of a concern in the design. Nowadays, as the process level and the demand for power consumption increase, the supply voltage is also decreasing. At a lower voltage, the writing speed of the SRAM is slowed, and in addition, the worst case in the process exists, if data writing delay is not considered, the insufficient valid time on the word line or the bit line can cause the writing failure on the memory cell, and finally the yield of the SRAM is affected. Therefore, it is necessary to provide a write tracking circuit to improve the accuracy and reliability of the entire SRAM operation timing. Under the condition of low voltage of a process corner of a Slow NMOS Fast PMOS (SNFP), a write tracking path of the existing write tracking circuit is faster than the actual write tracking path, which causes the word line turn-on time of a write cycle to be too short, and can cause the write failure of a storage unit in the worst case.
Disclosure of Invention
The invention provides a write tracking followability detection method, which comprises the following steps: providing a write tracking unit, a delay unit and a virtual storage unit; detecting whether the virtual storage unit fails to write; and when the virtual storage unit fails to write, outputting the output of the write tracking unit as a write feedback signal; and when the virtual storage unit fails in writing, the output of the writing tracking unit is delayed by the delay unit and then is output as a writing feedback signal.
On the other hand, the invention provides a write tracking following detection circuit, which comprises a write tracking unit, a delay unit, a virtual storage unit and a detection unit, wherein the detection unit is used for detecting whether the virtual storage unit fails in writing, and when the virtual storage unit fails in writing, the output of the write tracking unit is output as a write feedback signal, and when the virtual storage unit fails in writing, the output of the write tracking unit is output as the write feedback signal after being delayed by the delay unit.
In one embodiment of the present invention, the detection unit includes an inverter and an or-nand gate, wherein an input of the inverter is connected to one storage node of the dummy storage unit, an output of the write tracking unit is connected to an input of the delay unit, an output of the inverter, and an output of the write tracking unit are connected to an input of the or-nand gate, and the or-nand gate outputs the write feedback signal.
In one embodiment of the invention, the dummy memory cell includes a pair of cross-coupled inverters having a first storage node and a second storage node, a first pass transistor operatively connected to the first storage node, and a second pass transistor operatively connected to the second storage node.
In one embodiment of the present invention, the dummy memory cell is operatively connected to the first dummy bit line through the first pass transistor and operatively connected to a second dummy bit line through the second pass transistor, the first pass transistor and the second pass transistor being controlled by the dummy word line.
In another aspect, the present invention further provides a memory, where the memory includes a write tracking following detection circuit, a write tracking unit, a delay unit, a virtual storage unit, and a detection unit, where the detection unit is configured to detect whether the virtual storage unit fails to write, and output an output of the write tracking unit as a write feedback signal when the virtual storage unit fails to write, and output an output of the write tracking unit as a write feedback signal after being delayed by the delay unit when the virtual storage unit fails to write.
In one embodiment of the present invention, the detection unit includes an inverter and an or-nand gate, wherein an input of the inverter is connected to one storage node of the dummy storage unit, an output of the write tracking unit is connected to an input of the delay unit, an output of the inverter, and an output of the write tracking unit are connected to an input of the or-nand gate, and the or-nand gate outputs the write feedback signal.
In one embodiment of the invention, the dummy memory cell includes a pair of cross-coupled inverters having a first storage node and a second storage node, a first pass transistor operatively connected to the first storage node, and a second pass transistor operatively connected to the second storage node.
In one embodiment of the present invention, the dummy memory cell is operatively connected to the first dummy bit line through the first pass transistor and operatively connected to a second dummy bit line through the second pass transistor, the first pass transistor and the second pass transistor being controlled by the dummy word line.
In one embodiment of the invention, the memory is a static random access memory.
The write tracking followability detection method and circuit and the memory comprising the circuit can detect the followability of write tracking, and delay is added into a write tracking path when the write tracking path is faster than actual write, so that the word line can be ensured to have enough starting time, and the write failure of a memory cell is avoided.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a schematic flow diagram of a write tracking follower detection method according to an embodiment of the invention;
fig. 2 shows a schematic configuration diagram of a write tracking followability detection circuit according to an embodiment of the present invention;
FIG. 3 illustrates simulation results of the circuit shown in FIG. 2 with no write failures and write failures of the dummy memory cells; and
fig. 4 is a graph showing a comparison of simulation results of an existing write tracking circuit and a write tracking follow detection circuit according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In recent years, a Static Random Access Memory (SRAM) has been widely used in a large number because of its advantages such as high speed and simple system design. SRAM arrays typically include tracking circuits that detect the delay in the transmission of a signal to the array. In order to ensure that the reading time limit is long enough, namely, to ensure that the data on the memory is correctly read, the time sequence of the memory control signal is adjusted by using the delay detected by the tracking signal, so that the performance and the safety of the SRAM can be greatly improved.
Generally, the data read speed of the SRAM is slower than the write speed, and therefore, timing tracking on the read path is more of a concern in the design. As the process level and power consumption requirements increase, the supply voltage is also decreasing. At a lower voltage, the writing speed of the SRAM is slowed, and in addition, the worst case in the process exists, if data writing delay is not considered, the insufficient valid time on the word line or the bit line can cause the writing failure on the memory cell, and finally the yield of the SRAM is affected.
Early SRAM write tracking circuits borrowed tracking circuits for read operations. However, under the condition of the minimum operating voltage (Vccmin) at which the circuit can normally operate, SRAM write operation requires a longer word line on time than read operation. Therefore, it has become the mainstream to design a separate write tracking circuit.
Early write tracking circuits were implemented using a delay chain (delay chain), or a tracking circuit for read operations plus a delay chain. The disadvantage of this method is that the variation of the write operation with manufacturing process, voltage, temperature PVT is not well reflected.
At present, write tracking is mainly realized by adopting copy memory cell (bitcell) write operation. In order to ensure that the write tracking circuit is effective under the condition of Vccmin, a structure that two pull-up tubes are connected in series is usually adopted, and the write capability of a storage unit in the write tracking circuit is enhanced, so that the problem that the write tracking circuit fails before an actual clock path under the condition of Vccmin is solved. However, due to the difference between the memory cells in the write tracking circuit and the memory cells in the array, the write tracking path is faster than the actual write under the SNFP process corner low voltage condition, which will result in the write cycle word line on time being too short, which in the worst case may result in memory cell write failure.
In order to overcome the above problems, the present invention provides a method for detecting the tracking ability of a write trace, which can detect the tracking ability of a write trace, and add a delay to a write trace path when the write trace path is faster than the actual write path, thereby ensuring that a word line has a sufficient turn-on time.
The correct implementation of the memory cell writing operation requires that a pull-up PMOS transistor is weaker than a transmission NMOS transistor, so that the writing margin (write margin) of the memory cell under the SNFP process corner is minimum, and the memory cell writing failure can occur under the Vccmin condition. Based on the analysis, the detection of the write tracking path under the SNFP process corner is equivalent to the detection of the write capability of the memory cell.
Therefore, a dummy cell (dummy cell) which is more prone to write failure than a memory cell (bitcell) in the memory array can be provided. When the virtual memory unit fails to write, delay is added to the write tracking path to increase the on time of the word line. If the virtual memory location has not failed, no delay is added.
FIG. 1 shows a schematic flow diagram of a write tracking follower detection method 100 according to an embodiment of the invention. As shown in FIG. 1, the write tracking compliance detection method 100 includes the steps of:
in step S110, a write tracking unit, a delay unit, and a virtual storage unit are provided.
In step S120, it is detected whether the virtual storage unit has write failure. When the virtual storage unit fails to write, continuing to step S130; when the virtual storage unit write fails, step S140 is performed.
In step S130, the output of the write tracking unit is output as a write feedback signal.
In step S140, the output of the write tracking unit is delayed by the delay unit and then output as a write feedback signal.
The write tracking following performance detection method provided by the invention can detect the following performance of write tracking, and when the write tracking path is faster than the actual write path, delay is added into the write tracking path, so that the word line can be ensured to have enough starting time, and the write failure of the storage unit is avoided.
A write tracking followability detection circuit provided according to another aspect of the present invention, which can implement the above-described write tracking followability detection method according to an embodiment of the present invention, is described below.
The write tracking following detection circuit comprises a write tracking unit, a delay unit, a virtual storage unit and a detection unit. The detection unit is used for detecting whether the virtual storage unit is write-failed or not, enabling the output of the write tracking unit to be output as a write feedback signal when the virtual storage unit is not write-failed, and enabling the output of the write tracking unit to be output as the write feedback signal after the output of the write tracking unit is delayed by the delay unit when the virtual storage unit is write-failed.
In one embodiment, the detection unit includes an inverter and an or nand gate. Wherein an input of the inverter is connected to one storage node of the dummy storage unit, an output of the write tracking unit is connected to an input of the delay unit, an output of the inverter, and an output of the write tracking unit are connected to an input of the or-nand gate, and the or-nand gate outputs the write feedback signal. In other embodiments, the detection unit may also be implemented in other structures as long as the above-described functions of detecting whether the virtual storage unit is write-failed and then controlling the output are implemented.
In one embodiment, a write tracking follower detection circuit according to embodiments of the present invention may include a dummy memory cell including a pair of cross-coupled inverters having a first storage node and a second storage node, a first pass transistor operatively connected to the first storage node, and a second pass transistor operatively connected to the second storage node. A dummy memory cell is operatively connected to a dummy bit line (e.g., a first dummy bit line) associated with the dummy memory cell through a first pass transistor and to another dummy bit line (e.g., a second dummy bit line) associated with the dummy memory cell through a second pass transistor. The first pass transistor and the second pass transistor are controlled by a dummy word line associated with the dummy memory cell.
The write tracking followability detection circuit provided by the present invention is described in detail according to the specific embodiment with reference to the drawings. Fig. 2 shows a schematic structural diagram of a write tracking follow detection circuit 200 according to an embodiment of the present invention. As shown in fig. 2, the write tracking follow detection circuit 200 includes a write tracking unit 210, a delay unit 220, a dummy storage unit 230, and a detection unit. Which is shown in fig. 2 as including an inverter 240 and an or nand gate 250.
The dummy memory cell 230 includes a pair of cross-coupled inverters consisting of transistors M1, M2, M3 and M4 having a first storage node BC and a second storage node BCN, a first pass transistor M5 operatively connected to the first storage node BC, and a second pass transistor M6 operatively connected to the second storage node BCN. In FIG. 2, a dummy word line DWL and a pair of dummy bit lines DBL and DBLB are also shown associated with the dummy memory cell 230.
The input of the inverter 240 is connected to one storage node BC of the dummy storage unit 230, the output RBB of the write tracking unit 210 is connected to the input of the Delay unit 220, the output RBB _ Delay of the Delay unit 220, the output BCB of the inverter 240, and the output RBB of the write tracking unit 210 are connected to the input of the or-gate 250, or the nand-gate 250 outputs the write feedback signal FB.
The connections between the devices of the write tracking follow detection circuit 200 according to the embodiment of the present invention are described above, and the operation principle of the circuit is described below. As shown in fig. 2, when the dummy memory cell 230 fails to write, the output BCB of the inverter 240 is equal to 0, and the falling edge of the write feedback signal FB depends on the output RBB _ delay of the delay unit 220, i.e., a delay is added in the write tracking path. When the dummy memory cell 230 is able to write normally, the falling edge of the write feedback signal FB depends on the output RBB of the write tracking unit 210, i.e., no additional delay is added.
Based on the above description, the write tracking followability detection circuit according to the embodiment of the present invention can detect the followability of write tracking, and add a delay to a write tracking path when the write tracking path is faster than actual write, thereby ensuring that a word line has sufficient turn-on time and avoiding write failure of a memory cell.
This is further described by specific simulation results in conjunction with fig. 3 and 4. FIG. 3 shows simulation results of the circuit shown in FIG. 2 with no write failures and write failures of the dummy memory cells. Fig. 4 is a graph showing a comparison of simulation results of an existing write tracking circuit and a write tracking follow detection circuit according to an embodiment of the present invention.
As shown in FIG. 3, when the dummy memory cell 230 is not write-failed, the internal storage node BC/BCN (shown as BC/BCN _1 in FIG. 3) of the dummy memory cell 230 is correctly flipped, and at this time, the falling edge of the write feedback signal FB (shown as FB _1 in FIG. 3) depends on the output RBB (shown as RBB _1 in FIG. 3) signal of the write tracking unit 210. When the dummy memory cell 230 fails to write, the internal storage node BC/BCN (shown as BC/BCN _2 in fig. 3) of the dummy memory cell 230 cannot be flipped correctly, the output BCB (shown as BCB _2 in fig. 3) of the inverter 240 is equal to 0, and the falling edge of the write feedback signal FB (shown as FB _2 in fig. 3) depends on the output RBB _ Delay (shown as RBB _ Delay _2 in fig. 3) of the Delay unit 220.
As shown in FIG. 4, at the time of a virtual storage unit write failure: the write feedback signal of the conventional write tracking circuit is FB1, the word line is turned on for WL1, and the internal nodes of the memory cells in the array are BC1/BCN 1; the write tracking follower detection circuit outputs the write feedback signal FB2, the word line is turned on for WL2, and the internal nodes of the memory cells in the array are BC2/BCN 2.
As shown in fig. 4, the conventional write tracking circuit does not add a detection to the write tracking following performance, so that the internal node of the memory cell in the array cannot be correctly inverted when the write failure occurs to the dummy memory cell, and thus the correct write operation cannot be completed. In contrast, the falling edge of the write feedback signal output by the write tracking follower detection circuit according to the embodiment of the invention added to the write tracking follower detection increases the delay and increases the time for turning on the word line, so that the internal nodes of the memory cells in the array can be correctly turned over to complete correct write operation.
Therefore, it is verified that the write tracking followability detection circuit provided by the present invention based on the above embodiment can detect the followability of write tracking, and when the write tracking path is faster than the actual write path, a delay is added to the write tracking path, thereby ensuring that the word line has sufficient turn-on time and avoiding the write failure of the memory cell.
According to another aspect of the present invention, there is also provided a memory including the write tracking followability detection circuit described in the above embodiments. Specifically, the write tracking follower detection circuit comprises a write tracking unit, a delay unit, a virtual storage unit and a detection unit, wherein the detection unit is used for detecting whether the virtual storage unit is write-failed or not, enabling the output of the write tracking unit to be output as a write feedback signal when the virtual storage unit is not write-failed, and enabling the output of the write tracking unit to be output as the write feedback signal after being delayed by the delay unit when the virtual storage unit is write-failed.
In one embodiment of the present invention, the detection unit may include an inverter and an or-nand gate, wherein an input of the inverter is connected to one storage node of the dummy storage unit, an output of the write tracking unit is connected to an input of the delay unit, an output of the inverter, and an output of the write tracking unit are connected to an input of the or-nand gate, and the or-nand gate outputs the write feedback signal.
In one embodiment of the present invention, the dummy memory cell may include a pair of cross-coupled inverters having a first storage node and a second storage node, a first pass transistor operatively connected to the first storage node, and a second pass transistor operatively connected to the second storage node.
In one embodiment of the present invention, the dummy memory cell is operatively connected to the first dummy bit line through the first pass transistor and operatively connected to a second dummy bit line through the second pass transistor, the first pass transistor and the second pass transistor being controlled by the dummy word line.
In one embodiment of the present invention, the memory is a static random access memory or any other memory to which the above-described write tracking follower detection circuit according to the embodiment of the present invention is applicable.
A person skilled in the art can understand the specific structure of the write tracking follow detection circuit of the memory according to the embodiment of the present invention with reference to the specific embodiment of the write tracking follow detection circuit described previously, and for brevity, the detailed description is omitted here. Of course, the memory according to the embodiment of the present invention may further include any other elements or circuits known to those of ordinary skill in the art, which will not be described in detail herein in order to avoid obscuring the present invention.
Although the foregoing example embodiments have been described with reference to the accompanying drawings, it is to be understood that the foregoing example embodiments are merely illustrative and are not intended to limit the scope of the invention thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as set forth in the appended claims.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present invention should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A write tracking followability detection method, the method comprising:
providing a writing tracking unit, a delay unit, a virtual storage unit and a detection unit;
detecting whether the virtual storage unit fails to write through the detection unit; and
when the virtual storage unit fails to write, outputting the output of the write tracking unit as a write feedback signal; when the virtual storage unit fails in writing, the output of the writing tracking unit is delayed by the delay unit and then is used as a writing feedback signal to be output;
the detection unit comprises an inverter, an OR gate and a NAND gate, wherein the input of the inverter is connected to one storage node of the virtual storage unit, the output of the write tracking unit is connected to the input of the delay unit, the output of the delay unit is connected to one input of the OR gate, the output of the inverter is connected to the other input of the OR gate, the output of the OR gate is connected to one input of the NAND gate, the output of the write tracking unit is connected to the other input of the NAND gate, and the NAND gate outputs the write feedback signal.
2. A write tracking followability detection circuit comprising a write tracking unit, a delay unit, a dummy storage unit, and a detection unit, wherein,
the detection unit is used for detecting whether the virtual storage unit is write-failed or not, enabling the output of the write tracking unit to be output as a write feedback signal when the virtual storage unit is not write-failed, and enabling the output of the write tracking unit to be output as a write feedback signal after the output of the write tracking unit is delayed by the delay unit when the virtual storage unit is write-failed;
the detection unit comprises an inverter, an OR gate and a NAND gate, wherein the input of the inverter is connected to one storage node of the virtual storage unit, the output of the write tracking unit is connected to the input of the delay unit, the output of the delay unit is connected to one input of the OR gate, the output of the inverter is connected to the other input of the OR gate, the output of the OR gate is connected to one input of the NAND gate, the output of the write tracking unit is connected to the other input of the NAND gate, and the NAND gate outputs the write feedback signal.
3. The circuit of claim 2, wherein the dummy storage cell comprises a pair of cross-coupled inverters having a first storage node and a second storage node, a first pass transistor operably connected to the first storage node, and a second pass transistor operably connected to the second storage node.
4. The circuit of claim 3, wherein the dummy memory cell is operatively connected to a first dummy bit line through the first pass transistor and to a second dummy bit line through the second pass transistor, the first pass transistor and the second pass transistor being controlled by a dummy word line.
5. A memory comprising a write tracking follower detection circuit comprising a write tracking cell, a delay cell, a dummy storage cell, and a detection cell, wherein,
the detection unit is used for detecting whether the virtual storage unit is write-failed or not, enabling the output of the write tracking unit to be output as a write feedback signal when the virtual storage unit is not write-failed, and enabling the output of the write tracking unit to be output as a write feedback signal after the output of the write tracking unit is delayed by the delay unit when the virtual storage unit is write-failed;
the detection unit comprises an inverter, an OR gate and a NAND gate, wherein the input of the inverter is connected to one storage node of the virtual storage unit, the output of the write tracking unit is connected to the input of the delay unit, the output of the delay unit is connected to one input of the OR gate, the output of the inverter is connected to the other input of the OR gate, the output of the OR gate is connected to one input of the NAND gate, the output of the write tracking unit is connected to the other input of the NAND gate, and the NAND gate outputs the write feedback signal.
6. The memory of claim 5, wherein the dummy storage cell comprises a pair of cross-coupled inverters having a first storage node and a second storage node, a first pass transistor operably connected to the first storage node, and a second pass transistor operably connected to the second storage node.
7. The memory of claim 6, wherein the dummy memory cell is operatively connected to a first dummy bit line through the first pass transistor and operatively connected to a second dummy bit line through the second pass transistor, the first pass transistor and the second pass transistor being controlled by a dummy word line.
8. The memory of claim 5, wherein the memory is a static random access memory.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591684A (en) * | 2003-08-29 | 2005-03-09 | 松下电器产业株式会社 | Semiconductor memory device |
| US20120020169A1 (en) * | 2010-07-20 | 2012-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Two-port sram write tracking scheme |
| CN103886892A (en) * | 2007-05-31 | 2014-06-25 | 高通股份有限公司 | Memory device with delay tracking for improved timing margin |
| CN107293323A (en) * | 2016-04-05 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | Write operation follows the trail of circuit and the memory of circuit is followed the trail of including write operation |
-
2016
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591684A (en) * | 2003-08-29 | 2005-03-09 | 松下电器产业株式会社 | Semiconductor memory device |
| CN103886892A (en) * | 2007-05-31 | 2014-06-25 | 高通股份有限公司 | Memory device with delay tracking for improved timing margin |
| US20120020169A1 (en) * | 2010-07-20 | 2012-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Two-port sram write tracking scheme |
| CN107293323A (en) * | 2016-04-05 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | Write operation follows the trail of circuit and the memory of circuit is followed the trail of including write operation |
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