CN108053794A - A kind of shift register and its driving method, gate driving circuit - Google Patents
A kind of shift register and its driving method, gate driving circuit Download PDFInfo
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- CN108053794A CN108053794A CN201810003999.3A CN201810003999A CN108053794A CN 108053794 A CN108053794 A CN 108053794A CN 201810003999 A CN201810003999 A CN 201810003999A CN 108053794 A CN108053794 A CN 108053794A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the present invention, which provides a kind of shift register and its driving method, gate driving circuit, the shift register, to be included：Sub-circuit is pulled up, is connected with signal input part and pull-up node, under the control of signal input part, pulling up the signal that node provides signal input part；Sub-circuit is exported, is connected with pull-up node, signal output part and clock signal terminal, under the control of pull-up node, the clock signal of clock signal terminal to be provided to signal output part；Output control sub-circuit, it is connected with clock signal terminal, signal output part and power end, for under the control of clock signal terminal, the signal of power end is provided to signal output part, the clock signal current potential one that the present invention exports control sub-circuit clock signal terminal by setting reduces, dragged down to the output signal of signal output part moment, reduce the trailing edge of output signal, it avoids due to being exported caused by trailing edge by mistake, ensure that job stability, use reliability and the display effect of display panel.
Description
Technical field
The present embodiments relate to display technology fields, and in particular to a kind of shift register and its driving method, grid
Driving circuit.
Background technology
In recent years, flat-panel monitor, such as liquid crystal display panel of thin film transistor (Thin Film Transistor-
Liquid Crystal Display, TFT-LCD) and active matrix organic light-emitting diode display panel (Active Matrix
Organic Light Emitting Diode, AMOLED), light-weight due to having many advantages, such as, thickness is thin and low-power consumption, because
And it is widely used in the electronic products such as TV, mobile phone.
With the development of science and technology the display panel of high-resolution, narrow frame becomes the trend of development, occurs array therefore
Substrate raster data model (Gate Driver on Array, GOA) technology, GOA technologies refer to will be for the GOA circuits of driven grid line
The technology of the effective display area domain both sides of array substrate in display panel is arranged on, wherein, in GOA circuits, including multiple displacements
Register.
Through inventor the study found that in current GOA circuits, since the load excessive of gate line, transistor can not be done greatly
Etc. other factors influence, the waveform of the output signal of GOA be frequently not a perfect square wave and there are one trailing edge, instantly
Drop along it is larger when, when next line exports, lastrow is not turned off if generating output, be may result in and is exported by mistake so that display
Panel abnormal show reduces job stability, use reliability and the display effect of display panel.
The content of the invention
In order to solve the above-mentioned technical problem, an embodiment of the present invention provides a kind of shift register and its driving method, grid
Pole driving circuit can avoid, due to exporting caused by trailing edge by mistake, ensure that the job stability of display panel, using reliable
Property and display effect.
On one side, an embodiment of the present invention provides a kind of shift register, including：Pull up sub-circuit, output sub-circuit
Sub-circuit is controlled with output；
The pull-up sub-circuit, is connected with signal input part and pull-up node, under the control of signal input part, to
Pull-up node provides the signal of signal input part；
The output sub-circuit, is connected with pull-up node, signal output part and clock signal terminal, in pull-up node
Under control, the clock signal of clock signal terminal is provided to signal output part；
The output control sub-circuit, is connected with clock signal terminal, signal output part and power end, in clock signal
Under the control at end, the signal of power end is provided to signal output part.
Optionally, the shift register further includes：Reset subcircuit；
The reset subcircuit is connected with pull-up node, reset signal end, signal output part and power end, for multiple
Under the control of position signal end, pull up node and signal output part provides the signal of power end.
Optionally, the pull-up sub-circuit includes：The first transistor；
The control pole of the first transistor and the first pole are connected with signal input part, and the second pole is connected with pull-up node.
Optionally, the output sub-circuit includes：Capacitance and second transistor；
The first end of the capacitance is connected with pull-up node, and second end is connected with signal output part；
The control pole of the second transistor is connected with pull-up node, and the first pole is connected with clock signal terminal, the second pole with
Signal output part connects.
Optionally, the output control sub-circuit includes：Third transistor；
The control pole of the third transistor is connected with clock signal terminal, and the first pole is connected with power end, the second pole and letter
The connection of number output terminal.
Optionally, the reset subcircuit includes：4th transistor and the 5th transistor；
The control pole of 4th transistor is connected with reset signal end, and the first pole is connected with pull-up node, the second pole with
Power end connects；
The control pole of 5th transistor is connected with reset signal end, and the first pole is connected with signal output part, the second pole
It is connected with power end.
Optionally, the third transistor is P-type TFT.
On the other hand, the embodiment of the present invention also provides a kind of gate driving circuit, including multiple cascade above-mentioned displacements
Register.
On the other hand, the embodiment of the present invention also provides a kind of driving method of shift register, is posted applied to above-mentioned displacement
In storage, including：
In input phase, pull-up sub-circuit pulls up node and provides signal input part under the control of signal input part
Signal；
In the output stage, output sub-circuit provides clock signal terminal under the control of pull-up node, to signal output part
Clock signal；Output control sub-circuit provides the signal of power end to signal output part under the control of clock signal terminal.
Optionally, the method further includes：
In reseting stage, reset subcircuit pulls up node and signal output part provides under the control at reset signal end
The signal of power end.
The embodiment of the present invention provides a kind of shift register and its driving method, gate driving circuit, wherein, shift LD
Device includes：Sub-circuit is pulled up, is connected with signal input part and pull-up node, under the control of signal input part, pulling up
Node provides the signal of signal input part；Sub-circuit is exported, is connected with pull-up node, signal output part and clock signal terminal, is used
In under the control of pull-up node, the clock signal of clock signal terminal is provided to signal output part；Output control sub-circuit, with when
Clock signal end, signal output part are connected with power end, under the control of clock signal terminal, power supply to be provided to signal output part
The signal at end, the clock signal current potential one that the embodiment of the present invention exports control sub-circuit clock signal terminal by setting drop
It is low, dragged down to the output signal of signal output part moment, reduce the trailing edge of output signal, avoid since trailing edge causes
Mistake output, ensure that job stability, use reliability and the display effect of display panel.
Certainly, implement any of the products of the present invention or method it is not absolutely required at the same reach all the above excellent
Point.Other features and advantages of the present invention will illustrate in subsequent specification embodiment, also, partly implement from specification
It becomes apparent in example or is understood by implementing the present invention.The purpose of the embodiment of the present invention and other advantages can pass through
Specifically noted structure is realized and obtained in specification, claims and attached drawing.
Description of the drawings
Attached drawing is used for providing further understanding technical solution of the embodiment of the present invention, and one of constitution instruction
Point, for explaining the technical solution of the embodiment of the present invention together with embodiments herein, do not form to the embodiment of the present invention
The limitation of technical solution.
Fig. 1 is the structure diagram one of shift register provided in an embodiment of the present invention；
Fig. 2 is the structure diagram two of shift register provided in an embodiment of the present invention；
Fig. 3 is the equivalent circuit diagram of shift register provided in an embodiment of the present invention；
Fig. 4 is the working timing figure of shift register provided in an embodiment of the present invention；
Fig. 5 is the flow chart one of the driving method of shift register provided in an embodiment of the present invention；
Fig. 6 is the flowchart 2 of the driving method of shift register provided in an embodiment of the present invention；
Fig. 7 is the structure diagram of gate driving circuit provided in an embodiment of the present invention.
Reference sign：
INPUT：Signal input part；
OUTPUT：Signal output part；
CLK、CLKB：Clock signal terminal；
RESET：Reset signal end；
C：Capacitance；
VGL：Power end；
PU：Pull-up node；
M1~M5：Transistor；
STV：Initial signal end.
Specific embodiment
Purpose, technical scheme and advantage to make the embodiment of the present invention are more clearly understood, below in conjunction with attached drawing pair
The embodiment of the embodiment of the present invention is described in detail.It should be noted that in the case where there is no conflict, the implementation in the application
Feature in example and embodiment can be mutually combined.
Unless otherwise defined, the embodiment of the present invention discloses the technical term used or scientific terminology should be institute of the present invention
The ordinary meaning that the personage with general technical ability is understood in category field." first ", " second " used in the embodiment of the present invention
And similar word is not offered as any order, quantity or importance, and be used only to distinguish different components.
The element or flase drop that the similar word such as " comprising " or "comprising" goes out always before the word, which are covered, appears in the word presented hereinafter
Element either object and its equivalent and be not excluded for other elements or object.The similar word such as " connection " or " connected "
Physics or mechanical connection is not limited to, but electrical connection can be included, it is either directly or indirect.
It will be understood by those skilled in the art that the switching transistor and driving transistor that are used in all embodiments of the application
It all can be thin film transistor (TFT) or field-effect tube or the identical device of other characteristics.Preferably, used in the embodiment of the present invention
Thin film transistor (TFT) can be oxide semi conductor transistor.Since the source electrode of the switching transistor that uses here, drain electrode are symmetrical
, so its source electrode, drain electrode can exchange.In embodiments of the present invention, control extremely grid removes grid to distinguish switching transistor
One of electrode is known as the first pole by the two poles of the earth outside pole, and another electrode is known as the second pole, first extremely can be source electrode or
Drain electrode, second extremely can be drain electrode or source electrode.
Embodiment one
Fig. 1 is the structure diagram one of shift register provided in an embodiment of the present invention, as shown in Figure 1, the present invention is implemented
The shift register that example provides includes：Pull up sub-circuit, output sub-circuit and output control sub-circuit；
In the present embodiment, sub-circuit is pulled up, is connected with signal input part INPUT and pull-up node PU, in signal
Under the control of input terminal INPUT, the signal that node PU provides signal input part INPUT is pulled up.
Export sub-circuit, be connected with pull-up node PU, signal output part OUTPUT and clock signal terminal CLK, for
Under the control for drawing node PU, the clock signal of clock signal terminal CLK is provided to signal output part OUTPUT.
Output control sub-circuit, be connected with clock signal terminal CLK, signal output part OUTPUT and power end VGL, for
Under the control of clock signal terminal CLK, the signal of power end VGL is provided to signal output part OUTPUT.
Specifically, signal output part OUTPUT provides gate drive signal for this grade of shift register, and moved with next stage
The signal input part connection of bit register.
In the present embodiment, power end VGL persistently provides low level signal.
Shift register provided in an embodiment of the present invention includes：Sub-circuit is pulled up, is connected with signal input part and pull-up node
It connects, under the control of signal input part, pulling up the signal that node provides signal input part；Sub-circuit is exported, with pull-up
Node, signal output part are connected with clock signal terminal, under the control of pull-up node, clock letter to be provided to signal output part
Number end clock signal；Output control sub-circuit, is connected with clock signal terminal, signal output part and power end, in clock
Under the control of signal end, the signal of power end is provided to signal output part, the embodiment of the present invention exports control son electricity by setting
As soon as road causes the clock signal current potential of clock signal terminal to reduce, moment drags down the output signal of signal output part, reduces defeated
Go out the trailing edge of signal, avoid due to being exported caused by trailing edge by mistake, ensure that the job stability of display panel, using can
By property and display effect.
Optionally, Fig. 2 is the structure diagram two of shift register provided in an embodiment of the present invention, as shown in Fig. 2, this hair
The shift register that bright embodiment provides further includes：Reset subcircuit.
Reset subcircuit connects with pull-up node PU, reset signal end RESET, signal output part OUTPUT and power end VGL
It connects, power end VGL is provided under the control of reset signal end RESET, pulling up node PU and signal output part OUTPUT
Signal.
In embodiments of the present invention, increase reset subcircuit in a shift register, can reduce in shift register
Noise.
In the present embodiment, reset signal end RESET is connected with the signal output part OUTNPUT of next stage shift register.
Fig. 3 is the equivalent circuit diagram of shift register provided in an embodiment of the present invention, and rock electricity has been shown in particular in Fig. 3
Road, output sub-circuit, the example arrangement for exporting control sub-circuit and reset subcircuit.Skilled addressee readily understands that
Be, more than each sub-circuit realization method it is without being limited thereto, as long as its respective function can be realized.
Optionally, pull-up sub-circuit includes：The first transistor M1.
Specifically, the control pole of the first transistor M1 and the first pole are connected with signal input part, the second pole and pull-up node
PU connections.
Optionally, output sub-circuit includes：Capacitance C and second transistor M2.
Specifically, the first end of capacitance C is connected with pull-up node PU, second end is connected with signal output part OUTPUT；The
The control pole of two-transistor M2 is connected with pull-up node PU, and the first pole is connected with clock signal terminal CLK, the second pole and signal output
Hold OUTPUT connections.
Optionally, output control sub-circuit includes：Third transistor M3.
Specifically, the control pole of third transistor M3 is connected with clock signal terminal CLK, the first pole is connected with power end VGL,
Second pole is connected with signal output part OUTPUT.
Specifically, third transistor M3 is used for the moment when the clock signal of clock signal terminal becomes low potential by high potential
It opens, the output signal moment of signal output part is pulled low to the low potential of power end.
In the present embodiment, third transistor is P-type TFT.
Optionally, reset subcircuit includes：4th transistor M4 and the 5th transistor M5.
Specifically, the control pole of the 4th transistor M4 is connected with reset signal end RESET, the first pole connects with pull-up node PU
It connects, the second pole is connected with power end VGL；The control pole of 5th transistor M5 is connected with reset signal end RESET, the first pole and letter
Number output terminal OUTPUT connections, the second pole is connected with power end VGL.
In the present embodiment, third transistor M3 is P-type TFT, the first transistor M1, second transistor M2, the
Four transistor M4 and the 5th transistor M5 all can be N-type TFT or P-type TFT, technique stream can be unified
Journey can reduce manufacturing process, help to improve the yield of product.It is it should be noted that brilliant in view of low-temperature polysilicon film
The leakage current of body pipe is smaller, and therefore, preferably all transistors of the embodiment of the present invention are low-temperature polysilicon film transistor, and film is brilliant
Body pipe can specifically select the thin film transistor (TFT) of bottom grating structure or the thin film transistor (TFT) of top gate structure, as long as switch can be realized
Function.
It should be noted that capacitance C can be the liquid crystal capacitance that is made of pixel electrode and public electrode or by
The equivalent capacity that the liquid crystal capacitance and storage capacitance that pixel electrode is formed with public electrode are formed, the present invention do not limit this
It is fixed.
The technical solution of embodiment is further illustrated the present invention below by the course of work of shift register.
It is N-type TFT with transistor M1, M2, M4 and M5 in shift register provided in an embodiment of the present invention
Exemplified by, Fig. 4 is the working timing figure of shift register provided in an embodiment of the present invention, and as shown in Figure 3 and Figure 4, the present invention is implemented
The shift register that example provides include 5 transistor units (M1~M5), 1 capacitance (C), 3 signal input parts (INPUT,
RESET and CLK), 1 signal output part (OUTPUT) and 1 power end (VGL).
It should be noted that power end VGL persistently provides low level signal.
Specifically：
First stage T1, i.e. input phase, the signal of signal input part INPUT is high level, and the first transistor M1 is opened,
The current potential of pull-up node PU is drawn high, is charged to capacitance C.
In this stage, the signal of the signal input part INPUT in input terminal is high level, reset signal end RESET and when
The signal of clock signal end CLK is low level, and the output signal of signal output part OUTPUT is low level.
Second stage T2 exports the stage, the signal of signal input part INPUT is low level, and the first transistor M1 is turned off,
And the signal of clock signal terminal CLK becomes high level, due to the bootstrap effect of capacitance C so that the current potential of pull-up node PU continues
It is driven high, the high level of pull-up node PU opens second transistor M2, signal output part OUTPUT output clock signal terminals CLK
Signal, i.e. this grade of gate drive signal in addition, the rise of pull-up node PU current potentials, improve second transistor M2 conducting energy
Power ensure that pixel charges, when the clock signal of clock signal terminal CLK becomes low potential by high potential, third transistor M3
Moment is opened, and signal output part OUTPUT is connected with power end VGL, and the output signal moment of signal output part OUTPUT is drawn
It is low.
In this stage, the signal of the clock signal terminal CLK in input terminal is high level, signal input part INPUT and reset
The signal of signal end RESET is low level, and the output signal of signal output part OUTPUT is high level.
Phase III T3, i.e. reseting stage, the signal of reset signal end RESET is high level, and the 4th transistor M4 is opened,
The current potential of pull-up node PU is pulled low to the low level of power end VGL, to reduce noise, the 5th transistor M5 is opened, by signal
The current potential of output terminal OUTPUT is pulled low to the low level of power end VGL, to reduce noise.
In this stage, the reset signal end RESET in input terminal is high level, clock signal terminal CLK and signal input part
The signal of INPUT is low level, and the output signal of signal output part OUTPUT is low level.
The signal of fourth stage T4, clock signal terminal CLK are high level, at this point, since pull-up node PU is low level, the
Two-transistor M2 is off state, and the high level of clock signal terminal CLK can not be output to signal output part OUTPUT, signal output
OUTPUT is held to keep the low level output in upper stage.
In this stage, the clock signal terminal CLK in input terminal is high level, reset signal end RESET and signal input part
The signal of INPUT is low level, and the output signal of signal output part OUTPUT is low level.
5th stage T5, the signal of clock signal terminal are low level, at this point, since pull-up node PU is low level, second
Transistor M2 is off state, and signal output part OUTPUT keeps the low level output in upper stage.
In this stage, the letter of clock signal terminal CLK, reset signal end RESET and signal input part INPUT in input terminal
Number it is low level, the output signal of signal output part OUTPUT is low level.
In all stages, the signal of power end VGL is continuously low level.
After reseting stage T3, shift register continuously carries out fourth stage T4 and the 5th stage T5, until signal is defeated
Enter INPUT is held to receive high level signal again.
In the present embodiment, the signal of signal input part INPUT is pulse signal, is only high level in input phase；Letter
The output signal of number output terminal OUTPUT is pulse signal, is only high level in the output stage；The signal of reset signal end RESET
Only it is high level in reseting stage for pulse signal.
Embodiment two
Inventive concept based on above-described embodiment, the embodiment of the present invention additionally provide a kind of driving side of shift register
Method, applied to embodiment one provide shift register in, Fig. 5 be shift register provided in an embodiment of the present invention driving side
The flow chart one of method, wherein, shift register includes：Signal input part INPUT, reset signal end RESET, clock signal terminal
CLK, signal output part OUTPUT and power end VGL, pull-up sub-circuit, output sub-circuit, output control sub-circuit, such as Fig. 5 institutes
Show, the driving method of shift register provided in an embodiment of the present invention includes：
Step 100, in input phase, pull-up sub-circuit pulls up node and provides signal under the control of signal input part
The signal of input terminal.
Specifically, the signal of signal input part is pulse signal, in step 100, the signal of signal input part is high electricity
Flat, pull-up sub-circuit has drawn high the current potential of pull-up node.
Step 200, output the stage, output sub-circuit under the control of pull-up node, to signal output part provide clock
The clock signal of signal end；Output control sub-circuit provides power end under the control of clock signal terminal to signal output part
Signal.
Specifically, pull-up node, under the boot strap of capacitance, the current potential of pull-up node further raises, clock signal is
High level, the output signal of signal output part is high level, and control is exported when clock signal becomes low potential by high potential
The output signal moment of signal output part is pulled low to the low potential of power end by circuit.
The driving method of shift register provided in an embodiment of the present invention includes：In input phase, pull-up sub-circuit is being believed
Under the control of number input terminal, the signal that node provides signal input part is pulled up, in the output stage, output sub-circuit is saved in pull-up
Under the control of point, the clock signal of clock signal terminal is provided to signal output part；Output control sub-circuit is in clock signal terminal
Under control, the signal of power end is provided to signal output part, the embodiment of the present invention is by exporting control sub-circuit in clock signal
Under the control at end, as soon as the signal that power end is provided to signal output part causes the clock signal current potential of clock signal terminal to reduce,
Moment drags down the output signal of signal output part, reduces the trailing edge of output signal, avoids due to being missed caused by trailing edge
Output, ensure that job stability, use reliability and the display effect of display panel.
Optionally, Fig. 6 is the flowchart 2 of the driving method of shift register provided in an embodiment of the present invention, such as Fig. 6 institutes
Show, the driving method of shift register provided in an embodiment of the present invention further includes：
Step 300, in reseting stage, reset subcircuit pulls up node and signal is defeated under the control at reset signal end
Outlet provides the signal of power end.
Specifically, the signal at reset signal end is pulse signal, reset subcircuit is by pull-up node signal and signal output
The current potential at end drags down, to avoid noise.
Specifically, it is that N-type is thin with transistor M1, M2, M4 and M5 in shift register provided in an embodiment of the present invention
Exemplified by film transistor, the signal of power end is low level；In input phase, the signal of signal input part is high level；It is exporting
The signal of stage, clock signal terminal and signal output part is high level；In reseting stage, the signal at reset signal end is high electricity
It is flat.
Embodiment three
Inventive concept based on above-described embodiment, the embodiment of the present invention also provide a kind of gate driving circuit, and Fig. 7 is this hair
The structure diagram for the gate driving circuit that bright embodiment provides, as shown in fig. 7, raster data model provided in an embodiment of the present invention is electric
Road, including multiple cascade shift registers.
Specifically, as shown in fig. 7, the signal output part of N grades of shift registers and the signal of N+1 grades of shift registers
Input terminal connects, and the reset signal end of N grades of shift registers is connected with the signal output part of N+1 grades of shift registers.
As shown in fig. 7, the signal input part INPUT of N-1 grades of shift registers is connected with initial signal end STV, N-1
The signal output part OUTPUT of grade shift register is connected with the signal input part INPUT of N grades of shift registers, N-1 grades
The reset signal end RESET of shift register is connected with N grades of signal output part OUTPUT.
It should be noted that the signal of the clock signal terminal connection of adjacent shift register is reverse signal.
Wherein, shift register is the shift register that embodiment one provides, and realization principle is similar with effect is realized,
This is repeated no more.
There is the following to need to illustrate：
Attached drawing of the embodiment of the present invention pertain only to the present embodiments relate to structure, other structures, which can refer to, usually to be set
Meter.
In the case where there is no conflict, the feature in the embodiment of the present invention, that is, embodiment can be mutually combined to obtain new
Embodiment.
Although the embodiment disclosed by the embodiment of the present invention is as above, only the present invention is real for ease of understanding for the content
The embodiment applied example and used is not limited to the embodiment of the present invention.Skill in any fields of the embodiment of the present invention
Art personnel, can be in the form and details of implementation on the premise of the spirit and scope disclosed by the embodiment of the present invention are not departed from
It is upper to carry out any modification and variation, but the scope of patent protection of the embodiment of the present invention, it still must be with appended claims institute
Subject to the scope defined.
Claims (10)
1. a kind of shift register, which is characterized in that including：Pull up sub-circuit, output sub-circuit and output control sub-circuit；
The pull-up sub-circuit, is connected with signal input part and pull-up node, under the control of signal input part, pulling up
Node provides the signal of signal input part；
The output sub-circuit, is connected with pull-up node, signal output part and clock signal terminal, in the control of pull-up node
Under, to the clock signal of signal output part offer clock signal terminal；
The output control sub-circuit, is connected with clock signal terminal, signal output part and power end, in clock signal terminal
Under control, the signal of power end is provided to signal output part.
2. shift register according to claim 1, which is characterized in that the shift register further includes：Reset son electricity
Road；
The reset subcircuit is connected with pull-up node, reset signal end, signal output part and power end, for resetting letter
Under the control at number end, the signal that node and signal output part provide power end is pulled up.
3. shift register according to claim 1, which is characterized in that the pull-up sub-circuit includes：The first transistor；
The control pole of the first transistor and the first pole are connected with signal input part, and the second pole is connected with pull-up node.
4. shift register according to claim 1, which is characterized in that the output sub-circuit includes：Capacitance and second
Transistor；
The first end of the capacitance is connected with pull-up node, and second end is connected with signal output part；
The control pole of the second transistor is connected with pull-up node, and the first pole is connected with clock signal terminal, the second pole and signal
Output terminal connects.
5. shift register according to claim 1, which is characterized in that the output control sub-circuit includes：3rd is brilliant
Body pipe；
The control pole of the third transistor is connected with clock signal terminal, and the first pole is connected with power end, and the second pole and signal are defeated
Outlet connects.
6. shift register according to claim 2, which is characterized in that the reset subcircuit includes：4th transistor
With the 5th transistor；
The control pole of 4th transistor is connected with reset signal end, and the first pole is connected with pull-up node, the second pole and power supply
End connection；
The control pole of 5th transistor is connected with reset signal end, and the first pole is connected with signal output part, the second pole and electricity
Source connects.
7. shift register according to claim 5, which is characterized in that the third transistor is P-type TFT.
8. a kind of gate driving circuit, which is characterized in that posted including multiple cascade displacements as described in claim 1-7 is any
Storage.
9. a kind of driving method of shift register, which is characterized in that applied to any shift LDs of claim 1-7
In device, including：
In input phase, pull-up sub-circuit pulls up the signal that node provides signal input part under the control of signal input part；
In the output stage, output sub-circuit provides the clock of clock signal terminal to signal output part under the control of pull-up node
Signal；Output control sub-circuit provides the signal of power end to signal output part under the control of clock signal terminal.
10. according to the method described in claim 9, it is characterized in that, the method further includes：
In reseting stage, reset subcircuit pulls up node and signal output part provides power supply under the control at reset signal end
The signal at end.
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| CN201810003999.3A CN108053794A (en) | 2018-01-02 | 2018-01-02 | A kind of shift register and its driving method, gate driving circuit |
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| CN201810003999.3A CN108053794A (en) | 2018-01-02 | 2018-01-02 | A kind of shift register and its driving method, gate driving circuit |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140320466A1 (en) * | 2011-09-23 | 2014-10-30 | Hydis Technologies Co., Ltd. | Shift Register and Gate Driving Circuit Using the Same |
| CN104658505A (en) * | 2015-03-13 | 2015-05-27 | 京东方科技集团股份有限公司 | Shifting register, grid electrode driving circuit and related devices |
| CN104952417A (en) * | 2015-07-23 | 2015-09-30 | 合肥京东方光电科技有限公司 | Shift register unit and driving method thereof, grid drive circuit and display device |
| CN105096902A (en) * | 2015-09-28 | 2015-11-25 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, gate drive circuit and display device |
| CN105609136A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Shifting register unit, drive method, grid drive circuit and display device |
| CN105895045A (en) * | 2016-06-12 | 2016-08-24 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and driving method of gate drive circuit |
| CN106531117A (en) * | 2017-01-05 | 2017-03-22 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, gate integrated drive circuit and display device |
| CN107274856A (en) * | 2017-08-22 | 2017-10-20 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN107492338A (en) * | 2017-10-13 | 2017-12-19 | 京东方科技集团股份有限公司 | A kind of gate driving circuit and display device |
-
2018
- 2018-01-02 CN CN201810003999.3A patent/CN108053794A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140320466A1 (en) * | 2011-09-23 | 2014-10-30 | Hydis Technologies Co., Ltd. | Shift Register and Gate Driving Circuit Using the Same |
| CN104658505A (en) * | 2015-03-13 | 2015-05-27 | 京东方科技集团股份有限公司 | Shifting register, grid electrode driving circuit and related devices |
| CN104952417A (en) * | 2015-07-23 | 2015-09-30 | 合肥京东方光电科技有限公司 | Shift register unit and driving method thereof, grid drive circuit and display device |
| CN105096902A (en) * | 2015-09-28 | 2015-11-25 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, gate drive circuit and display device |
| CN105609136A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Shifting register unit, drive method, grid drive circuit and display device |
| CN105895045A (en) * | 2016-06-12 | 2016-08-24 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and driving method of gate drive circuit |
| CN106531117A (en) * | 2017-01-05 | 2017-03-22 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, gate integrated drive circuit and display device |
| CN107274856A (en) * | 2017-08-22 | 2017-10-20 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN107492338A (en) * | 2017-10-13 | 2017-12-19 | 京东方科技集团股份有限公司 | A kind of gate driving circuit and display device |
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