CN108052739A - Design express passway design method in integrated circuit semi-custom rear end - Google Patents
Design express passway design method in integrated circuit semi-custom rear end Download PDFInfo
- Publication number
- CN108052739A CN108052739A CN201711326399.2A CN201711326399A CN108052739A CN 108052739 A CN108052739 A CN 108052739A CN 201711326399 A CN201711326399 A CN 201711326399A CN 108052739 A CN108052739 A CN 108052739A
- Authority
- CN
- China
- Prior art keywords
- design
- data
- rear end
- mentioned
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of integrated circuit semi-custom rear ends to design express passway design method.Step S1：Rear end design tool obtains initial data and updates the data.Step S2：By comparing above-mentioned initial data and updating the data to form data difference information, and analyzed for above-mentioned data difference information and perform order to generate.Step S3：Above-mentioned execution order is performed to synthesize the design data for express passway design.Step S4：Above-mentioned design data is applied to actual engineering design to record crucial execution information.Step S5：It analyzes and judges whether above-mentioned crucial execution information meets default design standard.Design express passway design method in integrated circuit semi-custom rear end disclosed by the invention, rear end design is avoided to lag behind Front-end Design, make rear end design that can shift to an earlier date the design efficiency for carrying out, improving rear end design link synchronous with Front-end Design, shorten the entire chip design cycle.
Description
Technical field
The invention belongs to IC design industry designs to automate EDA technical fields, and in particular to a kind of integrated circuit
Design express passway design method in semi-custom rear end.
Background technology
At present, EDA technical fields are automated in IC design industry design, the design of semi-custom rear end is divided into flattening
Design method and Hierarchical Design method.With the continuous increase of footprint, to existing designing technique, especially to semidefinite
Rear end design processed proposes higher requirement.
When the design scale of chip is excessive, conventional flattening rear end design method needs to spend the unaffordable time
Cost, while result may be cannot get or result is very poor.Accordingly, it is considered to EDA design tools ability to bear and operation when
Between, for large-scale chip design object, stratification rear end design cycle must be used in the industry.
Compared with flattening flow, since Hierarchical Design can be such that the key Design link more than comparison synchronizes parallel
Design.However, during Hierarchical Design, set in Front-end Design with the design link needs order that rear end design is mutually connected
Meter.Simultaneously as the characteristics of rear end design cycle is long, can cause rear end to be compared in designing in current conventional design flow and lean on
Key Design link afterwards needs to wait the design data result of front that could carry out, so as to waste the substantial amounts of stand-by period.By
There are many additional work to do in Hierarchical Design flow, design cycle cycle and design complexities all substantially increase, such as
Where make in the design of stratification rear end its key Design rearward try one's best it is synchronous with Front-end Design carry out, effective shortening chip is set
It counts the cycle and improves design efficiency, there are no effective methods in conventional semi-custom rear end design at present to be realized,
Also the technical barrier urgently solved is needed in current stratification rear end design present situation.
The content of the invention
The present invention is directed to the situation of the prior art, for above-mentioned condition, provides a kind of integrated circuit semi-custom rear end design
Express passway design method.
The present invention is included using following technical scheme, the integrated circuit semi-custom rear end design express passway design method
Following steps：
Step S1：Rear end design tool obtains initial data and updates the data；
Step S2：By comparing above-mentioned initial data and updating the data to form data difference information, and for above-mentioned number
It is analyzed according to different information and performs order to generate；
Step S3：Above-mentioned execution order is performed to synthesize the design data for express passway design；
Step S4：Above-mentioned design data is applied to actual engineering design to record crucial execution information；
Step S5：It analyzes and judges whether above-mentioned crucial execution information meets default design standard, if meeting
Correct result data are exported, otherwise output error result data performs step S2 simultaneously.
According to above-mentioned technical proposal, in step sl, above-mentioned initial data includes original SDC files and original netlist text
Part, it is above-mentioned to update the data including update SDC files and update net meter file.
According to above-mentioned technical proposal, in step s 2, above-mentioned execution order includes but not limited to data and removes order, data
Processing order, Data Synthesis order and data contrast verification order.
According to above-mentioned technical proposal, in step s 2, above-mentioned data difference information includes the content and type of data.
According to above-mentioned technical proposal, in step s 2, rear end design tool is analyzed for data difference information, specifically
For：It is defined and confirms for the content and type of data.
According to above-mentioned technical proposal, in step s3, rear end design tool sequentially carries out data and removes order, data processing
Order, Data Synthesis order and data contrast verification order.
Express passway design method is designed in integrated circuit semi-custom rear end disclosed by the invention, and its advantage is, keeps away
Exempt from rear end design and lag behind Front-end Design, make rear end design that can shift to an earlier date progress synchronous with Front-end Design, improve rear end design ring
The design efficiency of section shortens the entire chip design cycle.
Description of the drawings
Fig. 1 is the FB(flow block) of the preferred embodiment of the present invention.
Fig. 2 is the flow diagram of the acquisition data portion of the preferred embodiment of the present invention.
The flow diagram of the execution command portion of Fig. 3 preferred embodiment of the present invention.
Fig. 4 is the flow diagram of the processing compounding design data portion of the preferred embodiment of the present invention.
Fig. 5 is the flow diagram of the proving correctness part of the preferred embodiment of the present invention.
Specific embodiment
The invention discloses a kind of integrated circuit semi-custom rear ends to design express passway design method, with reference to preferred reality
Example is applied, the specific embodiment of the present invention is further described.
Referring to Figure 1 of the drawings, Fig. 1 shows the tool of the integrated circuit semi-custom rear end design express passway design method
Body flow.Referring to Fig. 2 to Fig. 5 of attached drawing, it is preferable that design express passway design method bag in the integrated circuit semi-custom rear end
Include following steps：
Step S1：Rear end design tool obtains initial data and updates the data；
Step S2：By comparing above-mentioned initial data and updating the data to form data difference information, and for above-mentioned number
It is analyzed according to different information and performs order to generate；
Step S3：Above-mentioned execution order is performed to synthesize the design data (new data) for express passway design；
Step S4：Above-mentioned design data is applied to (import and perform) actual engineering design and performs letter to record key
Breath；
Step S5：It analyzes and judges whether above-mentioned crucial execution information meets default design standard, if meeting
Correct result data are exported, otherwise output error result data performs step S2 simultaneously.
Wherein, in step sl, above-mentioned initial data includes original SDC files and original netlist file, above-mentioned update number
According to including update SDC files and update net meter file.We define, initial data for data used in the current generation (including
The related data returned due to output error result data in step s 5), update the data for during Front-end Design
Complete but without the data generated by preamble design link.
Wherein, in step s 2, above-mentioned execution order includes but not limited to data stripping order, data processing command, number
According to synthetic order and data contrast verification order.
Wherein, in step s 2, above-mentioned data difference information includes the content and type of data.
Wherein, in step s 2, rear end design tool is analyzed for data difference information, is specially：For data
Content and type be defined and confirm.
Wherein, in step s3, rear end design tool sequentially carries out data and removes order, data processing command, data conjunction
Into order and data contrast verification order.We define, and link is removed in data, order are removed by running data, new and old
Data carry out data lift-off processing according to engineering design function, contents attribute and design phase definition etc..In data processing link
Nonuseable part in legacy data is removed, updates the data and extracts what new data needs retained.It will be new in Data Synthesis link
The useful content that legacy data is retained is integrated together again, forms a complete design data.Link is verified in data comparison
Integrality and Correctness checking are carried out for design data.
Wherein, in step s 4, correctness process of the final data in engineer application is completed by the step, so protected
Card data can ensure that the correct of actual engineering design link runs and obtain correct and effective design result, key link
For：New data imports, practical engineering application, and data run information record and the crucial data that perform export.It is believed that it is verifying
Obtained express passway design data is imported into actual engineering project by the correct sexual stage first, then is carried out simple and fast
The execution of speed, while the record work of key message is carried out in implementation procedure, it is analyzed finally by crucial execution information,
It is exported if analysis result meets design requirement through information otherwise output error result data, and feed back to execution command link
Section is handled again.
It is noted that after express passway design data is by verification of correctness, you can export and design ring to rear end
Section carries out engineering design, make subsequent rear end design link obtain upgrading in time with it is synchronous, avoid caused by designing pause the time
Waste problem, while newest design parameter is obtained by designed in advance and is determined for compliance with newly designed layout strategy in advance.
It is worth noting that, at the end of each step of step S1 to step S5, the data that generate this step and/
Or order is kept in designated position, so that next step is read and is used.
For a person skilled in the art, the technical solution recorded in foregoing embodiments can still be repaiied
Change or equivalent substitution is carried out to which part technical characteristic, within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in protection scope of the present invention.
Claims (6)
1. express passway design method is designed in a kind of integrated circuit semi-custom rear end, which is characterized in that comprises the following steps：
Step S1：Rear end design tool obtains initial data and updates the data；
Step S2：By comparing above-mentioned initial data and updating the data to form data difference information, and for above-mentioned data difference
Different information is analyzed performs order to generate；
Step S3：Above-mentioned execution order is performed to synthesize the design data for express passway design；
Step S4：Above-mentioned design data is applied to actual engineering design to record crucial execution information；
Step S5：It analyzes and judges whether above-mentioned crucial execution information meets default design standard, exported if meeting
Correct result data, otherwise output error result data perform step S2 simultaneously.
2. express passway design method is designed in integrated circuit semi-custom rear end according to claim 1, which is characterized in that
In step S1, above-mentioned initial data includes original SDC files and original netlist file, above-mentioned to update the data including update SDC texts
Part and update net meter file.
3. express passway design method is designed in integrated circuit semi-custom rear end according to claim 1, which is characterized in that
In step S2, above-mentioned execution order includes but not limited to data and removes order, data processing command, Data Synthesis order and data
Contrast verification order.
4. express passway design method is designed in integrated circuit semi-custom rear end according to claim 3, which is characterized in that
In step S2, above-mentioned data difference information includes the content and type of data.
5. express passway design method is designed in integrated circuit semi-custom rear end according to claim 4, which is characterized in that
In step S2, rear end design tool is analyzed for data difference information, is specially：Content and type for data carry out
Definition and confirmation.
6. express passway design method is designed in integrated circuit semi-custom rear end according to claim 3, which is characterized in that
In step S3, rear end design tool sequentially carries out data and removes order, data processing command, the comparison of Data Synthesis order and data
Verification command.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711326399.2A CN108052739B (en) | 2017-12-13 | 2017-12-13 | Method for designing quick channel of semi-custom back-end design of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711326399.2A CN108052739B (en) | 2017-12-13 | 2017-12-13 | Method for designing quick channel of semi-custom back-end design of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108052739A true CN108052739A (en) | 2018-05-18 |
| CN108052739B CN108052739B (en) | 2021-07-20 |
Family
ID=62132058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711326399.2A Active CN108052739B (en) | 2017-12-13 | 2017-12-13 | Method for designing quick channel of semi-custom back-end design of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108052739B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020059553A1 (en) * | 1998-01-30 | 2002-05-16 | Eng Tommy K. | Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information |
| CN1737807A (en) * | 2005-09-01 | 2006-02-22 | 上海交通大学 | Clock frequency divider capable of controlling spike and clock skew by front/back end cooperation |
| US7143341B1 (en) * | 2002-06-20 | 2006-11-28 | Cadence Design Systems | Method and apparatus for concurrent engineering and design synchronization of multiple tools |
| CN102354165A (en) * | 2011-05-30 | 2012-02-15 | 浙江中控技术股份有限公司 | Method for updating data online, controller and man-machine interactive system |
| CN102508660A (en) * | 2011-10-26 | 2012-06-20 | 青岛海信宽带多媒体技术有限公司 | Generation method and device of executable file |
| CN103023824A (en) * | 2012-12-11 | 2013-04-03 | 华为技术有限公司 | Peripheral component interconnect-express (PCIe) based data transmission system and method |
| CN103425804A (en) * | 2012-05-15 | 2013-12-04 | 北京华大九天软件有限公司 | Method for graphically displaying structure of clock system |
| CN106611084A (en) * | 2016-11-29 | 2017-05-03 | 北京集创北方科技股份有限公司 | Integrated circuit designing method and apparatus |
| CN107066681A (en) * | 2016-02-11 | 2017-08-18 | 三星电子株式会社 | The computer implemented method of integrated circuit and manufacture integrated circuit |
-
2017
- 2017-12-13 CN CN201711326399.2A patent/CN108052739B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020059553A1 (en) * | 1998-01-30 | 2002-05-16 | Eng Tommy K. | Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information |
| US7143341B1 (en) * | 2002-06-20 | 2006-11-28 | Cadence Design Systems | Method and apparatus for concurrent engineering and design synchronization of multiple tools |
| CN1737807A (en) * | 2005-09-01 | 2006-02-22 | 上海交通大学 | Clock frequency divider capable of controlling spike and clock skew by front/back end cooperation |
| CN102354165A (en) * | 2011-05-30 | 2012-02-15 | 浙江中控技术股份有限公司 | Method for updating data online, controller and man-machine interactive system |
| CN102508660A (en) * | 2011-10-26 | 2012-06-20 | 青岛海信宽带多媒体技术有限公司 | Generation method and device of executable file |
| CN103425804A (en) * | 2012-05-15 | 2013-12-04 | 北京华大九天软件有限公司 | Method for graphically displaying structure of clock system |
| CN103023824A (en) * | 2012-12-11 | 2013-04-03 | 华为技术有限公司 | Peripheral component interconnect-express (PCIe) based data transmission system and method |
| CN107066681A (en) * | 2016-02-11 | 2017-08-18 | 三星电子株式会社 | The computer implemented method of integrated circuit and manufacture integrated circuit |
| CN106611084A (en) * | 2016-11-29 | 2017-05-03 | 北京集创北方科技股份有限公司 | Integrated circuit designing method and apparatus |
Non-Patent Citations (5)
| Title |
|---|
| NADEEM N. ELEYAN,ET AL.: "Semi-Custom Design Flow: Leveraging Place and Route Tools in Custom Circuit Design", 《IEEE》 * |
| 孙书娟 等: "高性能DSP内核的层次化综合方法", 《第十八届计算机工程与工艺年会暨第四届微处理器技术论坛论文集》 * |
| 张玲: "JC2865芯片的后端设计与实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 王巧玉: "半定制大规模集成电路", 《微电子学与计算机》 * |
| 章华: "数字音频处理器芯片XD2309的后端设计与验证", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108052739B (en) | 2021-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101849235B (en) | Method and apparatus for memory abstraction and for word level net list reduction and verification using same | |
| CN101246516B (en) | Circuit design amending method capable of executing on computer system | |
| US20110035203A1 (en) | system level power evaluation method | |
| CN105138769B (en) | A kind of temporal model generation method and device for programmable circuit | |
| CN108170956A (en) | The sequential signing method and device of a kind of retention time | |
| CN109543212B (en) | Function test method and device of programmable logic device and computer storage medium | |
| US7822591B2 (en) | Logic circuit model conversion apparatus and method thereof; and logic circuit model conversion program | |
| US20190278884A1 (en) | Methodology To Create Constraints And Leverage Formal Coverage Analyzer To Achieve Faster Code Coverage Closure For An Electronic Structure | |
| CN113569524B (en) | Method for extracting clock tree based on comprehensive netlist in chip design and application | |
| CN110580393A (en) | Method for quickly converging and establishing time after modification of gate-level netlist | |
| CN115470748A (en) | Chip simulation acceleration method and device, electronic equipment and storage medium | |
| US20060101363A1 (en) | Method of associating timing violations with critical structures in an integrated circuit design | |
| US7908577B2 (en) | Apparatus and method for analyzing circuit specification description design | |
| CN116776793B (en) | Multi-period path constraint verification method combining static time sequence analysis and pre-simulation | |
| US7949509B2 (en) | Method and tool for generating simulation case for IC device | |
| Amarú et al. | SAT-sweeping enhanced for logic synthesis | |
| TW201218008A (en) | Intelligent architecture creator | |
| US8245163B1 (en) | Partial compilation of circuit design with new software version to obtain a complete compiled design | |
| CN108052739A (en) | Design express passway design method in integrated circuit semi-custom rear end | |
| Bombieri et al. | Integrating RTL IPs into TLM designs through automatic transactor generation | |
| CN102663041B (en) | Automatic extraction method oriented to data of deep web pages | |
| Lee et al. | Sequential engineering change order under retiming and resynthesis | |
| CN106897504A (en) | The method to form parameterized units is developed to IP modules | |
| CN113051868A (en) | DRC automatic interface realization method for integrated circuit manufacturing process rule verification | |
| Jong et al. | ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |