CN108052307A - The advanced operation method and system of processor floating point unit leading zero quantity - Google Patents
The advanced operation method and system of processor floating point unit leading zero quantity Download PDFInfo
- Publication number
- CN108052307A CN108052307A CN201711207258.9A CN201711207258A CN108052307A CN 108052307 A CN108052307 A CN 108052307A CN 201711207258 A CN201711207258 A CN 201711207258A CN 108052307 A CN108052307 A CN 108052307A
- Authority
- CN
- China
- Prior art keywords
- data
- leading zero
- level
- computing
- input data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
Abstract
The invention discloses a kind of advanced operation methods and system of processor floating point unit leading zero quantity.Wherein, this method includes decoding operation, obtains the leading zero number of every 8 data：It is 8n data A [8n 1 by data bit:0] 8 one group is divided into according to the order from a high position to low level, translates the number B of leading zero in n 8 data by n 84 decoders respectivelym[3:0]；Wherein, BmRepresent the leading zero number of 8 data of m groups, m=1~n, n=1~8；Data A [8n 1 are obtained by the advanced computing and logic judgment of every level-one in three-level:0] leading zero number per can two-by-two be divided input data in level-one pair, carries out computing parallel between each pair；Wherein, when n is odd number, last is to only there are one input datas.It is time-consuming longer that the present invention solves the problems, such as that multi-group data adds up, and has achieved the effect that quickly to provide leading zero quantity.
Description
Technical field
The invention belongs to floating-point operation field more particularly to a kind of advanced computings of processor floating point unit leading zero quantity
Method and system.
Background technology
Leading zero refers to scan 0 occurred between until first 1 since the highest order of binary data
Number.Determine leading zero number effect be to maintain character length it is consistent, facilitate character string sorting.Leading zero prediction passes through
The leading zero of mantissa's subtraction result is predicted to reduce the normalization shift computing required time, it is necessary to use leading zero count
Component.
China Patent Publication No. CN 102664637A, publication date are September in 2012 12, entitled " to determine binary number
According to the method and device of leading zero number " in disclose, the leading zero computing for 32 data, it is a kind of it is more common,
Easy method is it to be divided into 4 groups by a high position to low level, 8 digits are one group, and every group of data are compiled by an encoder
The output of code device then represents the number of the leading zero of each 8 data, and next judging the output of this four encoders successively is
The no number for being 8, leading zero then being drawn by accumulating operation.Accumulating operation is the side more generally used in leading zero computing
Method, shortcoming are that multiple data accumulations need to consume longer time.
The content of the invention
Present invention solves the technical problem that it is：It is leading to overcome the deficiencies of the prior art and provide a kind of processor floating point unit
It is time-consuming longer to solve the problems, such as that multi-group data adds up, has reached before quickly providing for the advanced operation method and system of zero quantity
Lead the effect of zero quantity.
The object of the invention is achieved by the following technical programs：According to an aspect of the invention, there is provided a kind of place
The advanced operation method of device floating point unit leading zero quantity is managed, the described method includes the following steps：Step 100：Decoding operation obtains
To the leading zero number of every 8 data：By the data A [8n-1 that data bit is 8n:0] according to the order from a high position to low level according to
It is secondary to be divided into 8 one group, the number B of leading zero in n 8 data is translated by n 8-4 decoder respectivelym[3:0]；Wherein, Bm
Represent the leading zero number of 8 data of m groups, m=1~n, n=1~8；Step 200：Pass through the advanced of every level-one in three-level
Computing and logic judgment obtain data A [8n-1:0] leading zero number, per can two-by-two be divided input data in level-one pair,
Carry out computing parallel between each pair；Wherein, when n is odd number, last is to only there are one input datas.
In the advanced operation method of above-mentioned processor floating point unit leading zero quantity, step 200 comprises the following steps：Step
210：First order input is the result B of decoding operationm[3:0], export as the leading zero number B of every 16 or 8 datajk[4:
0], logic judgment is according to the highest order B for being each pair input datam[3], result and/or input number from advanced computing are exported
According to low three Bm[2:0]；Wherein, k=j+1, j=1,3,5,7 and j≤n；Step 220：Second level input exports for the first order
Result Bjk[4:0], export as the leading zero number B of every 32,16 or 8 datajkrs[5:0], logic judgment foundation is
The highest order B of each pair input datajk[4], low four B of result and/or input data from advanced computing are exportedjk[3:
0]；Wherein, k=j+1, r=j+2, s=j+3, j=1,5 and j≤n；Step 230：The knot that third level input exports for the second level
Fruit Bjkrs[5:0], export as the leading zero number B of 8n data；Logic judgment is according to the highest order B for being each pair input datajkrs
[5], low four B of result and/or input data from advanced computing are exportedjkrs[4:0]；Wherein, n=1~8.
In the advanced operation method of above-mentioned processor floating point unit leading zero quantity, the decoding principle of 8-4 decoders is, when
When input data is 8 ' b00000000,4 ' b1000 of output data；When input data is 8 ' b00000001, output data
For 4 ' b0111；When input data is 8 ' b0000001x (x=0 or 1), 4 ' b0110 of output data；When input data is 8 '
During b000001xx, 4 ' b0101 of output data；When input data is 8 ' b00001xxx, 4 ' b0100 of output data；When
When input data is 8 ' b0001xxxx, 4 ' b0011 of output data；When input data is 8 ' b001xxxxx, output data
For 4 ' b0010；When input data is 8 ' b01xxxxxx, 4 ' b0001 of output data；When input data is 8 ' b1xxxxxxx
When, 4 ' b0000 of output data.
In the advanced operation method of above-mentioned processor floating point unit leading zero quantity, data Bm[3:0] operational formula is：
Bm[3]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] | A [0])；
Bm[2]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] |~A [0]) ＆ (A [3] | A [2] |~A
[1]) ＆ (A [3] |~A [2]) ＆ (~A [3])；
Bm[1]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | ((A [1] |~A [0]) ＆~A [1])) ＆ (A [5]
|~A [4]) ＆ (~A [5])；
Bm[0]=~(A [7] | (and A [6] | A [5] | (A [4] | A [3] | (A [2] | A [1] |~A [0]) ＆~A [2]) ＆~A
[4]) ＆~A [6])；
Wherein, A [p] be data A pth+1, Bm[q] (q=0~3) are data BmQ+1；Wherein, p=0~
7。
In the advanced operation method of above-mentioned processor floating point unit leading zero quantity, in every level-one logic judgment, to data
Divide two-by-two to method be：As n=1, B1As the leading zero quantity of computing, computing terminate；When 1<During n≤8, by BmBy height
Position to low level is divided into a pair two-by-two, carries out first order computing parallel between each pair, when n for odd number when last to less than two numbers
According to then retaining BnIt is not computing, BnValue be transferred directly to next stage, high position zero padding during digit deficiency；Or as n=2, B1With
B2Operation result B12As the leading zero quantity of computing, computing terminate；When 2<It, will into the second level logic judgment during n≤8
The output result B of first order logic judgmentjk(wherein k=j+1；J=1,3,5,7 and j≤n) big-endian is divided into one two-by-two
It is right, carry out second level logic judgment between each pair parallel, if last retains a data and do not transport to less than two data
Calculation is directly passed to next stage, high position zero padding, wherein k=j+1 during digit deficiency；J=1,3,5,7 and j≤n；Or when 2<n≤4
When, B1234As the leading zero quantity of computing, computing terminate；When 4<During n≤8, into third level logic judgment, the second level is patrolled
It collects two operation results judged and carries out computing.
In the advanced operation method of above-mentioned processor floating point unit leading zero quantity, include per the advanced computing of level-one：
In the advanced computing of level-one, if high-order numerical value Bj<8, then this is B to data leading zero numberjk=5 ' b { 00, Bj[2:0]}；It is if high
Bit value Bj=8, and low level numerical value Bk<8, then this is B to data leading zero numberjk=5 ' b { 01, Bk[2:0]}；If seniority top digit
Value Bj=8, and low level numerical value Bk=8, then this is B to data leading zero numberjk=5 ' b { 10,000 }；When n is odd number, most
It is latter to there was only Bn, only need to be in high-order zero padding, that is, exportable Bjk=5 ' b { 0, Bn[3:0]}；Wherein, k=j+1, j=1,3,5,7
And j≤n；In the advanced computing in the second level, if high-order numerical value Bjk<16, then this is B to data leading zero numberjkrs=6 ' b 00,
Bjk[3:0]}；If high-order numerical value Bjk=16, and low level numerical value Brs<16, then this is B to data leading zero numberjkrs=6 ' b
{01,Brs[3:0]}；If seniority top digit Bjk=16, and low level numerical value Brs=16, then this is B to data leading zero numberjkrs=6 ' b
{100,000}；When last is to there was only a data BjkWhen, it only need to be in high-order zero padding, that is, exportable Bjkrs=6 ' b { 0, Bjk[4:
0]}；Wherein, k=j+1, r=j+2, s=j+3, j=1,5 and j≤n；In the advanced computing of the third level, if high-order numerical value B1234<
32, then this is B=7 ' b { 00, B to data leading zero number1234[4:0]}；If high-order numerical value B1234=32, and low level numerical value
B5678<32, then this is B=7 ' b { 01, B to data leading zero number5678[4:0]}；If seniority top digit B1234=32, and low level numerical value
B5678=32, then this is B=7 ' b { 1,000,000 } to data leading zero number.
In the advanced operation method of above-mentioned processor floating point unit leading zero quantity, include per level-one logic judgment：
In level-one logic judgment, if BjHighest order Bj[3]=0, then B is exportedjk=5 ' b { 00, Bj[2:0]}；If Bj[3]=1, Bk
[3]=0, then B is exportedjk=5 ' b { 01, Bk[2:0]}；If BjAnd B [3]=1,k[3]=1, then B is exportedjk=5 ' b { 10,000 }；
When n is odd number, last is to there was only Bn, export Bjk=5 ' b { 0, Bn[3:0]}；Wherein, k=j+1, j=1,3,5,7 and j≤
n；In the logic judgment of the second level, if Bjk[4]=0, then B is exportedjkrs=6 ' b { 00, Bjk[3:0]}；If Bjk[4]=1, Brs
[4]=0, then B is exportedjkrs=6 ' b { 01, Brs[3:0]}；If BjkAnd B [4]=1,rs[4]=1, then B is exportedjkrs=6 ' b 100,
000}；When last is to there was only a data BjkWhen, export Bjkrs=6 ' b { 0, Bjk[4:0]}；Wherein, k=j+1, r=j+2, s
=j+3, j=1,5 and j≤n；In third level logic judgment, if B1234[5]=0, then B=7 ' b { 00, B are exported1234[4:
0]}；If B1234[5]=1 B5678[5]=0, then B=7 ' b { 01, B are exported5678[4:0]}；If B1234And B [5]=15678[5]=
1, then export B=7 ' b { 1,000,000 }.When only existing B1234, without B5678When, leading zero number B=B1234。
According to another aspect of the present invention, a kind of advanced computing system of processor floating point unit leading zero quantity is additionally provided
System, including：First module obtains the leading zero number of every 8 data for decoding operation：By the data A that data bit is 8n
[8n-1:0] 8 one group is divided into according to the order from a high position to low level, translates n 8 by n 8-4 decoder respectively
The number B of leading zero in datam[3:0]；Wherein, BmRepresent the leading zero number of 8 data of m groups, m=1~n, n=1~8；
Second module obtains data A [8n-1 for passing through the advanced computing of every level-one in three-level and logic judgment:0] leading zero
Number per can two-by-two be divided input data in level-one pair, carries out computing parallel between each pair；Wherein, when n is odd number, most
It is latter to only there are one input data.
In the advanced computing method, system of above-mentioned processor floating point unit leading zero quantity, the decoding principle of 8-4 decoders is,
When input data is 8 ' b00000000,4 ' b1000 of output data；When input data is 8 ' b00000001, number is exported
According to for 4 ' b0111；When input data is 8 ' b0000001x, 4 ' b0110 of output data；When input data is 8 '
During b000001xx, 4 ' b0101 of output data；When input data is 8 ' b00001xxx, 4 ' b0100 of output data；When
When input data is 8 ' b0001xxxx, 4 ' b0011 of output data；When input data is 8 ' b001xxxxx, output data
For 4 ' b0010；When input data is 8 ' b01xxxxxx, 4 ' b0001 of output data；When input data is 8 ' b1xxxxxxx
When, 4 ' b0000 of output data；Wherein, x=0 or 1.
In the advanced computing method, system of above-mentioned processor floating point unit leading zero quantity, data Bm[3:0] operational formula
For：
Bm[3]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] | A [0])；
Bm[2]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] |~A [0]) ＆ (A [3] | A [2] |~A
[1]) ＆ (A [3] |~A [2]) ＆ (~A [3])；
Bm[1]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | ((A [1] |~A [0]) ＆~A [1])) ＆ (A [5]
|~A [4]) ＆ (~A [5])；
Bm[0]=~(A [7] | (and A [6] | A [5] | (A [4] | A [3] | (A [2] | A [1] |~A [0]) ＆~A [2]) ＆~A
[4]) ＆~A [6])；
Wherein, A [p] be data A pth+1, Bm[q] (q=0~3) are data BmQ+1；Wherein, p=0~
7。
The present invention has the advantages that compared with prior art：
(1) the 8-4 decoders that the present invention uses can directly provide the control bit of selector compared to common 8-3 decoders
And carry-out bit, efficient arithmetic speed has been exchanged for the area cost of very little.
(2) it is a kind of supplementary means that the present invention reduces arithmetic speed to computing data to be divided two-by-two, can allow every level-one
In data press to concurrent operation, 8n data point are log to the series of computing needs2N, and the operation stage needed for computing one by one
Number is n-1, and the operation time per level-one is essentially identical, so the bigger advantage of the data bit of computing is more apparent.
(3) present invention is using the advantage of advanced computing, when obtaining the decoding result of 8-4 decoders, input data
Leading zero quantity just it has been determined that the result output that need to only coordinate control bit selection definite, without doing add operation again, is
The present invention is obtained where the core of efficient arithmetic speed.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this field
Technical staff will be apparent understanding.Attached drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings：
Fig. 1 is the functional block of the advanced operation method of processor floating point unit leading zero quantity provided in an embodiment of the present invention
Figure.
Specific embodiment
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although the disclosure is shown in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
Completely it is communicated to those skilled in the art.It should be noted that in the case where there is no conflict, embodiment in the present invention and
Feature in embodiment can be mutually combined.The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
Fig. 1 is the functional block of the advanced operation method of processor floating point unit leading zero quantity provided in an embodiment of the present invention
Figure.As described in Figure 1, the advanced operation method of the processor floating point unit leading zero quantity comprises the following steps：
Step 100：Decoding operation obtains the leading zero number of every 8 data：It is 8n data A [8n-1 by data bit:
0] 8 one group is divided into according to the order from a high position to low level, is translated respectively by n 8-4 decoder in n 8 data
The number B of leading zerom[3:0]；Wherein, BmRepresent the leading zero number of 8 data of m groups, m=1~n, n=1~8；
Step 200：Data A [8n-1 are obtained by the advanced computing and logic judgment of every level-one in three-level:0] leading
Zero number per can two-by-two be divided input data in level-one pair, carries out computing parallel between each pair；Wherein, when n is odd number,
Last is to only there are one input datas.
Step 200 comprises the following steps：
Step 210：First order input is the result B of decoding operationm[3:0], export as the leading of every 16 or 8 data
Zero number Bjk[4:0], logic judgment is according to the highest order B for being each pair input datam[3], the result from advanced computing is exported
And/or low three B of input datam[2:0]；Wherein, k=j+1, j=1,3,5,7 and j≤n；
Step 220：The result B that second level input exports for the first orderjk[4:0], export as every 32,16 or 8 digits
According to leading zero number Bjkrs[5:0], logic judgment is according to the highest order B for being each pair input datajk[4], output is from advanced
The result of computing and/or low four B of input datajk[3:0]；Wherein, k=j+1, r=j+2, s=j+3, j=1,5 and j≤
n；
Step 230：The result B that third level input exports for the second leveljkrs[5:0], export as the leading zero of 8n data
Number B；Logic judgment is according to the highest order B for being each pair input datajkrs[5], the result from preceding computing and/or input are exported
Low four B of datajkrs[4:0]；Wherein, n=1~8.
In above-described embodiment, the decoding principle of 8-4 decoders is, when input data is 8 ' b00000000, output data
For 4 ' b1000；When input data is 8 ' b00000001,4 ' b0111 of output data；When input data is 8 ' b0000001x
When (x=0 or 1), 4 ' b0110 of output data；When input data is 8 ' b000001xx, 4 ' b0101 of output data；When
When input data is 8 ' b00001xxx, 4 ' b0100 of output data；When input data is 8 ' b0001xxxx, output data
For 4 ' b0011；When input data is 8 ' b001xxxxx, 4 ' b0010 of output data；When input data is 8 ' b01xxxxxx
When, 4 ' b0001 of output data；When input data is 8 ' b1xxxxxxx, 4 ' b0000 of output data.Data Bm[3:0]
Operational formula be：
Bm[3]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] | A [0])；
Bm[2]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] |~A [0]) ＆ (A [3] | A [2] |~A
[1]) ＆ (A [3] |~A [2]) ＆ (~A [3])；
Bm[1]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | ((A [1] |~A [0]) ＆~A [1])) ＆ (A [5]
|~A [4]) ＆ (~A [5])；
Bm[0]=~(A [7] | (and A [6] | A [5] | (A [4] | A [3] | (A [2] | A [1] |~A [0]) ＆~A [2]) ＆~A
[4]) ＆~A [6])；
Wherein, A [p] (p=0~7) be data A pth+1, Bm[q] (q=0~3) are data BmQ+1.
In above-described embodiment, per level-one logic judgment in, data are divided two-by-two to method be：
As n=1, B1As the leading zero quantity of computing, computing terminate；When 1<During n≤8, by BmBig-endian two
Two are divided into a pair, carry out first order computing parallel between each pair, when n be odd number when last to less than two data, then retain
BnIt is not computing, BnValue be transferred directly to next stage, high position zero padding during digit deficiency；Or
As n=2, B1And B2Operation result B12As the leading zero quantity of computing, computing terminate；When 2<During n≤8,
Into second level logic judgment, by the output result B of first order logic judgmentjk(wherein k=j+1；J=1,3,5,7 and j≤n)
Big-endian is divided into a pair two-by-two, carries out second level logic judgment parallel between each pair, if last is to less than two numbers
According to, then retain a data and do not do computing and be directly passed to next stage, high position zero padding, wherein k=j+1 during digit deficiency；J=1,
3,5,7 and j≤n；Or
When 2<During n≤4, B1234As the leading zero quantity of computing, computing terminate；When 4<During n≤8, patrolled into the third level
It collects and judges, computing is carried out to two operation results of second level logic judgment.
In above-described embodiment, include per the advanced computing of level-one：
In the advanced computing of the first order, if high-order numerical value Bj<8, then this is B to data leading zero numberjk=5 ' b { 00, Bj
[2:0]}；If high-order numerical value Bj=8, and low level numerical value Bk<8, then this is B to data leading zero numberjk=5 ' b { 01, Bk[2:
0]}；If high-order numerical value Bj=8, and low level numerical value Bk=8, then this is B to data leading zero numberjk=5 ' b { 10,000 }；Work as n
For odd number when, last is to there was only Bn, only need to be in high-order zero padding, that is, exportable Bjk=5 ' b { 0, Bn[3:0]}；Wherein, k=j+1,
J=1,3,5,7 and j≤n；
In the advanced computing in the second level, if high-order numerical value Bjk<16, then this is B to data leading zero numberjkrs=6 ' b
{00,Bjk[3:0]}；If high-order numerical value Bjk=16, and low level numerical value Brs<16, then this is B to data leading zero numberjkrs=6 '
b{01,Brs[3:0]}；If seniority top digit Bjk=16, and low level numerical value Brs=16, then this is B to data leading zero numberjkrs=6 '
b{100,000}；When last is to there was only a data BjkWhen, it only need to be in high-order zero padding, that is, exportable Bjkrs=6 ' b { 0, Bjk[4:
0]}；Wherein, k=j+1, r=j+2, s=j+3, j=1,5 and j≤n；
In the advanced computing of the third level, if high-order numerical value B1234<32, then this to data leading zero number for B=7 ' b 00,
B1234[4:0]}；If high-order numerical value B1234=32, and low level numerical value B5678<32, then this is B=7 ' b to data leading zero number
{01,B5678[4:0]}；If seniority top digit B1234=32, and low level numerical value B5678=32, then this is B=7 ' to data leading zero number
b{1,000,000}。
In above-described embodiment, include per level-one logic judgment：
In first order logic judgment, if BjHighest order Bj[3]=0, then B is exportedjk=5 ' b { 00, Bj[2:0]}；If Bj
[3]=1, Bk[3]=0, then B is exportedjk=5 ' b { 01, Bk[2:0]}；If BjAnd B [3]=1,k[3]=1, then B is exportedjk=5 '
b{10,000}；When n is odd number, last is to there was only Bn, export Bjk=5 ' b { 0, Bn[3:0]}；Wherein, k=j+1, j=1,
3,5,7 and j≤n；
In the logic judgment of the second level, if Bjk[4]=0, then B is exportedjkrs=6 ' b { 00, Bjk[3:0]}；If Bjk[4]=
1, and Brs[4]=0, then B is exportedjkrs=6 ' b { 01, Brs[3:0]}；If BjkAnd B [4]=1,rs[4]=1, then B is exportedjkrs=
6’b{100,000}；When last is to there was only a data BjkWhen, export Bjkrs=6 ' b { 0, Bjk[4:0]}；Wherein, k=j+1,
R=j+2, s=j+3, j=1,5 and j≤n；
In third level logic judgment, if B1234[5]=0, then B=7 ' b { 00, B are exported1234[4:0]}；If B1234[5]
=1 and B5678[5]=0, then B=7 ' b { 01, B are exported5678[4:0]}；If B1234And B [5]=15678[5]=1, then B=is exported
7’b{1,000,000}.When only existing B1234, without B5678When, leading zero number B=B1234。
Below with 64 data instances, leading zero calculation that the present invention uses is first passes through 8-4 decoders and translates often
The number of leading zero in 8, then using the highest order of decoding value as judgment condition, the low level of decoding value is as the election select it is defeated
Go out value, the data of output valve also advanced computing simultaneously provide final result after judgement two-by-two step by step, are of leading zero
Number.
Embodiment：
As shown in Figure 1, it is provided during 64 data of processing, it is necessary to use eight decoders of B1~B8 by three-level logic judgment
As a result.By 64 data A [63:0] it is divided into 8 one group, respectively by eight 8-4 decoders, translates leading in eight 8 data
Zero number Bm[3:0] (m=1~8).Decoding principle is as shown in the table：
It is as shown in the table after completing decoding, into first order logic judgment：If 8 data A [63 of highest:56] translate
Data B1Numerical value is less than 8, i.e. B1[3]=0, then B12=5 ' b { 00, B1[2:0]}.If B1[3]=1 B2[3]=0, then B12=5 '
b{01,B2[2:0]}.If B1And B [3]=12[3]=1, then B12=5 ' b { 10,000 }.
In detection B1While value, B is detected3Whether numerical value is less than 8, if B3[3]=0, then B34=5 ' b { 00, B3[2:0]}；
If B3[3]=1 B4[3]=0, in computing B12While computing B34, B34=5 ' b { 01, B4[2:0]}；If B3And B [3]=14
[3]=1, then in computing B12While draw B34=5 ' b { 10,000 }.B56、B78Logic judgment and the same B of output principle12And B34。
In the logic judgment of the second level, highest order input B is detected first12Value, if B12[4]=0, then B1234=6 ' b
{00,B12[3:0]}.If B12[4]=1 B34[4]=0, then B1234=6 ' b { 01, B34[3:0]}.If B12And B [4]=134[4]
=1, then B1234=6 ' b { 100,000 }.B5678Logic judgment and the same B of output principle1234。
In third level logic judgment, highest order input B is detected first1234Value, if B1234[5]=0, then leading zero
Number B=7 ' b { 00, B1234[4:0]}.If B1234[5]=1 B5678[5]=0, then number B=7 ' b { 01, B of leading zero5678
[4:0]}.If B1234And B [5]=15678[5]=1, then B=7 ' b { 1,000,000 } i.e. 32.Computing terminates.
Above-mentioned logic discrimination condition can be clearly corresponding in the following table with exporting the relation of result.
In summary often during level-one logic judgment, corresponding input value or advanced is selected simply by control signal for step
Operation values are as output, without doing other computings (such as add operation) again, so as to save operation time.It, will at different levels
A pair of of concurrent operation, 64 data only need that by 3 grades of logic judgments leading zero quantity can be obtained, are less than two-by-two for data division
The time loss by 7 grades of logic judgments is needed from a high position to low level sequential operation.
The 8-4 decoders that the present embodiment uses can directly provide the control bit of selector compared to common 8-3 decoders
And carry-out bit, efficient arithmetic speed has been exchanged for the area cost of very little；It is the present embodiment drop to computing that data are divided two-by-two
A kind of supplementary means of low arithmetic speed, can allowing the data in every level-one, 8n data point need computing by concurrent operation
The series wanted is log2N, and the computing series needed for computing is n-1 one by one, the operation time per level-one is essentially identical, so fortune
The bigger advantage of data bit of calculation is more apparent；The present embodiment is using the advantage of advanced computing, is obtaining the decoding of 8-4 decoders
When as a result, the leading zero quantity of input data just it has been determined that the result output that need to only coordinate control bit selection definite, without
Add operation is done again, is the core place that the present invention obtains efficient arithmetic speed.
Device embodiment
The present embodiment additionally provides a kind of advanced arithmetic system of processor floating point unit leading zero quantity, including：First
Module and the second module.Wherein.
First module obtains the leading zero number of every 8 data for decoding operation：It is 8n data A by data bit
[8n-1:0] 8 one group is divided into according to the order from a high position to low level, translates n 8 by n 8-4 decoder respectively
The number B of leading zero in datam[3:0]；Wherein, BmRepresent the leading zero number of 8 data of m groups, m=1~n, n=1~8；
Second module obtains data A [8n-1 for passing through the advanced computing of every level-one in three-level and logic judgment:0]
Leading zero number, per can two-by-two be divided input data in level-one pair, carry out computing parallel between each pair；Wherein, n is strange
During number, last is to only there are one input datas.
In above-described embodiment, the decoding principle of 8-4 decoders is, when input data is 8 ' b00000000, output data
For 4 ' b1000；When input data is 8 ' b00000001,4 ' b0111 of output data；When input data is 8 ' b0000001x
When, 4 ' b0110 of output data；When input data is 8 ' b000001xx, 4 ' b0101 of output data；When input data is
During 8 ' b00001xxx, 4 ' b0100 of output data；When input data is 8 ' b0001xxxx, 4 ' b0011 of output data；
When input data is 8 ' b001xxxxx, 4 ' b0010 of output data；When input data is 8 ' b01xxxxxx, number is exported
According to for 4 ' b0001；When input data is 8 ' b1xxxxxxx, 4 ' b0000 of output data；Wherein, x=0 or 1.
In above-described embodiment, data Bm[3:0] operational formula is：
Bm[3]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] | A [0])；
Bm[2]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] |~A [0]) ＆ (A [3] | A [2] |~A
[1]) ＆ (A [3] |~A [2]) ＆ (~A [3])；
Bm[1]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | ((A [1] |~A [0]) ＆~A [1])) ＆ (A [5]
|~A [4]) ＆ (~A [5])；
Bm[0]=~(A [7] | (and A [6] | A [5] | (A [4] | A [3] | (A [2] | A [1] |~A [0]) ＆~A [2]) ＆~A
[4]) ＆~A [6])；
Wherein, A [p] be data A pth+1, Bm[q] (q=0~3) are data BmQ+1；Wherein, p=0~
7。
The 8-4 decoders that the present embodiment uses can directly provide the control bit of selector compared to common 8-3 decoders
And carry-out bit, efficient arithmetic speed has been exchanged for the area cost of very little；It is the present embodiment drop to computing that data are divided two-by-two
A kind of supplementary means of low arithmetic speed, can allowing the data in every level-one, 8n data point need computing by concurrent operation
The series wanted is log2N, and the computing series needed for computing is n-1 one by one, the operation time per level-one is essentially identical, so fortune
The bigger advantage of data bit of calculation is more apparent；The present embodiment is using the advantage of advanced computing, is obtaining the decoding of 8-4 decoders
When as a result, the leading zero quantity of input data just it has been determined that the result output that need to only coordinate control bit selection definite, without
Add operation is done again, is the core place that the present invention obtains efficient arithmetic speed.
Embodiment described above is the present invention more preferably specific embodiment, and those skilled in the art is in this hair
The usual variations and alternatives carried out in the range of bright technical solution should all include within the scope of the present invention.
Claims (10)
1. a kind of advanced operation method of processor floating point unit leading zero quantity, which is characterized in that the described method includes following
Step：
Step 100：Decoding operation obtains the leading zero number of every 8 data：By the data A [8n-1 that data bit is 8n:0]
8 one group is divided into according to the order from a high position to low level, before being translated respectively by n 8-4 decoder in n 8 data
Lead zero number Bm[3:0]；Wherein, BmRepresent the leading zero number of 8 data of m groups, m=1~n, n=1~8；
Step 200：Data A [8n-1 are obtained by the advanced computing and logic judgment of every level-one in three-level:0] leading zero
Number per can two-by-two be divided input data in level-one pair, carries out computing parallel between each pair；Wherein, when n is odd number, finally
It is a pair of that only there are one input datas.
2. the advanced operation method of processor floating point unit leading zero quantity according to claim 1, it is characterised in that：Step
Rapid 200 comprise the following steps：
Step 210：First order input is the result B of decoding operationm[3:0], export as the leading zero of every 16 or 8 data
Number Bjk[4:0], logic judgment is according to the highest order B for being each pair input datam[3], export result from advanced computing and/or
Low three B of input datam[2:0]；Wherein, k=j+1, j=1,3,5,7 and j≤n；
Step 220：The result B that second level input exports for the first orderjk[4:0], export as every 32,16 or 8 data
Leading zero number Bjkrs[5:0], logic judgment is according to the highest order B for being each pair input datajk[4], output is from advanced computing
Result and/or input data low four Bjk[3:0]；Wherein, k=j+1, r=j+2, s=j+3, j=1,5 and j≤n；
Step 230：The result B that third level input exports for the second leveljkrs[5:0], export as the leading zero number B of 8n data；
Logic judgment is according to the highest order B for being each pair input datajkrs[5], result and/or input data from advanced computing are exported
Low four Bjkrs[4:0]；Wherein, n=1~8.
3. the advanced operation method of floating point unit leading zero quantity according to claim 1, it is characterised in that：8-4 is decoded
The decoding principle of device is, when input data is 8 ' b00000000,4 ' b1000 of output data；When input data is 8 '
During b00000001,4 ' b0111 of output data；When input data is 8 ' b0000001x, 4 ' b0110 of output data；When
When input data is 8 ' b000001xx, 4 ' b0101 of output data；When input data is 8 ' b00001xxx, output data
For 4 ' b0100；When input data is 8 ' b0001xxxx, 4 ' b0011 of output data；When input data is 8 ' b001xxxxx
When, 4 ' b0010 of output data；When input data is 8 ' b01xxxxxx, 4 ' b0001 of output data；When input data is
During 8 ' b1xxxxxxx, 4 ' b0000 of output data；Wherein, x=0 or 1.
4. the advanced operation method of floating point unit leading zero quantity according to claim 1 or 2, it is characterised in that：Data Bm
[3:0] operational formula is：
Bm[3]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] | A [0])；
Bm[2]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] |~A [0]) ＆ (A [3] | A [2] |~A [1]) ＆ (A
[3] |~A [2]) ＆ (~A [3])；
Bm[1]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | ((A [1] |~A [0]) ＆~A [1])) ＆ (A [5] |~A
[4]) ＆ (~A [5])；
Bm[0]=~(A [7] | (and A [6] | A [5] | (A [4] | A [3] | (A [2] | A [1] |~A [0]) ＆~A [2]) ＆~A [4]) ＆~
A[6])；
Wherein, A [p] be data A pth+1, Bm[q] (q=0~3) are data BmQ+1；Wherein, p=0~7.
5. the advanced operation method of floating point unit leading zero quantity according to claim 1 or 2, it is characterised in that：It is each
Grade logic judgment in, data are divided two-by-two to method be：
As n=1, B1As the leading zero quantity of computing, computing terminate；When 1<During n≤8, by BmBig-endian divides two-by-two
For a pair, carry out first order computing parallel between each pair, last then retains B to less than two data when n is odd numbernNo
It is computing, BnValue be transferred directly to next stage, high position zero padding during digit deficiency；Or
As n=2, B1And B2Operation result B12As the leading zero quantity of computing, computing terminate；When 2<During n≤8, into
Two-level logic judges, by the output result B of first order logic judgmentjk(wherein k=j+1；J=1,3,5,7 and j≤n) by a high position
It is divided into a pair two-by-two to low level, carries out second level logic judgment parallel between each pair, if last protects less than two data
A data is stayed not do computing and are directly passed to next stage, high position zero padding, wherein k=j+1 during digit deficiency；J=1,3,5,7 and
j≤n；Or
When 2<During n≤4, B1234As the leading zero quantity of computing, computing terminate；When 4<During n≤8, sentence into third level logic
It is disconnected, computing is carried out to two operation results of second level logic judgment.
6. the advanced operation method of floating point unit leading zero quantity according to claim 5, it is characterised in that：Surpass per level-one
Preceding computing includes：
In the advanced computing of the first order, if high-order numerical value Bj<8, then this is B to data leading zero numberjk=5 ' b { 00, Bj[2:
0]}；If high-order numerical value Bj=8, and low level numerical value Bk<8, then this is B to data leading zero numberjk=5 ' b { 01, Bk[2:0]}；
If high-order numerical value Bj=8, and low level numerical value Bk=8, then this is B to data leading zero numberjk=5 ' b { 10,000 }；When n is strange
During number, last is to there was only Bn, only need to be in high-order zero padding, that is, exportable Bjk=5 ' b { 0, Bn[3:0]}；Wherein, k=j+1, j=
1,3,5,7 and j≤n；
In the advanced computing in the second level, if high-order numerical value Bjk<16, then this is B to data leading zero numberjkrs=6 ' b { 00, Bjk
[3:0]}；If high-order numerical value Bjk=16, and low level numerical value Brs<16, then this is B to data leading zero numberjkrs=6 ' b 01,
Brs[3:0]}；If seniority top digit Bjk=16, and low level numerical value Brs=16, then this is B to data leading zero numberjkrs=6 ' b
{100,000}；When last is to there was only a data BjkWhen, it only need to be in high-order zero padding, that is, exportable Bjkrs=6 ' b { 0, Bjk[4:
0]}；Wherein, k=j+1, r=j+2, s=j+3, j=1,5 and j≤n；
In the advanced computing of the third level, if high-order numerical value B1234<32, then this is B=7 ' b { 00, B to data leading zero number1234
[4:0]}；If high-order numerical value B1234=32, and low level numerical value B5678<32, then this to data leading zero number for B=7 ' b 01,
B5678[4:0]}；If seniority top digit B1234=32, and low level numerical value B5678=32, then this to data leading zero number for B=7 ' b 1,
000,000}。
7. the advanced operation method of floating point unit leading zero quantity according to claim 5, it is characterised in that：It is patrolled per level-one
It collects and judges to include：
In first order logic judgment, if BjHighest order Bj[3]=0, then B is exportedjk=5 ' b { 00, Bj[2:0]}；If Bj[3]
=1, and Bk[3]=0, then B is exportedjk=5 ' b { 01, Bk[2:0]}；If BjAnd B [3]=1,k[3]=1, then B is exportedjk=5 ' b
{10,000}；When n is odd number, last is to there was only Bn, export Bjk=5 ' b { 0, Bn[3:0]}；Wherein, k=j+1, j=1,
3,5,7 and j≤n；
In the logic judgment of the second level, if Bjk[4]=0, then B is exportedjkrs=6 ' b { 00, Bjk[3:0]}；If Bjk[4]=1, and
Brs[4]=0, then B is exportedjkrs=6 ' b { 01, Brs[3:0]}；If BjkAnd B [4]=1,rs[4]=1, then B is exportedjkrs=6 ' b
{100,000}；When last is to there was only a data BjkWhen, export Bjkrs=6 ' b { 0, Bjk[4:0]}；Wherein, k=j+1, r=
J+2, s=j+3, j=1,5 and j≤n；
In third level logic judgment, if B1234[5]=0, then B=7 ' b { 00, B are exported1234[4:0]}；If B1234[5]=1 and
B5678[5]=0, then B=7 ' b { 01, B are exported5678[4:0]}；If B1234And B [5]=15678[5]=1, then export B=7 ' b 1,
000,000}.When only existing B1234, without B5678When, leading zero number B=B1234。
8. a kind of advanced arithmetic system of processor floating point unit leading zero quantity, it is characterised in that including：
First module obtains the leading zero number of every 8 data for decoding operation：By the data A [8n- that data bit is 8n
1:0] 8 one group is divided into according to the order from a high position to low level, n 8 data is translated by n 8-4 decoder respectively
The number B of middle leading zerom[3:0]；Wherein, BmRepresent the leading zero number of 8 data of m groups, m=1~n, n=1~8；
Second module obtains data A [8n-1 for passing through the advanced computing of every level-one in three-level and logic judgment:0] before
Zero number is led, per can two-by-two be divided input data in level-one pair, carries out computing parallel between each pair；Wherein, n is odd number
When, last is to only there are one input datas.
9. the advanced arithmetic system of floating point unit leading zero quantity according to claim 8, it is characterised in that：8-4 is decoded
The decoding principle of device is, when input data is 8 ' b00000000,4 ' b1000 of output data；When input data is 8 '
During b00000001,4 ' b0111 of output data；When input data is 8 ' b0000001x, 4 ' b0110 of output data；When
When input data is 8 ' b000001xx, 4 ' b0101 of output data；When input data is 8 ' b00001xxx, output data
For 4 ' b0100；When input data is 8 ' b0001xxxx, 4 ' b0011 of output data；When input data is 8 ' b001xxxxx
When, 4 ' b0010 of output data；When input data is 8 ' b01xxxxxx, 4 ' b0001 of output data；When input data is
During 8 ' b1xxxxxxx, 4 ' b0000 of output data；Wherein, x=0 or 1.
10. the advanced arithmetic system of floating point unit leading zero quantity according to claim 9, it is characterised in that：Data Bm
[3:0] operational formula is：
Bm[3]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] | A [0])；
Bm[2]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | A [1] |~A [0]) ＆ (A [3] | A [2] |~A [1]) ＆ (A
[3] |~A [2]) ＆ (~A [3])；
Bm[1]=~(A [7] | A [6] | A [5] | A [4] | A [3] | A [2] | ((A [1] |~A [0]) ＆~A [1])) ＆ (A [5] |~A
[4]) ＆ (~A [5])；
Bm[0]=~(A [7] | (and A [6] | A [5] | (A [4] | A [3] | (A [2] | A [1] |~A [0]) ＆~A [2]) ＆~A [4]) ＆~
A[6])；
Wherein, A [p] be data A pth+1, Bm[q] (q=0~3) are data BmQ+1；Wherein, p=0~7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711207258.9A CN108052307B (en) | 2017-11-27 | 2017-11-27 | Advanced operation method and system for leading zero number of floating point unit of processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711207258.9A CN108052307B (en) | 2017-11-27 | 2017-11-27 | Advanced operation method and system for leading zero number of floating point unit of processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108052307A true CN108052307A (en) | 2018-05-18 |
| CN108052307B CN108052307B (en) | 2020-07-03 |
Family
ID=62120588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711207258.9A Active CN108052307B (en) | 2017-11-27 | 2017-11-27 | Advanced operation method and system for leading zero number of floating point unit of processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108052307B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109960486A (en) * | 2019-02-14 | 2019-07-02 | 安谋科技（中国）有限公司 | Binary data processing method and its device, medium and system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3453452B2 (en) * | 1995-05-19 | 2003-10-06 | キヤノン株式会社 | Decryption device |
| US20080144717A1 (en) * | 2006-12-15 | 2008-06-19 | Arcsoft, Inc. | Variable length decoding method |
| CN105468331A (en) * | 2014-09-26 | 2016-04-06 | Arm有限公司 | Standalone floating-point conversion unit |
| CN105786444A (en) * | 2014-12-26 | 2016-07-20 | 联想(北京)有限公司 | Detection method and apparatus for leading zeros in mantissas of floating-point number |
-
2017
- 2017-11-27 CN CN201711207258.9A patent/CN108052307B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3453452B2 (en) * | 1995-05-19 | 2003-10-06 | キヤノン株式会社 | Decryption device |
| US20080144717A1 (en) * | 2006-12-15 | 2008-06-19 | Arcsoft, Inc. | Variable length decoding method |
| CN105468331A (en) * | 2014-09-26 | 2016-04-06 | Arm有限公司 | Standalone floating-point conversion unit |
| CN105786444A (en) * | 2014-12-26 | 2016-07-20 | 联想(北京)有限公司 | Detection method and apparatus for leading zeros in mantissas of floating-point number |
Non-Patent Citations (1)
| Title |
|---|
| 邰强强等: "基于浮点融合乘加部件的前导零预测与检测方法研究", 《第十六届计算机工程与工艺年会受第二届微处理器技术论坛论文集》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109960486A (en) * | 2019-02-14 | 2019-07-02 | 安谋科技（中国）有限公司 | Binary data processing method and its device, medium and system |
| CN109960486B (en) * | 2019-02-14 | 2021-06-25 | 安谋科技（中国）有限公司 | Binary data processing method, and apparatus, medium, and system thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108052307B (en) | 2020-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE69736105T2 (en) | HIERARCHICAL SEARCH LOGGING FOR UNLAWFUL LOADING / MEMORY EXECUTION CONTROL | |
| CN1113279C (en) | Process for automatic fault diagnosis | |
| CN107340993A (en) | A kind of apparatus and method for the neural network computing for supporting less digit floating number | |
| CN1100289C (en) | Method and device for determining number of leading zero or 1 in binary data threshold | |
| CN107305485A (en) | It is a kind of to be used to perform the device and method that multiple floating numbers are added | |
| CN104536911B (en) | The cache memory and its processing method that a kind of multichannel group is connected | |
| CN109587483A (en) | Code stream extraction module | |
| CN106775573A (en) | A kind of potential target sort method based on FPGA | |
| CN108052307A (en) | The advanced operation method and system of processor floating point unit leading zero quantity | |
| CN103746706B (en) | Test data compression based on double distance of swimming alternate coded and decompression method | |
| DE102018129032A1 (en) | HARDWARE ACCESSORIES FOR SQL SCANS | |
| CN110473593A (en) | A kind of Smith-Waterman algorithm implementation method and device based on FPGA | |
| CN104243095A (en) | Code word type blind identification method for convolutional code and linear block code | |
| CN103746704B (en) | Test data of chip transmission methods based on double distance of swimming alternate coded | |
| DE2364865A1 (en) | EXPANDED MEMORY ADDRESS FORMATION SYSTEM OF A DIGITAL COMPUTER SYSTEM | |
| CN105786444B (en) | A kind of floating number mantissa leading zero detection method and device | |
| CN112651552A (en) | Electric power big data based industrial structure optimization method and device and storage medium | |
| CN1936887A (en) | Automatic text classification method based on classification concept space | |
| CN1160630C (en) | Content addressable memory addressable by redundant form input data | |
| CN1144124C (en) | Program execution method and device using the same | |
| CN109783698A (en) | Industrial production data entity recognition method based on Merkle-tree | |
| CN104598205A (en) | Sorting system and method for dataflow of function block diagram | |
| CN101330620B (en) | Method and apparatus for encoding and decoding audio and video data | |
| CN101819513A (en) | Method for evaluating absolute value of true code from complementary code | |
| CN106406811B (en) | A kind of data flow division running gear and method based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |