CN108037696B - Control system for automatically tracking motor in FSO (free space operation) equipment and signal processing method thereof - Google Patents
Control system for automatically tracking motor in FSO (free space operation) equipment and signal processing method thereof Download PDFInfo
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- CN108037696B CN108037696B CN201711243263.5A CN201711243263A CN108037696B CN 108037696 B CN108037696 B CN 108037696B CN 201711243263 A CN201711243263 A CN 201711243263A CN 108037696 B CN108037696 B CN 108037696B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
Abstract
The invention discloses a control system for automatically tracking a motor in FSO equipment, which comprises: the system comprises a signal light detector, a beacon light detector, an A/D converter, an FPGA, a D/A converter, a motor driver and a clock driver, wherein the A/D converter and the FPGA are respectively connected with the signal light detector and the beacon light detector; the invention also provides a signal processing method of the control system. The signal light signals and the beacon light signals obtained by the signal light detector and the beacon light detector are converted in the A/D converter and analyzed and compared in the FPGA to obtain the motor rotating speed digital signals and the motor direction control signals required by the motor, the motor rotating speed digital signals are converted into motor rotating speed analog signals through the D/A converter, and the motor driver regulates the motor according to the motor direction control signals and the motor rotating speed analog signals, so that the normal communication of the FSO equipment is ensured.
Description
Technical Field
The invention relates to the technical field of mobile communication, in particular to a control system and a signal processing method for a motor in automatic tracking FSO (frequency selective input/output) equipment.
Background
When the train runs at a high speed (the speed per hour is more than 300km/h), the mobile wireless network in the train is unstable and basically unavailable, and for passengers who use the intelligent terminal on a high-speed rail to surf the internet through the mobile wireless network, the passengers can not surf the internet basically under the condition. In order to solve the problem that high-speed rail passengers cannot surf the internet or surf the internet slowly, stable broadband access can be provided for the passengers by using an FSO (Free Space Optical communication) technology, but the FSO technology is required to be adopted for realizing the access. The automatic tracking technology is adopted, the adjustment of the light beam is particularly critical, and a control system and a corresponding signal processing method are needed.
Accordingly, the prior art is deficient and needs improvement.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a control system for automatically tracking a motor in FSO equipment and a signal processing method thereof are provided, and stable broadband service is provided for passengers on high-speed rails.
the technical scheme of the invention is as follows: there is provided a control system for automatically tracking a motor in an FSO device, comprising: the system comprises a signal light detector, a beacon light detector, a first A/D converter connected with the signal light detector, a second A/D converter connected with the beacon light detector, an FPGA connected with the first A/D converter and the second A/D converter, a D/A converter connected with the FPGA, a motor driver connected with the D/A converter, and a clock driver respectively connected with the first A/D converter, the second A/D converter and the FPGA; the motor driver is connected with the FPGA; the FPGA comprises: the device comprises a clock management module, a beacon light coarse adjustment processing module, a signal light fine adjustment processing module and a motor control processing module, wherein the beacon light coarse adjustment processing module and the signal light fine adjustment processing module are respectively connected with the clock management module; the clock management module is connected with the clock driver, the signal light fine adjustment processing module is connected with the first A/D converter, the beacon light coarse adjustment processing module is connected with the second A/D converter, the motor control processing module is respectively connected with the D/A converter and the motor driver, and the motor driver is connected with the motor. The signal light detector is used for detecting signal light and converting the light signal into an analog signal, the beacon light detector is used for detecting beacon light and converting the light signal into an analog signal, the first A/D converter and the second A/D converter are used for converting the analog signal into a digital signal, the FPGA is used for processing the digital signal transmitted by the first A/D converter and the second A/D converter and outputting a direction control signal and a motor rotating speed digital signal of a motor, the D/A converter is used for converting the motor rotating speed digital signal output by the FPGA into a motor rotating speed analog signal, and the motor driver is used for driving the motor. The clock driver is used for providing synchronous clock signals for the first A/D converter, the second A/D converter and the FPGA.
Further, the control system for automatically tracking the motor in the FSO device further comprises: the high-gain MMICs are arranged between the signal light detector and the first A/D converter and between the beacon light detector and the second A/D converter, and the position sensor and the circuit system are respectively connected with the FPGA; the first A/D converter is connected with the signal light detector through a high-gain MMIC, the second A/D converter is connected with the beacon light detector through a high-gain MMIC, and the position sensor is arranged on the motor. The high-gain MMIC is used for amplifying analog signals obtained by the signal light detector and the beacon light detector. The position sensor is used for detecting whether the motor is in a zero position. The circuitry is to provide an initial reset signal.
Further, the signal photodetector and the beacon photodetector are each a four-Quadrant Photodetector (QPD), and the first a/D converter includes: the first high-precision high-speed 2-path A/D converter and the second high-precision high-speed 2-path A/D converter are connected in series, the second A/D converter comprises a third high-precision high-speed 2-path A/D converter and a fourth high-precision high-speed 2-path A/D converter, the first high-precision high-speed 2-path A/D converter and the second high-precision high-speed 2-path A/D converter correspond to four quadrant signals of the signal light detector, the third high-precision high-speed 2-path A/D converter and the fourth high-precision high-speed 2-path A/D converter correspond to four quadrant signals of the beacon light detector, the D/A converter is a high-resolution high-speed D/A converter, and the clock driver is a 1:5 clock driver. The clock driver is used for providing synchronous clocks for the first high-precision high-speed 2-path A/D converter, the second high-precision high-speed 2-path A/D converter, the third high-precision high-speed 2-path A/D converter, the fourth high-precision high-speed 2-path A/D converter and the FPGA.
Further, the signal light fine-tuning signal processing module includes: the first 4 paths of 10 bit comparators are respectively connected with the first 4 paths of 10 bit comparators and used for fine-tuning the 1 st path of data sampling, fine-tuning the 2 nd path of data sampling, fine-tuning the 3 rd path of data sampling and fine-tuning the 4 th path of data sampling; the fine-tuning 1 st data sampling and the fine-tuning 2 nd data sampling are respectively connected with a clock management module and a first high-precision high-speed 2-way A/D converter, the fine-tuning 3 rd data sampling and the fine-tuning 4 th data sampling are respectively connected with the clock management module and a second high-precision high-speed 2-way A/D converter, and the first 4-way 10-bit comparator is connected with the motor control processing module; the beacon light coarse adjustment processing module comprises: the second 4 paths of 10 bit comparators are respectively connected with the second 4 paths of 10 bit comparators and used for roughly adjusting the 1 st path of data sampling, roughly adjusting the 2 nd path of data sampling, roughly adjusting the 3 rd path of data sampling and roughly adjusting the 4 th path of data sampling; the 1 st data sampling and the 2 nd data sampling are respectively connected with a clock management module and a third high-precision high-speed 2-way A/D converter, the 3 rd data sampling and the 4 th data sampling are respectively connected with the clock management module and a fourth high-precision high-speed 2-way A/D converter, and the 4 th 10-way bit comparator is connected with the motor control processing module; the motor control processing module includes: the control module, with the RAM module that control module connects, control module respectively with first 4 way 10 bit comparator, second 4 way 10 bit comparator, motor drive and clock management module are connected, the RAM module respectively with clock management module and DA converter are connected, the storage has the motor speed digital information of control motor under the different circumstances in the RAM module, and the RAM module corresponds different motor speed digital information according to the address of difference and writes in the good motor speed digital information of debugging. The motor rotating speed digital information in the RAM is provided by a circuit system of the FSO system in advance.
Further, the signal light detector is QP20-6TO, the beacon light detector is QP100-6SMD, and the clock driver is 100MHz TTL 1: the clock driver 5 can select P2I2305NZG, the first A/D converter and the second A/D converter are both AD9218, the FPGA is XC2C256-TQG144, and the D/A converter is AD 9754.
further, the high-gain MMIC is INA-02186.
The invention also provides a signal processing method, which comprises the following steps:
s1: the signal light detector and the beacon light detector respectively detect the signal light and the beacon light, respectively obtain a signal light analog signal and a beacon light analog signal, and respectively transmit the obtained signal light analog signal and beacon light analog signal to the first A/D converter and the second A/D converter.
S2: the first A/D converter and the second A/D converter respectively perform A/D conversion on the obtained signal light analog signal and the obtained beacon light analog signal under the synchronous clock of the clock driver; and transmitting the converted signal light digital signal and the beacon light digital signal to the FPGA.
S3: the FPGA analyzes and processes the signal light digital signals and the beacon light digital signals under the synchronous clock of the clock driver to obtain motor rotating speed digital signals and motor direction control signals, and the motor rotating speed digital signals and the motor direction control signals are respectively transmitted to the D/A converter and the motor driver.
s4: the D/A converter performs D/A conversion on the obtained motor rotating speed digital signal under the synchronous clock of the clock driver, and transmits the converted motor rotating speed analog signal to the motor driver.
S5: the motor driver combines the obtained motor rotating speed analog signal and the motor direction control signal to control the motor.
Further, the signal processing method further includes, in step S1, amplifying the obtained signal optical analog signal and the beacon optical analog signal by a high-gain MMIC, and in step S2, transmitting an auxiliary signal to the FPGA, the auxiliary signal including: the system comprises an indication signal and an initial reset signal which can not rotate after the motor rotates to a zero position and a maximum range, wherein the initial reset signal is used for indicating the system to initialize and comprises the initialization of the running of a CPU (central processing unit) in the system, the initialization of the logic relation in the FPGA and the reset generated by an internal control time sequence signal in the FPGA, and the motor rotating speed digital information for controlling the motor to rotate is written into an RAM (random access memory) module.
Further, in step S3, the clock management module receives the synchronous clock signal of the clock driver and divides the synchronous clock signal into at least nine, the fine-tuned 1 st data sample and the fine-tuned 2 nd data sample respectively receive the digital signal converted by the first high-precision high-speed 2-way a/D converter and a synchronous clock signal distributed by the clock management module, the fine-tuned 3 rd data sample and the fine-tuned 4 th data sample respectively receive the digital signal converted by the second high-precision high-speed 2-way a/D converter and a synchronous clock signal distributed by the clock management module, the fine-tuned 1 st data sample, the fine-tuned 2 nd data sample, the fine-tuned 3 rd data sample and the fine-tuned 4 th data sample respectively sample and transmit the sampled digital signals to the first 4-way 10 comparator, the first 4-way 10 comparator compares and analyzes the four sets of sampled digital signals, obtaining a first control coding signal and outputting the first control coding signal to a motor control processing module; the 1 st path of coarse data sampling and the 2 nd path of coarse data sampling respectively receive the digital signal converted by the third high-precision high-speed 2-path A/D converter and a synchronous clock signal distributed by the clock management module, the 3 rd path of coarse data sampling and the 4 th path of coarse data sampling respectively receive the digital signal converted by the fourth high-precision high-speed 2-path A/D converter and a synchronous clock signal distributed by the clock management module, the 1 st data sampling, the 2 nd data sampling, the 3 rd data sampling and the 4 th data sampling are sampled and sampled respectively, and sampled digital signals are transmitted to a 4 th 10-way second comparator, and the 4 th 10-way second comparator compares and analyzes the four groups of sampled digital signals to obtain a second control coding signal and outputs the second control coding signal to the motor control processing module; the control module receives and analyzes the first control coding signal, the second control coding signal, a synchronous clock signal and the auxiliary signal to obtain an address signal and a motor direction control signal, the control module respectively sends the address signal and the motor direction control signal to the RAM module and the motor driver, the control module reads out motor rotating speed digital information corresponding to the address signal in the RAM module under the synchronous clock to obtain motor rotating speed digital information corresponding to the address signal, and the RAM module outputs the motor rotating speed digital information to the high-resolution high-speed D/A converter in a motor rotating speed digital signal mode.
further, the synchronous clock signals are divided into 10, and the extra synchronous clock signals can be used for debugging.
further, the motor in the FSO device operates as follows:
(1) The beacon light detector does not detect the beacon light, the signal light detector does not detect the signal light, and the motor restores the plane mirror to the initial state.
(2) The beacon light detector detects beacon light, the signal light detector does not detect signal light, and the motor coarsely adjusts the plane mirror.
(3) The beacon light is detected by the beacon light detector, the signal amplitude difference of the signal light detected by the signal light detector is large, and the motor is used for roughly adjusting the plane mirror.
(4) The beacon light is detected by the beacon light detector, the signal amplitude difference of the signal light detected by the signal light detector is not large, and the motor finely adjusts the plane mirror.
(5) the beacon light detector does not detect the beacon light, the signal light detector detects the signal light, and the motor finely adjusts the plane mirror.
By adopting the scheme, the invention provides a control system for automatically tracking a motor in FSO equipment and a signal processing method thereof, a signal light signal and a beacon light signal obtained by a signal light detector and a beacon light detector are amplified in a high-gain MMIC, converted in a high-precision high-speed 2-path A/D converter and analyzed and compared in an FPGA to obtain a motor rotating speed digital signal and a motor direction control signal required by the motor, the motor rotating speed digital signal is converted into a motor rotating speed analog signal through the D/A converter, and a motor driver regulates the motor according to the motor direction control signal and the motor rotating speed analog signal to ensure the normal communication of the FSO equipment.
Drawings
FIG. 1 is a functional block diagram of a control system of the present invention;
FIG. 2 is a functional block diagram of an FPGA of the present invention;
FIG. 3 is a clock management module in the FPGA of the present invention;
FIG. 4 is a signal light fine tuning signal processing module in the FPGA of the present invention;
FIG. 5 is a schematic diagram of a beacon light coarse tuning signal processing module in an FPGA of the present invention;
FIG. 6 is a motor control processing module in the FPGA of the present invention;
FIG. 7 is a flow chart of a method of the present invention;
FIG. 8 is a flow chart of a control algorithm of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and the specific embodiments.
Referring to fig. 1, fig. 2, fig. 3, fig. 4, fig. 5 and fig. 6, the control system for automatically tracking the motor in the FSO device according to the present invention includes: the system comprises a signal light detector 10, a beacon light detector 11, a first A/D converter connected with the signal light detector 10, a second A/D converter connected with the beacon light detector 11, an FPGA100 connected with the first A/D converter and the second A/D converter, a D/A converter 19 connected with the FPGA100, a motor driver 20 connected with the D/A converter 19, and a clock driver 13 connected with the first A/D converter, the second A/D converter and the FPGA100 respectively; the motor driver 20 is connected with the FPGA 100; the FPGA100 includes: a clock management module 110, a beacon light coarse tuning processing module 130 and a signal light fine tuning processing module 120 respectively connected to the clock management module 110, and a motor control processing module 140 respectively connected to the beacon light coarse tuning processing module 130 and the signal light fine tuning processing module 120; the clock management module 110 is connected to the clock driver 13, the signal light fine adjustment processing module 120 is connected to the first a/D converter, the beacon light coarse adjustment processing module 130 is connected to the second a/D converter, the motor control processing module 140 is connected to the D/a converter 19 and the motor driver 20, and the motor driver 20 is connected to the motor 21. The signal light detector 10 is configured to detect signal light and convert the light signal into an analog signal, the beacon light detector 11 is configured to detect beacon light and convert the light signal into an analog signal, the first a/D converter and the second a/D converter are configured to convert the analog signal into a digital signal, the FPGA100 is configured to process the digital signal transmitted by the first a/D converter and the second a/D converter and output a direction control signal of a motor and a motor rotation speed digital signal, the D/a converter 19 is configured to convert the motor rotation speed digital signal output by the FPGA100 into a motor rotation speed analog signal, and the motor driver 20 is configured to drive the motor 21. The clock driver 13 is used to provide synchronous clock signals to the first a/D converter, the second a/D converter and the FPGA 100.
The control system for automatically tracking the motor in the FSO equipment further comprises: a plurality of high-gain MMICs 12 disposed between the signal light detector 10 and the first a/D converter, and between the beacon light detector 11 and the second a/D converter, a position sensor and circuitry 18 connected to the FPGA100, respectively; the first a/D converter is connected to the signal light detector 10 through a high-gain MMIC12, the second a/D converter is connected to the beacon light detector 11 through a high-gain MMIC12, and the position sensor is provided on the motor 21. The high-gain MMIC12 is used to amplify the analog signals obtained by the signal light detector 10 and the beacon light detector 11. The position sensor is used to detect whether the motor 21 is in the zero position. The circuitry is to provide an initial reset signal.
the signal light detector 10 and the beacon light detector 11 are four-quadrant photodetectors, and the first a/D converter includes: a first high-precision high-speed 2-way A/D converter 14 and a second high-precision high-speed 2-way A/D converter 15, wherein the second A/D converter comprises a third high-precision high-speed 2-way A/D converter 16 and a fourth high-precision high-speed 2-way A/D converter 17, the first high-precision high-speed 2-way A/D converter 14 and the second high-precision high-speed 2-way A/D converter 15 correspond to four quadrant signals of the signal light detector 10, the third high-precision high-speed 2-way A/D converter 16 and the fourth high-precision high-speed 2-way A/D converter 17 correspond to four quadrant signals of the beacon light detector 11, the D/A converter 19 is a high-precision high-speed D/A converter, and the clock driver 13 is a 1:5 clock driver. The clock driver 13 is used for providing synchronous clocks for five modules, namely a first high-precision high-speed 2-way A/D converter 14, a second high-precision high-speed 2-way A/D converter 15, a third high-precision high-speed 2-way A/D converter 16, a fourth high-precision high-speed 2-way A/D converter 17 and the FPGA 100.
The signal light fine-tuning signal processing module 120 includes: a first 4-way 10-bit comparator 121, a fine-tuned 1 st data sample 122, a fine-tuned 2 nd data sample 123, a fine-tuned 3 rd data sample 124 and a fine-tuned 4 th data sample 125 respectively connected to the first 4-way 10-bit comparator 121; the fine-tuning 1 st data sample 122 and the fine-tuning 2 nd data sample 123 are respectively connected with the clock management module 110 and the first high-precision high-speed 2-way a/D converter 14, the fine-tuning 3 rd data sample 124 and the fine-tuning 4 th data sample 125 are respectively connected with the clock management module 110 and the second high-precision high-speed 2-way a/D converter 15, and the first 4-way 10-bit comparator 121 is connected with the motor control processing module 140; the beacon light coarse tuning processing module 130 includes: a second 4-way 10-bit comparator 131, coarse-tuning 1 st data sample 132, coarse-tuning 2 nd data sample 133, coarse-tuning 3 rd data sample 134 and coarse-tuning 4 th data sample 135 respectively connected to the second 4-way 10-bit comparator 131; the 1 st rough data sampling 132 and the 2 nd rough data sampling 133 are respectively connected with the clock management module 110 and the third high-precision high-speed 2-way a/D converter 16, the 3 rd rough data sampling 134 and the 4 th rough data sampling 135 are respectively connected with the clock management module 110 and the fourth high-precision high-speed 2-way a/D converter 17, and the 4 th 4-way 10-bit comparator 131 is connected with the motor control processing module 140; the motor control processing module 140 includes: the control module 141 is respectively connected with the first 4-channel 10-bit comparator 121, the second 4-channel 10-bit comparator 131, the motor driver 20 and the clock management module 110, the RAM module 142 is respectively connected with the clock management module 110 and the D/a converter 19, the RAM module 142 stores motor rotating speed digital information of the control motor 21 under different conditions, and the RAM module 142 writes the regulated motor rotating speed digital information corresponding to different motor rotating speed digital information according to different addresses. The motor speed digital information in the RAM module 142 is provided in advance by the circuitry of the FSO system.
in this embodiment, the signal light detector 10 is QP20-6TO, and is a small area QPD of 5mm × 5mm, the beacon light detector 11 is QP100-6SMD, and is a large area QPD of 10mm × 10mm, and the clock driver 13 is 100mhz ttl 1:5 clock driver P2I2305NZG, the first A/D converter and the second A/D converter are both AD9218, the FPGA100 is XC2C256-TQG144, and the D/A converter 19 is AD 9754.
In this embodiment, the high-gain MMIC12 is INA-02186.
Referring to fig. 7, the present invention further provides a signal processing method, including the following steps:
S1: the signal light detector 10 and the beacon light detector 11 detect the signal light and the beacon light, respectively, and obtain a signal light analog signal and a beacon light analog signal, respectively, and transmit the obtained signal light analog signal and beacon light analog signal to the first a/D converter and the second a/D converter, respectively.
s2: the first a/D converter and the second a/D converter respectively a/D-convert the obtained signal light analog signal and the beacon light analog signal under the synchronous clock of the clock driver 13; and transmits the converted signal light digital signal and beacon light digital signal to the FPGA 100.
S3: the FPGA100 analyzes and processes the signal light digital signal and the beacon light digital signal under the synchronous clock of the clock driver 13 to obtain a motor speed digital signal and a motor direction control signal, and transmits the motor speed digital signal and the motor direction control signal to the D/a converter 19 and the motor driver 20, respectively.
s4: the D/a converter 19D/a-converts the obtained motor rotational speed digital signal at the synchronous clock of the clock driver 13, and transmits the converted motor rotational speed analog signal to the motor driver 20.
S5: the motor driver 20 combines the obtained motor rotational speed analog signal and the motor direction control signal to control the motor 21.
The signal processing method further includes, in step S1, amplifying the obtained signal optical analog signal and the beacon optical analog signal by the high-gain MMIC12, and, in step S2, transmitting an auxiliary signal to the FPGA100, the auxiliary signal including: the initial reset signal is used for indicating the system to initialize, and comprises the initialization of CPU operation in the system, the initialization of logic relation in the FPGA100, the reset generated by an internal control time sequence signal in the FPGA100, and the writing of the motor rotating speed digital information for controlling the motor to rotate into the RAM module 142.
In step S3, the clock management module 100 receives the synchronous clock signal from the clock driver 13 and divides the synchronous clock signal into at least nine, the fine-tuned 1 st data sample 122 and the fine-tuned 2 nd data sample 123 respectively receive the digital signal converted by the first high-precision high-speed 2-way a/D converter 14 and a synchronous clock signal distributed by the clock management module 110, the fine-tuned 3 rd data sample 124 and the fine-tuned 4 th data sample 125 respectively receive the digital signal converted by the second high-precision high-speed 2-way a/D converter 15 and a synchronous clock signal distributed by the clock management module 110, the fine-tuned 1 st data sample 122, the fine-tuned 2 nd data sample 123, the fine-tuned 3 rd data sample 124 and the fine-tuned 4 th data sample 125 respectively sample and transmit the sampled digital signals to the first 4-way 10-bit comparator 121, the first 4-way 10-bit comparator 121 compares and analyzes the four groups of sampled digital signals to obtain first control coded signals J2-J0, and outputs the first control coded signals J2-J0 to the motor control processing module 140; the coarse-tuning 1 st data sample 132 and the coarse-tuning 2 nd data sample 133 respectively receive the digital signal converted by the third high-precision high-speed 2-way a/D converter 16 and a synchronous clock signal distributed by the clock management module 110, the coarse-tuning 3 rd data sample 134 and the coarse-tuning 4 th data sample 135 respectively receive the digital signal converted by the fourth high-precision high-speed 2-way a/D converter 17 and a synchronous clock signal distributed by the clock management module 110, the coarse-tuning 1 st data sample 132, the coarse-tuning 2 nd data sample 133, the coarse-tuning 3 rd data sample 134 and the coarse-tuning 4 th data sample 135 respectively sample and transmit the sampled digital signals to the second 4-way 10 comparator 131, the second 4-way 10 comparator 131 compares and analyzes the four groups of sampled digital signals to obtain second control coding signals C2-C0, and outputs the second control code signal C2-C0 to the motor control processing module 140; the control module 141 receives and analyzes the first control code signal J2-J0, the second control code signal C2-C0, a synchronous clock signal and an auxiliary signal to obtain a RAM read address signal and a motor direction control signal, the control module 141 sends the RAM read address signal and the motor direction control signal to the RAM module 142 and the motor driver 20 respectively, the control module 141 reads out motor rotation speed digital information corresponding to the address signal in the RAM module 142 under the synchronous clock to obtain motor rotation speed digital information corresponding to the RAM read address signal, and the RAM module 142 outputs the motor rotation speed digital information to the high-resolution high-speed D/a converter 19 in a motor rotation speed digital signal mode.
in this embodiment, the synchronous clock signals are divided into 10, and the extra synchronous clock signals can be used for debugging.
Referring to fig. 8, the operation of the motor in the FSO device is as follows:
(1) The beacon light is not detected by the beacon light detector 11, the signal light is not detected by the signal light detector 10, and the motor returns the plane mirror to the initial state.
(2) the beacon light is detected by the beacon light detector 11 and no signal light is detected by the signal light detector 10, and the motor coarsely adjusts the plane mirror.
(3) The beacon light is detected by the beacon light detector 11, the signal amplitude of the signal light detected by the signal light detector 10 is greatly different, and the motor is used for roughly adjusting the plane mirror.
(4) The beacon light is detected by the beacon light detector 11, the signal amplitude of the signal light detected by the signal light detector 10 is not greatly different, and the motor finely adjusts the plane mirror.
(5) The beacon light is not detected by the beacon light detector 11, the signal light is detected by the signal light detector 10, and the motor finely adjusts the plane mirror.
in this embodiment, '000' of the control coded signals C2-C0 of the second 4-way 10-bit comparator indicates that no beacon light is received, '111' indicates that beacon light is received and the signal amplitude of each quadrant is not much different, '101' indicates that beacon light is received but the signal amplitude is much different. The control coded signals J2-J0 of the first 4-way 10-bit comparator indicate that no signal light is received, '111' indicates that signal light is received and the signal amplitude of each quadrant is not much different, '101' indicates that signal light is received but the signal amplitude is much different. According to the algorithm flow chart, when the value of C2-C0 is not '000', if the value of J2-J0 is '111', the system is finely adjusted; if the values of J2-J0 are '000' or '101', the system performs a coarse adjustment. When the value of C2-C0 is '000', if the value of J2-J0 is '000', the motor rapidly rotates the plane mirror to the initial position; if the values of J2-J0 are '101' or '111', the system is fine-tuned. The codes of C2-C0 and J2-J0 in the system are determined according to the actual control needs of the system and are not limited to the above three types.
The beacon light coarse tuning processing module 130 compares the signal intensity of each quadrant of the beacon light detector 11, and outputs 3-bit control encoding signals C2-C0 according to the comparison result, wherein different encoding meanings are different. The signal light fine-tuning processing module 120 compares the signal intensity of each quadrant of the signal light detector 10, and outputs 3-bit control coded signals J2-J0 according to the comparison result, wherein different numbering meanings are different. The motor control processing module 140 controls the rotation direction and the rotation speed of the motor 21 according to the output codes of the beacon light coarse adjustment processing module 130 and the signal light fine adjustment processing module 120. The rotation speed of the motor 21 is determined by the magnitude of the current, which is determined by the magnitude of the motor rotation speed analog signal output from the 14-bit D/a converter 19, the motor driver 20 further linearly amplifies the motor rotation speed analog signal to drive the motor 21, and the D/a converter 19 receives the motor rotation speed digital signal from the RAM block 142, so that the magnitude of the current is determined by the output from the RAM block 142. The RAM block 142 is 32 16-bit memory cells, and since the D/a converter 19 is 14 bits, the upper 2 bits of the RAM block 142 remain unchanged. When the system is powered on and initialized, the RAM module 142 writes the adjusted and measured rotating speed value according to the address, and different addresses correspond to different rotating speeds. After initialization, the system starts to work, when adjustment is needed, the rotating speed of the motor 21 is controlled according to the adjustment condition, the digital signal of the rotating speed of the motor is read out from the corresponding address, and the digital signal drives the motor to rotate after D/A conversion and motor driving. The rotation direction of the motor 21 is controlled by a control signal output by the FPGA100, and the FPGA100 simultaneously receives a motor rotation zero position indication signal sent by the motor 21 to instruct the FPGA100 to stop the motor rotation driving. The address signal and the read/write control signal of the RAM block 142 are generated by the control block 141 according to the synchronous clock.
In summary, the invention provides a control system for automatically tracking a motor in an FSO device and a signal processing method thereof, wherein a signal light signal and a beacon light signal obtained by a signal light detector and a beacon light detector are amplified in a high-gain MMIC, converted in a high-precision high-speed 2-way a/D converter and analyzed and compared in an FPGA to obtain a motor speed digital signal and a motor direction control signal required by the motor, the motor speed digital signal is converted into a motor speed analog signal through a D/a converter, and the motor driver adjusts the motor according to the motor direction control signal and the motor speed analog signal to ensure normal communication of the FSO device.
the present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A control system for automatically tracking a motor in an FSO device, comprising: the system comprises a signal light detector, a beacon light detector, a first A/D converter connected with the signal light detector, a second A/D converter connected with the beacon light detector, an FPGA connected with the first A/D converter and the second A/D converter, a D/A converter connected with the FPGA, a motor driver connected with the D/A converter, and a clock driver respectively connected with the first A/D converter, the second A/D converter and the FPGA; the motor driver is connected with the FPGA; the FPGA comprises: the device comprises a clock management module, a beacon light coarse adjustment processing module, a signal light fine adjustment processing module and a motor control processing module, wherein the beacon light coarse adjustment processing module and the signal light fine adjustment processing module are respectively connected with the clock management module; the clock management module is connected with the clock driver, the signal light fine adjustment processing module is connected with the first A/D converter, the beacon light coarse adjustment processing module is connected with the second A/D converter, the motor control processing module is respectively connected with the D/A converter and the motor driver, and the motor driver is connected with the motor; the signal light fine-tuning signal processing module comprises: the first 4 paths of 10 bit comparators are respectively connected with the first 4 paths of 10 bit comparators and used for fine-tuning the 1 st path of data sampling, fine-tuning the 2 nd path of data sampling, fine-tuning the 3 rd path of data sampling and fine-tuning the 4 th path of data sampling; the fine-tuning 1 st data sampling and the fine-tuning 2 nd data sampling are respectively connected with a clock management module and a first high-precision high-speed 2-way A/D converter, the fine-tuning 3 rd data sampling and the fine-tuning 4 th data sampling are respectively connected with the clock management module and a second high-precision high-speed 2-way A/D converter, and the first 4-way 10-bit comparator is connected with the motor control processing module; the beacon light coarse adjustment processing module comprises: the second 4 paths of 10 bit comparators are respectively connected with the second 4 paths of 10 bit comparators and used for roughly adjusting the 1 st path of data sampling, roughly adjusting the 2 nd path of data sampling, roughly adjusting the 3 rd path of data sampling and roughly adjusting the 4 th path of data sampling; the 1 st data sampling and the 2 nd data sampling are respectively connected with a clock management module and a third high-precision high-speed 2-way A/D converter, the 3 rd data sampling and the 4 th data sampling are respectively connected with the clock management module and a fourth high-precision high-speed 2-way A/D converter, and the 4 th 10-way bit comparator is connected with the motor control processing module; the motor control processing module includes: control module, with the RAM module that control module connects, control module respectively with first 4 way 10 bit comparator, 4 way 10 bit comparator of second, motor drive and clock management module are connected, the RAM module respectively with clock management module and DA converter are connected, the storage has the motor speed digital information of control motor rotational speed under the different circumstances in the RAM module, and the RAM module corresponds different motor speed digital information according to the address of difference and writes in the motor speed digital information of transferring and surveying.
2. The control system for automatically tracking a motor in an FSO device according to claim 1, further comprising: the high-gain MMICs are arranged between the signal light detector and the first A/D converter and between the beacon light detector and the second A/D converter, and the position sensor and the circuit system are respectively connected with the FPGA; the first A/D converter is connected with the signal light detector through a high-gain MMIC, the second A/D converter is connected with the beacon light detector through a high-gain MMIC, and the position sensor is arranged on the motor.
3. the control system for automatically tracking a motor in an FSO device as claimed in claim 1, wherein said signal photodetector and said beacon photodetector are each four quadrant photodetectors, and wherein said first a/D converter comprises: the first high-precision high-speed 2-path A/D converter and the second high-precision high-speed 2-path A/D converter are connected in series, the second A/D converter comprises a third high-precision high-speed 2-path A/D converter and a fourth high-precision high-speed 2-path A/D converter, the first high-precision high-speed 2-path A/D converter and the second high-precision high-speed 2-path A/D converter correspond to four quadrant signals of the signal light detector, the third high-precision high-speed 2-path A/D converter and the fourth high-precision high-speed 2-path A/D converter correspond to four quadrant signals of the beacon light detector, the D/A converter is a high-resolution high-speed D/A converter, and the clock driver is a 1:5 clock driver.
4. The control system for automatically tracking a motor in an FSO device as claimed in claim 1, wherein said signal light detector is QP20-6TO, said beacon light detector is QP100-6SMD, said clock driver is 100MHz TTL 1: the clock driver 5 can select P2I2305NZG, the first A/D converter and the second A/D converter are both AD9218, the FPGA is XC2C256-TQG144, and the D/A converter is AD 9754.
5. The control system for automatically tracking a motor in an FSO device of claim 2, wherein the high gain MMIC is INA-02186.
6. a signal processing method for automatically tracking a motor in FSO equipment is characterized by comprising the following steps:
S1: the signal light detector and the beacon light detector respectively detect the signal light and the beacon light, respectively obtain a signal light analog signal and a beacon light analog signal, and respectively transmit the obtained signal light analog signal and the obtained beacon light analog signal to the first A/D converter and the second A/D converter;
s2: the first A/D converter and the second A/D converter respectively perform A/D conversion on the obtained signal light analog signal and the obtained beacon light analog signal under the synchronous clock of the clock driver; the converted signal light digital signal and the beacon light digital signal are transmitted to the FPGA;
S3: the FPGA analyzes and processes the signal light digital signal and the beacon light digital signal under the synchronous clock of the clock driver to obtain a motor rotating speed digital signal and a motor direction control signal, and respectively transmits the motor rotating speed digital signal and the motor direction control signal to the D/A converter and the motor driver; wherein, the clock management module receives the synchronous clock signal of the clock driver and divides the synchronous clock signal into at least nine, the fine-adjustment 1 st data sampling and the fine-adjustment 2 nd data sampling respectively receive the digital signal converted by the first high-precision high-speed 2-path A/D converter and a synchronous clock signal distributed by the clock management module, the fine-adjustment 3 rd data sampling and the fine-adjustment 4 th data sampling respectively receive the digital signal converted by the second high-precision high-speed 2-path A/D converter and a synchronous clock signal distributed by the clock management module, the fine-adjustment 1 st data sampling, the fine-adjustment 2 nd data sampling, the fine-adjustment 3 rd data sampling and the fine-adjustment 4 th data sampling respectively carry out sampling and transmit the sampled digital signal to the first 4-path 10-bit comparator, the first 4-path 10-bit comparator carries out comparative analysis on the four groups of sampled digital signals, obtaining a first control coding signal and outputting the first control coding signal to a motor control processing module; the 1 st data sampling and the 2 nd data sampling are coarsely adjusted to respectively receive the digital signal converted by the third high-precision high-speed 2-path A/D converter and a synchronous clock signal distributed by the clock management module, the 3 rd data sampling and the 4 th data sampling are coarsely adjusted to respectively receive the digital signal converted by the fourth high-precision high-speed 2-path A/D converter and a synchronous clock signal distributed by the clock management module, the 1 st data sampling, the 2 nd data sampling, the 3 rd data sampling and the 4 th data sampling are sampled and sampled respectively, and sampled digital signals are transmitted to a 4 th 10-way second comparator, and the 4 th 10-way second comparator compares and analyzes the four groups of sampled digital signals to obtain a second control coding signal and outputs the second control coding signal to the motor control processing module; the control module receives and analyzes a first control coding signal, a second control coding signal, a synchronous clock signal and an auxiliary signal to obtain an address signal and a motor direction control signal, the control module respectively sends the address signal and the motor direction control signal to the RAM module and the motor driver, the control module reads out motor rotating speed digital information corresponding to the address signal in the RAM module under the synchronous clock to obtain motor rotating speed digital information corresponding to the address signal, and the RAM module outputs the motor rotating speed digital information to the high-resolution high-speed D/A converter in a motor rotating speed digital signal mode;
S4: D/A converter carries on D/A conversion in the synchronous clock of the clock driver with the digital signal of rotational speed of the motor obtained, and transmit the motor rotational speed analog signal after converting to the motor driver;
S5: the motor driver combines the obtained motor rotating speed analog signal and the motor direction control signal to control the motor.
7. The signal processing method of claim 6, further comprising amplifying the obtained signal optical analog signal and the beacon optical analog signal by a high-gain MMIC at step S1, and further comprising transmitting an auxiliary signal to the FPGA at step S2, the auxiliary signal comprising: the system comprises an indication signal and an initial reset signal which can not rotate after the motor rotates to a zero position and a maximum range, wherein the initial reset signal is used for indicating the system to initialize and comprises the initialization of the running of a CPU (central processing unit) in the system, the initialization of the logic relation in the FPGA and the reset generated by an internal control time sequence signal in the FPGA, and the motor rotating speed digital information for controlling the motor to rotate is written into an RAM (random access memory) module.
8. the signal processing method of claim 6, wherein the motor in the FSO device operates as follows:
(1) The beacon light detector does not detect beacon light, the signal light detector does not detect signal light, and the motor restores the plane mirror to the initial state;
(2) The beacon light detector detects beacon light, the signal light detector does not detect signal light, and the motor performs coarse adjustment on the plane mirror;
(3) The beacon light is detected by the beacon light detector, the signal amplitude difference of the signal light detected by the signal light detector is large, and the motor is used for roughly adjusting the plane mirror;
(4) The beacon light detector detects beacon light, the signal amplitude difference of the signal light detected by the signal light detector is not large, and the motor finely adjusts the plane mirror;
(5) the beacon light detector does not detect the beacon light, the signal light detector detects the signal light, and the motor finely adjusts the plane mirror.
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