CN108020727B - Capacitor voltage conversion circuit - Google Patents
Capacitor voltage conversion circuit Download PDFInfo
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- CN108020727B CN108020727B CN201711238298.XA CN201711238298A CN108020727B CN 108020727 B CN108020727 B CN 108020727B CN 201711238298 A CN201711238298 A CN 201711238298A CN 108020727 B CN108020727 B CN 108020727B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
- G01D5/14—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
- G01D5/24—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
Abstract
The invention provides a capacitance-voltage conversion circuit, which comprises a CPU unit, a square wave excitation signal generating circuit, a measured capacitor (C), a synchronous digital detection circuit, a time-sharing integration circuit and a low-pass RC filter circuit, wherein the square wave excitation signal generating circuit is connected with the measured capacitor (C); the CPU unit is used for generating a synchronous excitation signal and a logic control signal; the square wave excitation signal generating circuit is used for converting a reference level into a square wave excitation signal by taking the synchronous excitation signal as a trigger signal and outputting the square wave excitation signal for being applied to the tested capacitor (C) to excite the tested capacitor (C); the synchronous digital detection circuit is connected to the return end of the tested capacitor (C) and is used for detecting the return signal of the tested capacitor (C) into an integral half-wave signal by taking the synchronous excitation signal as a trigger signal; the time-sharing integration circuit is used for integrating the integrated half-wave signal in a time-sharing mode by taking the synchronous excitation signal as a trigger signal and outputting a direct-current level. The conversion circuit solves the technical problems of complex structure, limited application range, larger error and low detection sensitivity of the capacitance-voltage conversion circuit.
Description
Technical Field
The invention relates to the technical field of capacitance measurement. And more particularly to a capacitor-to-voltage conversion circuit.
Background
At present, the capacitive sensor is widely used due to the advantages of simple structure, good dynamic response, high sensitivity, capability of working in severe environment and the like. The basic principle of capacitive sensors is to reflect changes in the physical quantity of the measured object by measuring changes in capacitance. The capacitance of the capacitance sensor is usually small, and the measurement method mainly comprises the steps of converting the capacitance into corresponding voltage, and then carrying out digital conversion on a voltage signal in an analog-to-digital conversion mode and then carrying out acquisition and analysis. In the current capacitance-to-voltage conversion method: the LRC bridge measuring method has a complex structure, requires more hardware resources, is high in cost, and has poor anti-interference capability due to the fact that the measuring result is greatly influenced by the capacitance performance of a bridge arm; the oscillation excitation measuring method has high requirements on the accuracy of the amplitude and the frequency of an excitation signal, the measuring application range is limited, and the accuracy cannot reach the resolution of a tiny 0.1PF level. In order to obtain a stable direct current voltage signal, an alternating current excitation voltage source is usually adopted to excite the capacitance signal in engineering application, a diode loop is arranged at the return end of the capacitance signal to carry out detection, and then a filter circuit is used for realizing stable output of voltage.
Therefore, the capacitance-voltage conversion method in the prior art has the technical problems of complex structure, limited application range, weak anti-interference capability, larger error and low detection sensitivity, especially when measuring a small capacitance value capacitor.
Disclosure of Invention
The capacitance-voltage conversion method aims to solve the technical problems of complex structure, limited application range, larger error and low detection sensitivity in the prior art, particularly when a small-capacitance is measured. The invention provides a capacitance-voltage conversion circuit.
The capacitance-voltage conversion circuit comprises a CPU unit, a square wave excitation signal generation circuit and a measured capacitor, and is characterized in that: the circuit also comprises a synchronous digital detection circuit, a time-sharing integration circuit and a low-pass RC filter circuit; the CPU unit is used for generating a synchronous excitation signal and a logic control signal, wherein the synchronous excitation signal is a logic digital signal with '0' level and '1' level alternating according to a fixed period; the square wave excitation signal generating circuit is used for converting a reference level into a square wave excitation signal by taking the synchronous excitation signal as a trigger signal and outputting the square wave excitation signal; the square wave excitation signal is an analog signal with driving capability and is applied to the tested capacitor to excite the tested capacitor; the synchronous digital detection circuit is connected to the return end of the capacitor to be detected and is used for detecting the return signal of the capacitor to be detected into an integral half-wave signal by taking the synchronous excitation signal as a trigger signal; the time-sharing integration circuit is used for performing time-sharing integration on the integrated half-wave signal by taking the synchronous excitation signal as a trigger signal and outputting a direct current level; the low-pass RC filter circuit is used for performing low-pass filtering on the direct current level.
Furthermore, the capacitance-voltage conversion circuit also comprises a level switching control circuit, wherein the level switching control circuit is used for being controlled by a logic control signal output by the CPU unit; the square wave excitation signal generating circuit is provided with a reference level of 5V or 10V.
Further, the capacitance-voltage conversion circuit further comprises an amplification following circuit, and the amplification following circuit is used for amplifying the direct-current level after passing through the low-pass RC filter circuit.
Further, the frequency of the synchronous excitation signal is 10.3 KHz.
Further, the level switching control circuit comprises a two-stage operational amplifier circuit and a digital switching switch circuit, the two-stage operational amplifier circuit comprises a first operational amplifier and a second operational amplifier, and positive power supply ends and negative power supply ends of the first operational amplifier and the second operational amplifier are respectively connected with a positive end and a negative end of a 15V power supply after passing through a current-limiting filter circuit; the positive input end of the first operational amplifier is connected with a 5V power supply, and the output end and the negative input end are connected through a first resistor and a first capacitor which are connected in series; the output end of the first operational amplifier is also connected with the positive input end of a second operational amplifier, and the negative input end of the second operational amplifier is connected with the output end of the second operational amplifier; a blocking current limiting circuit consisting of a second resistor and a third resistor is connected in parallel between the output end of the first operational amplifier and the output end of the second operational amplifier, and the output end of the second operational amplifier is connected with the reverse input end of the first amplifier after passing through a fourth resistor; the digital change-over switch circuit comprises a unidirectional digital switch, a fifth resistor, a sixth resistor, a second capacitor and a third capacitor, wherein the control end of the unidirectional digital switch is connected with a logic control signal output by the CPU unit and is connected with a 5V power supply through the sixth resistor; the input end of the unidirectional digital switch is connected with the reverse input end of the first operational amplifier, and the output end of the unidirectional digital switch is grounded after passing through a fifth resistor; the second capacitor and the third capacitor are connected in parallel between the fourth resistor and the fifth resistor, and the output end of the second operational amplifier generates a reference level required by the square wave excitation signal circuit. In the circuit described above: when the control logic of the CPU unit is '0', the unidirectional digital switch is switched off, the first operational amplifier and the second operational amplifier form a 1 to 1 follower, namely, the 5V level of the positive input end of the first operational amplifier is transmitted to the output end of the second operational amplifier to be output as a 5V reference level for the square wave excitation signal generating circuit to use; when the control logic of the CPU unit is '1', the one-way digital switch is closed, one end of the fifth resistor is grounded, the other end of the fifth resistor is connected with the fourth resistor, when the fourth resistor is equal to the fifth resistor, the first operational amplifier and the second operational amplifier form an amplifying circuit with the ratio of 2 to 1, and the output end of the second operational amplifier outputs a 10V reference level for the square wave excitation signal generating circuit to use. Namely, the purpose of providing a 5V or 10V reference level for the square wave excitation signal generation circuit is realized.
Further, the square wave excitation signal generation circuit comprises a first multi-channel digital switch module, a first transistor, a second transistor, a variable resistor and a fourth capacitor; the first multi-path digital switch module comprises a first digital switch and a second digital switch, the control ends of the first digital switch and the second digital switch are connected with a synchronous excitation signal, the input end of the first digital switch is grounded, the input end of the second digital switch is connected with a reference level, and the first digital switch and the second digital switch are always in an on-off state; the variable resistor is connected in parallel between the first digital switch and the second digital switch. The grid electrode of the first transistor is connected with a reference level, the source electrode of the first transistor is connected with the output end of the first digital switch through a resistor, the grid electrode of the second transistor is grounded, the source electrode of the second transistor is connected with the second digital switch through a resistor, the first transistor is a low gating CMOS, the second transistor is a high gating CMOS, the first transistor is connected with the common end of the second transistor and is connected with the capacitor to be tested after passing through a fourth capacitor, and the output of the fourth capacitor end is a square wave excitation signal. In the circuit described above: the input of the second digital switch is a reference level, the synchronous excitation signal controls the second digital switch to periodically switch on the reference level and the grid of the second transistor, the output ends of the first digital switch and the second digital switch are respectively and alternately switched and connected to the source stages of the first transistor and the second transistor, and the gating logic controls the first transistor and the second transistor to alternately output frequency signals at the common end of the first transistor and the second transistor, namely square waves are formed at the common end of the first transistor and the second transistor. Because the circuit is completely controlled and conducted through the first transistor and the second transistor, certain requirements on the time sequence are met: namely, when the first transistor is gated, the second transistor is turned off in advance; when the second transistor is gated, the first transistor is turned off in advance. Thus the selection is ensured by the circuit consisting of a first transistor, which selects the low gate transistor, and a second transistor, which selects the high gate. The first transistor and the second transistor select low leakage, which can reduce the peak of the output signal when changing, and the variable resistance connected in parallel between the switching lines in a bridging way is used to make the level of the first transistor and the second transistor change alternately, and can control the time sequence of the input level, so that the high level of the second transistor arrives later than the first transistor, and the low level of the first transistor arrives earlier than the second transistor, which ensures the stability and undistortion of the frequency signal output by the common end of the first transistor and the second transistor. Finally, a reference level is converted into a square wave excitation signal to be output by taking the synchronous excitation signal as a trigger signal.
Further, the synchronous digital detection circuit comprises a second multi-path digital switch module, a fifth capacitor and a seventh resistor, the second multi-path digital switch module comprises a third digital switch and a fourth digital switch, and the third digital switch and the fourth digital switch are always in an on-off state; the third digital switch is connected with the input end of the fourth digital switch, and is connected with a fourth capacitor of the square wave excitation signal generating circuit after passing through a tested capacitor and a current limiting resistor which are connected in series; the control ends of the third digital switch and the fourth digital switch are both connected with a synchronous excitation signal; the output end of the fourth digital switch is grounded, and the output end of the third digital switch is connected with the seventh resistor and is connected with a grounded filter capacitor in parallel; the fifth capacitor is connected with the input ends of the third digital switch and the fourth digital switch; and the fifth capacitor and the seventh resistor are used for forming a loop with the time-sharing integration circuit. At this time, the fifth capacitor is an integrating capacitor, and the output of the fifth capacitor is an integrated half-wave signal after detection. In the circuit described above: an excitation source signal acts on a tested capacitor through a current-limiting resistor, the return end of the tested capacitor enters the input ends of a third digital switch and a fourth digital switch, the output ends of the third digital switch and the fourth digital switch are connected and disconnected with a loop of a fifth capacitor, a seventh resistor and a time-sharing integration circuit according to the control logic of a synchronous excitation signal, integral conversion is carried out on a square wave half-wave equivalent to '1' according to the control logic of the synchronous excitation signal, a '0' square wave half-wave return signal is grounded, and therefore the purpose that the return signal of the tested capacitor C is detected into an integral half-wave signal by taking the synchronous excitation signal as a trigger signal is achieved.
Furthermore, the time-sharing integration circuit comprises a first-stage operational following amplification circuit and an integration time-sharing control circuit, the first-stage operational following amplification circuit comprises a third operational amplifier and a fourth operational amplifier, the negative input end of the third operational amplifier is connected with a fifth capacitor in the synchronous digital detection circuit, and the negative input end and the output end of the third operational amplifier are connected with a resistor and a capacitor which are connected in parallel to form a low-pass RC filter circuit; the negative input end of the fourth operational amplifier is connected with the output end of the third operational amplifier through a resistor, and the output end of the fourth operational amplifier is connected with the negative input end of the third operational amplifier through a resistor to form a following amplifying circuit; the integration time-sharing control circuit comprises a third multi-path digital switch module, a sixth capacitor and an eighth resistor; the third multi-path digital switch module comprises a fifth digital switch, a sixth digital switch and a seventh digital switch; the control ends of the fifth digital switch, the sixth digital switch and the seventh digital switch are all connected with synchronous excitation signals; the fifth digital switch and the seventh digital switch are always in the same opening and closing state, and the fifth digital switch and the sixth digital switch are always in the opening and closing state; the input ends of the fifth digital switch, the sixth digital switch and the seventh digital switch are all connected with the output end of the fourth operational amplifier; the output end of the fifth digital switch is connected with the low-pass RC filter circuit and used for outputting the integrated direct-current level; the output end of the sixth digital switch is grounded; and the output end of the seventh digital switch is connected with a sixth capacitor and an eighth resistor in series and then is connected with a seventh resistor in the synchronous digital detection circuit to form an integral loop. In the circuit described above: the integral half-wave signal transmitted by the synchronous digital detection circuit enters a time-sharing integral circuit to realize a band-pass filtering function, so that a high-frequency interference signal does not enter an integral loop to carry out operation; meanwhile, the first-stage integral operation following amplifying circuit generates stable voltage after integral, and higher driving capability is provided. The synchronous excitation signal is also used for controlling the switching functions of the fifth digital switch, the sixth digital switch and the seventh digital switch, and the sixth capacitor and the eighth resistor are connected into the integration loop in a time-sharing mode to perform integration operation of effective excitation waveforms. The synchronous excitation signal is used as a trigger signal to integrate the integrated half-wave signal in a time-sharing manner and output a direct current level. I.e. the conversion of the capacitance to voltage is completed.
Further, the low-pass RC filter circuit comprises a lightning protection diode, a TVS (transient voltage suppressor) tube, a seventh capacitor and a ninth resistor; the input end of the ninth resistor is connected with the output end of a fifth digital switch of the time-sharing integrating circuit, and the output end of the ninth resistor is connected with a grounded seventh capacitor and an amplification following circuit; and the lightning protection diode and the TVS tube are connected to form a parallel loop, and the parallel loop is connected to the ninth resistor in parallel. In the circuit described above: and the ninth resistor and the seventh capacitor form an interface protection circuit for ensuring that the high-frequency voltage can be quickly conducted to the ground wire in time under the condition of abnormal high-frequency voltage input. Low-pass filtering of the dc level is achieved.
Further, the amplification follower circuit comprises a fifth operational amplifier, a tenth resistor, an eleventh resistor and a twelfth resistor; the positive input end of the fifth operational amplifier is connected with the ninth resistor of the low-pass RC filter circuit, and the negative input end of the fifth operational amplifier is connected with the output end of the low-pass RC filter circuit through the tenth resistor; the output end of the fifth operational amplifier is connected with an eleventh resistor in series and then is used as a voltage output end for outputting voltage; and the voltage output end is connected with a pull-up resistor twelfth resistor connected with a direct current power supply. In the circuit described above: the impedance of the tenth resistor and the impedance of the eleventh resistor determine the amplification coefficient of the amplification following circuit, the twelfth resistor further improves the driving capability of a rear-stage circuit through the pull-up action of the 5V direct-current power supply, and the direct-current signal distortion caused by too low impedance of a rear-stage measurement conversion circuit is prevented from influencing the measurement precision of the capacitance converted voltage. The direct current level after passing through the low-pass RC filter circuit is amplified.
The invention provides a synchronous excitation signal generated by a CPU unit in a capacitance-voltage conversion circuit, which is used as a shared synchronous control clock and is used for triggering a square wave excitation signal generating circuit, a synchronous digital detection circuit and a time-sharing integration circuit which comprise a digital switch. The CPU unit simultaneously generates a logic control signal as a selection signal to control the level switching control circuit to output a reference level of 5V or 10V; the square wave excitation signal generating circuit generates a square wave excitation signal to excite the tested capacitor based on the reference level under the control of the synchronous excitation signal; the return signal of the tested capacitor enters a synchronous digital detection circuit, a synchronous excitation signal controls a digital switch of the synchronous digital detection circuit, the return signal is detected into an integral half-wave signal through the digital switch, the return signal is controlled to be synchronously input into a later-stage time-sharing integral circuit in a time-sharing mode according to the synchronous excitation signal, an effective return waveform is integrated, an invalid half-wave signal is grounded, and meanwhile, the integrated voltage signal is transmitted to a voltage amplification following circuit through a low-pass RC filter circuit in the effective time sequence of the synchronous excitation signal so as to obtain proper voltage output and complete capacitor voltage conversion. In conclusion, the invention cancels the unidirectional conducting devices such as diodes and the like in the prior art, adopts a digital switch, and adopts fixed time base frequency as the switching frequency of the digital switch to realize half-wave digital detection, thereby reducing the error and improving the measurement sensitivity and the anti-interference capability; meanwhile, the measuring principle and the structure are relatively simple, hardware occupies less resources, frequency setting is not needed according to the sizes of different measured capacitors, the measurement of the capacitance with larger span can be realized by selecting different reference levels, and the application range is wider; meanwhile, by combining a digital circuit technology and an integrating circuit, capacitance signals of various capacitance sensors can be converted into voltage signals, capacitance values in a variation range of 5% to 100% of a reference capacitance value 10pf-2nf can be detected, and the detection sensitivity is high; meanwhile, the invention adopts a digital excitation mode, can easily control frequency output and meet different measurement requirements; meanwhile, the amplifying follower circuit is added at the voltage output end, so that the driving capability of an output voltage signal can be enhanced, different analog-digital conversion chips can be used for conversion and measurement, and higher reliable redundancy measurement and monitoring can be realized; meanwhile, the invention adopts a time-sharing integration mode, does not need to carry out bridge balance, and the multiplexing of the measurement channel is simpler, so the measurement speed is greatly improved, the multi-channel parallel measurement can be realized, the measurement response speed is improved, the channel measurement independence is enhanced, the single-point fault is reduced, and the measurement reliability is improved.
Compared with the prior art, the capacitance-voltage conversion method has the following advantages particularly when measuring small capacitance: simple structure, wide application range, small error and high detection sensitivity.
Drawings
The following describes in further detail specific embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic block diagram of a capacitor-to-voltage conversion circuit according to the present invention;
FIG. 2 is a circuit diagram of a level switch control circuit according to the present invention;
FIG. 3 is a circuit schematic of a square wave excitation signal generation circuit of the present invention;
FIG. 4 is a circuit schematic of a synchronous digital detection circuit of the present invention;
FIG. 5 is a circuit schematic of a time-division integrating circuit of the present invention;
FIG. 6 is a circuit schematic of a low pass RC filter circuit and an amplification follower circuit in accordance with the present invention;
in the figure: q1. first transistor, q2 second transistor, r variable resistor, r1 first resistor, r2 second resistor, r3 third resistor, r4 fourth resistor, R5. fifth resistor, R6. sixth resistor, R7. seventh resistor, R8. eighth resistor, R9. ninth resistor, r10 tenth resistor, r11 eleventh resistor, r12 twelfth resistor, c measured capacitor, c1 first capacitor, C2. second capacitor, C3. third capacitor, c4 fourth capacitor, C5. fifth capacitor, C6. sixth capacitor, C7. seventh capacitor, s unidirectional digital switch, s1 first digital switch, s2 second digital switch, s3 third digital switch, s4 fourth digital switch, s5 fifth digital switch, s6 sixth digital switch, s7 seventh digital switch, U1. first digital switch, s 84 second digital switch, s3 third digital switch, s4 fourth digital switch, s5 fifth digital switch, s6 sixth digital switch, s7 seventh digital switch, U1. first operational amplifier, fourth operational amplifier, 8925 operational amplifier, d 8236 operational amplifier, and operational amplifier, D2.TVS tube.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings, and it should be noted that the description of the embodiments is provided for understanding the present invention, but the present invention is not limited thereto. In addition, the technical features involved in the respective embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1:
as shown in fig. 1, the capacitance-to-voltage conversion circuit according to this embodiment includes a CPU unit, a square wave excitation signal generation circuit, and a measured capacitor C, and is characterized in that: the circuit also comprises a synchronous digital detection circuit, a time-sharing integration circuit and a low-pass RC filter circuit; the CPU unit is used for generating a synchronous excitation signal and a logic control signal, wherein the synchronous excitation signal is a logic digital signal with '0' level and '1' level alternating according to a fixed period; the square wave excitation signal generating circuit is used for converting a reference level into a square wave excitation signal to be output by taking the synchronous excitation signal as a trigger signal, and the square wave excitation signal is an analog signal with driving capability and is applied to the tested capacitor C to excite the tested capacitor C; the synchronous digital detection circuit is connected to the return end of the measured capacitor C and is used for detecting the return signal of the measured capacitor into an integral half-wave signal by taking the synchronous excitation signal as a trigger signal; the time-sharing integration circuit is used for performing time-sharing integration on the integrated half-wave signal by taking the synchronous excitation signal as a trigger signal and outputting a direct current level; the low-pass RC filter circuit is used for performing low-pass filtering on the direct current level.
Example 2:
on the basis of the above embodiment, an embodiment 2 is proposed, as shown in fig. 1, which is characterized in that: the capacitance-voltage conversion circuit further comprises a level switching control circuit; the level switching control circuit is used for being controlled by a logic control signal output by the CPU unit and providing a 5V or 10V reference level for the square wave excitation signal generating circuit.
Example 3:
on the basis of the above embodiment, an embodiment 3 is proposed, as shown in fig. 1, which is characterized in that: the capacitor voltage conversion circuit further comprises an amplification following circuit, and the amplification following circuit is used for amplifying the direct current level after passing through the low-pass RC filter circuit.
Example 4:
on the basis of the above embodiment, embodiment 4 is proposed, which is characterized in that: further, the frequency of the synchronous excitation signal is 10.3 KHz.
Example 5:
on the basis of the above embodiment, an embodiment 5 is proposed, as shown in fig. 2, which is characterized in that: the level switching control circuit comprises a two-stage operational amplifier circuit and a digital switching switch circuit, the two-stage operational amplifier circuit comprises a first operational amplifier U1 and a second operational amplifier U2, and positive power supply ends and negative power supply ends of the first operational amplifier U1 and the second operational amplifier U2 are respectively connected with a positive end and a negative end of a 15V power supply after passing through a current-limiting filter circuit; the forward input end of the first operational amplifier U1 is connected with a 5V power supply, and the output end and the reverse input end are connected through a first resistor R1 and a first capacitor C1 which are connected in series; the output end of the first operational amplifier U1 is also connected with the positive input end of a second operational amplifier U2, and the negative input end of the second operational amplifier U2 is connected with the output end thereof; a blocking and current limiting circuit composed of a second resistor R2 and a third resistor R3 is connected in parallel between the output end of the first operational amplifier U1 and the output end of the second operational amplifier U2, and the output end of the second operational amplifier U2 is connected with the reverse input end of the first amplifier U1 after passing through a fourth resistor R4; the digital change-over switch circuit comprises a unidirectional digital switch S, a fifth resistor R5, a sixth resistor R6, a second capacitor C2 and a third capacitor C3, wherein the control end of the digital switch S is connected with a logic control signal output by the CPU unit and is connected with a 5V power supply through the sixth resistor R6; the input end of the unidirectional digital switch S is connected with the reverse input end of the first operational amplifier U1, and the output end of the unidirectional digital switch S is grounded after passing through a fifth resistor R5; the second capacitor C2 and the third capacitor C3 are connected in parallel between the fourth resistor R4 and the fifth resistor R5, and the output end of the second operational amplifier U2 generates a reference level required by the square wave excitation signal circuit. In the circuit described above: when the CPU unit control logic is '0', the unidirectional digital switch S is disconnected, the first operational amplifier U1 and the second operational amplifier U2 form a 1 to 1 follower, namely, the 5V level of the positive input end of the first operational amplifier U1 is transmitted to the output end of the second operational amplifier U2 to be output as a 5V reference level for the square wave excitation signal generation circuit to use; when the CPU unit control logic is '1', the one-way digital switch S is closed, one end of the fifth resistor R5 is grounded, the other end is connected with the fourth resistor R4, when the fourth resistor R4 is equal to the fifth resistor R5, the first operational amplifier U1 and the second operational amplifier U2 form an amplifying circuit with the ratio of 2 to 1, and the output end of the second operational amplifier U2 outputs a reference level of 10V for the square wave excitation signal generation circuit to use. Namely, the purpose of providing a 5V or 10V reference level for the square wave excitation signal generation circuit is realized.
Example 6:
on the basis of the above embodiment, an embodiment 6 is proposed, as shown in fig. 3, which is characterized in that: the square wave excitation signal generating circuit comprises a first multi-path digital switch module, a first transistor Q1, a second transistor Q2, a variable resistor R and a fourth capacitor C4; the first multi-way digital switch module comprises a first digital switch S1 and a second digital switch S2, control ends of the first digital switch S1 and the second digital switch S2 are connected with a synchronous excitation signal, an input end of the first digital switch S1 is grounded, an input end of the second digital switch S2 is connected with a reference level, and the first digital switch S1 and the second digital switch S2 are always in an open-close state; the variable resistor R is connected in parallel between the first digital switch S1 and the second digital switch S2. The grid electrode of the first transistor Q1 is connected with a reference level, the source electrode is connected with the output end of the first digital switch S1 through a resistor, the grid electrode of the second transistor Q2 is grounded, the source electrode is connected with the second digital switch S2 through a resistor, the first transistor Q1 is a low-gating CMOS, the second transistor Q2 is a high-gating CMOS, the common end of the first transistor Q1 and the second transistor Q2 is connected with the measured capacitor C through a fourth capacitor C4, and the output end of the fourth capacitor C4 is a square wave excitation signal. In the circuit described above: the input of the second digital switch S2 is a reference level, the synchronous excitation signal controls the second digital switch S2 to periodically turn on the reference level and the gate of the second transistor Q2, the output terminals of the first digital switch S1 and the second digital switch 2 are alternately switched and connected to the source stages of the first transistor Q1 and the second transistor Q2, respectively, and the gating logic controls the first transistor Q1 and the second transistor Q2 to alternately output frequency signals at the common terminal thereof, namely, square waves are formed at the common terminal. Since the circuit is completely controlled and conducted by the first transistor Q1 and the second transistor Q2, there is a timing requirement: that is, when the first transistor Q1 is gated, the second transistor Q2 is turned off early; when the second transistor Q2 is gated, the first transistor Q1 is turned off early. Thus, the selection is ensured by a circuit consisting of a first transistor, which is selected to be a low-gated CMOS transistor, and a second transistor, which is selected to be a high-gated CMOS transistor. Meanwhile, the first transistor Q1 and the second transistor Q2 need to have small leakage selectively, so that the peak of the output signal during change can be reduced, and the variable resistor R connected in parallel between switching lines in a bridging manner is used for not only enabling the levels of the input first transistor Q1 and the second transistor Q2 to be alternately changed, but also controlling the time sequence of the input level, so that the high level of the input second transistor Q2 arrives later than the first transistor Q1, and the low level of the input second transistor Q1 arrives earlier than the second transistor Q2, so that the frequency signals output by the common end of the first transistor Q1 and the second transistor Q2 are stable and undistorted. Finally, a reference level is converted into a square wave excitation signal to be output by taking the synchronous excitation signal as a trigger signal.
Example 7:
on the basis of the above embodiment, an embodiment 7 is proposed, as shown in fig. 4, which is characterized in that: the synchronous digital detection circuit comprises a second multi-path digital switch module, a fifth capacitor C5 and a seventh resistor R7, the second multi-path digital switch module comprises a third digital switch S3 and a fourth digital switch S4, and the third digital switch S3 and the fourth digital switch S4 are always in an on-off state; the input ends of the third digital switch S3 and the fourth digital switch S4 are connected, and are connected with a fourth capacitor C4 of the square wave excitation signal generating circuit after passing through a tested capacitor C and a current-limiting resistor which are connected in series; the control ends of the third digital switch S3 and the fourth digital switch S4 are both connected with synchronous excitation signals; the output end of the fourth digital switch S4 is grounded, the output end of the third digital switch S3 is connected with the seventh resistor R7, and a grounded filter capacitor is connected in parallel; the fifth capacitor C5 is connected with the input ends of the third digital switch S3 and the fourth digital switch S4; the fifth capacitor C5 and the seventh resistor R7 are used for forming a loop with the time-sharing integration circuit. At this time, the fifth capacitor C5 is an integrating capacitor, and the output of the integrating capacitor is the integrated half-wave signal after detection. In the circuit described above: an excitation source signal is applied to a tested capacitor C through a current-limiting resistor, the return end of the tested capacitor C enters the input ends of a third digital switch S3 and a fourth digital switch S4, the output ends of the third digital switch S3 and the fourth digital switch S4 are connected with and disconnected with a loop of a fifth capacitor C5, a seventh resistor R7 and a time-sharing integration circuit according to the control logic of a synchronous excitation signal, integral conversion is carried out on a square wave half-wave equivalent to '1' according to the control logic of the synchronous excitation signal, and a '0' square wave half-wave return signal is grounded, namely, the return signal of the tested capacitor C is detected into an integral half-wave signal by taking the synchronous excitation signal as a trigger signal.
Example 8:
on the basis of the above embodiment, an embodiment 8 is proposed, as shown in fig. 5, which is characterized in that: the time-sharing integration circuit comprises a first-stage operational following amplification circuit and an integration time-sharing control circuit, the first-stage operational following amplification circuit comprises a third operational amplifier U3 and a fourth operational amplifier U4, the negative input end of the third operational amplifier U3 is connected with a fifth capacitor C5 in the synchronous digital detection circuit, and a resistor and a capacitor which are connected in parallel are connected with the negative input end and the output end of the third operational amplifier U3 to form a low-pass RC filter circuit; the negative input end of the fourth operational amplifier U4 is connected with the output end of the third operational amplifier U3 through a resistor, and the output end of the fourth operational amplifier U4 is connected with the negative input end of the third operational amplifier U3 through a resistor to form a following amplifying circuit; the integration time-sharing control circuit comprises a third multi-path digital switch module, a sixth capacitor C6 and an eighth resistor R8; the third multi-way digital switch module comprises a fifth digital switch S5, a sixth digital switch S6, a seventh digital switch S7; the control ends of the fifth digital switch S5, the sixth digital switch S6 and the seventh digital switch S7 are all connected with synchronous excitation signals; the fifth digital switch S5 and the seventh digital switch S7 are always in the same opening and closing state, and the sixth digital switch S6 is always in the opening and closing state; the input ends of the fifth digital switch S5, the sixth digital switch S6 and the seventh digital switch S7 are all connected with the output end of a fourth operational amplifier U4; the output end of the fifth digital switch S5 is connected with a low-pass RC filter circuit and used for outputting an integrated direct current level; the output terminal of the sixth digital switch S6 is grounded; the output end of the seventh digital switch S7 is connected in series with a sixth capacitor C6 and an eighth resistor R8 and then is connected with a seventh resistor R7 in the synchronous digital detector circuit to form an integral loop. In the circuit described above: the integral half-wave signal transmitted by the synchronous digital detection circuit enters a time-sharing integral circuit to realize a band-pass filtering function, so that a high-frequency interference signal does not enter an integral loop to carry out operation; meanwhile, the first-stage integral operation following amplifying circuit generates stable voltage after integral, and higher driving capability is provided. The synchronous excitation signal is also used for controlling the switching functions of the fifth digital switch S5, the sixth digital switch S6 and the seventh digital switch S7, and the sixth capacitor C6 and the eighth resistor R8 are connected into the integration loop in a time-sharing mode to perform the integration operation of the effective excitation waveform. The synchronous excitation signal is used as a trigger signal to integrate the integrated half-wave signal in a time-sharing manner and output a direct current level.
Example 9:
on the basis of the above embodiment, an embodiment 9 is proposed, as shown in fig. 6, which is characterized in that: the low-pass RC filter circuit comprises a lightning protection diode D1, a TVS tube D2, a seventh capacitor C7 and a ninth resistor R9; the input end of the ninth resistor R9 is connected with the output end of a fifth digital switch S5 of the time-sharing integrating circuit, and the output end of the ninth resistor R9 is connected with a seventh grounded capacitor C7 and an amplification following circuit; the lightning protection diode D1 and the TVS tube D2 are connected to form a parallel loop, and the parallel loop is connected in parallel to the ninth resistor R9. In the circuit described above: the ninth resistor R9 and the seventh capacitor C7 form an interface protection circuit, so as to ensure that the high-frequency voltage can be quickly conducted to the ground line in time under the condition of abnormal high-frequency voltage input. Low-pass filtering of the dc level is achieved.
Example 10:
on the basis of the above embodiment, an embodiment 10 is proposed, as shown in fig. 6, which is characterized in that: the amplification follower circuit comprises a fifth operational amplifier U5, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12; the positive input end of the fifth operational amplifier U5 is connected with the ninth resistor R9 of the low-pass RC filter circuit, and the negative input end is connected with the output end of the low-pass RC filter circuit through the tenth resistor R10; the output end of the fifth operational amplifier U5 is connected with an eleventh resistor R11 in series and then is used as a voltage output end for voltage output; and the voltage output end is connected with a twelfth pull-up resistor R12 connected with a 5V direct-current power supply. In the circuit described above: the impedance of the tenth resistor R10 and the eleventh resistor R11 determines the amplification coefficient of the amplification follower circuit, the twelfth resistor R12 further improves the driving capability of a rear-stage circuit through the pull-up action of the 5V direct-current power supply, and the direct-current signal distortion caused by too low impedance of a rear-stage measurement conversion circuit is prevented from influencing the measurement accuracy of the capacitor converted voltage. The direct current level after passing through the low-pass RC filter circuit is amplified.
Claims (8)
1. A capacitance-voltage conversion circuit comprises a CPU unit, a square wave excitation signal generating circuit, a capacitor to be tested (C), a synchronous digital detection circuit, a time-sharing integration circuit and a low-pass RC filter circuit; the CPU unit is used for generating a synchronous excitation signal and a logic control signal, wherein the synchronous excitation signal is a logic digital signal with '0' level and '1' level alternating according to a fixed period; the square wave excitation signal generating circuit is used for converting a reference level into a square wave excitation signal by taking the synchronous excitation signal as a trigger signal and outputting the square wave excitation signal; the square wave excitation signal is an analog signal with driving capability and is applied to the tested capacitor (C) to excite the tested capacitor (C); the synchronous digital detection circuit is connected to the return end of the tested capacitor (C) and is used for detecting the return signal of the tested capacitor (C) into an integral half-wave signal by taking the synchronous excitation signal as a trigger signal; the time-sharing integration circuit is used for performing time-sharing integration on the integrated half-wave signal by taking the synchronous excitation signal as a trigger signal and outputting a direct current level; the low-pass RC filter circuit is used for performing low-pass filtering on the direct current level, and is characterized in that: the device also comprises a level switching control circuit; the level switching control circuit is used for being controlled by a logic control signal output by the CPU unit and providing a 5V or 10V reference level for the square wave excitation signal generating circuit, the level switching control circuit comprises a two-stage operational amplifier circuit and a digital switching switch circuit, the two-stage operational amplifier circuit comprises a first operational amplifier (U1) and a second operational amplifier (U2), and a positive power supply end and a negative power supply end of the first operational amplifier (U1) and the second operational amplifier (U2) are respectively connected with a positive end and a negative end of a 15V power supply after passing through a current-limiting filter circuit; the positive input end of the first operational amplifier (U1) is connected with a 5V power supply, and the output end and the negative input end are connected with each other through a first resistor (R1) and a first capacitor (C1) which are connected in series; the output end of the first operational amplifier (U1) is also connected with the positive input end of a second operational amplifier (U2), and the negative input end of the second operational amplifier (U2) is connected with the output end thereof; the output end of the first operational amplifier (U1) and the output end of the second operational amplifier (U2) are connected after passing through a second resistor (R2) and a third resistor (R3); the output end of the second operational amplifier (U2) is connected with the inverting input end of the first operational amplifier (U1) through a third resistor (R3) and a fourth resistor (R4); the digital change-over switch circuit comprises a one-way digital switch (S), a fifth resistor (R5), a sixth resistor (R6), a second capacitor (C2) and a third capacitor (C3), wherein the control end of the one-way digital switch (S) is connected with a logic control signal output by the CPU unit and is connected with a 5V power supply through the sixth resistor (R6); the input end of the unidirectional digital switch (S) is connected with the inverted input end of the first operational amplifier (U1), and the output end of the unidirectional digital switch (S) is grounded after passing through a fifth resistor (R5); the second capacitor (C2) and the third capacitor (C3) are connected in parallel between the common end of the fourth resistor (R4) and the third resistor (R3) and the grounding end of the fifth resistor (R5).
2. The capacitance-to-voltage conversion circuit of claim 1, wherein: the capacitor voltage conversion circuit further comprises an amplification following circuit, and the amplification following circuit is used for amplifying the direct current level after passing through the low-pass RC filter circuit.
3. The capacitance-to-voltage conversion circuit of claim 2, wherein: the frequency of the synchronous excitation signal is 10.3 KHz.
4. A capacitance-to-voltage conversion circuit according to claim 3, wherein: the square wave excitation signal generation circuit comprises a first multi-path digital switch module, a first transistor (Q1), a second transistor (Q2), a variable resistor (R) and a fourth capacitor (C4); the first multi-way digital switch module includes a first digital switch (S1) and a second digital switch (S2); the control terminals of the first digital switch (S1) and the second digital switch (S2) are connected with a synchronous excitation signal, the input terminal of the first digital switch (S1) is grounded, the input terminal of the second digital switch (S2) is connected with a reference level, and the first digital switch (S1) and the second digital switch (S2) are always in an open-close state; the variable resistor (R) is connected in parallel between a first digital switch (S1) and a second digital switch (S2), the gate of the first transistor (Q1) is connected with a reference level, the source of the first transistor is connected with the output end of the first digital switch (S1) through a resistor, the gate of the second transistor (Q2) is grounded, the source of the second transistor is connected with the second digital switch (S2) through a resistor, the first transistor (Q1) is a low-gate CMOS, and the second transistor (Q2) is a high-gate CMOS; the first transistor (Q1) is connected with the drain electrode of the second transistor (Q2) and is connected with the measured capacitor (C) after passing through a fourth capacitor (C4).
5. The capacitance-to-voltage conversion circuit of claim 4, wherein: the synchronous digital detection circuit comprises a second multi-path digital switch module, a fifth capacitor (C5) and a seventh resistor (R7), the second multi-path digital switch module comprises a third digital switch (S3) and a fourth digital switch (S4), and the third digital switch (S3) and the fourth digital switch (S4) are always in an open-close state; the input ends of the third digital switch (S3) and the fourth digital switch (S4) are connected, and are connected with a fourth capacitor (C4) of the square wave excitation signal generating circuit after passing through a tested capacitor (C) and a current limiting resistor which are connected in series; the control ends of the third digital switch (S3) and the fourth digital switch (S4) are both connected with synchronous excitation signals; the output end of the fourth digital switch (S4) is grounded, the output end of the third digital switch (S3) is connected with the time-sharing integration circuit after passing through a seventh resistor (R7), and the output end of the third digital switch (S3) is grounded after passing through a filter capacitor; one end of the fifth capacitor (C5) is connected with the input ends of the third digital switch (S3) and the fourth digital switch (S4), and the other end of the fifth capacitor is connected with the time-sharing integration circuit.
6. The capacitance-to-voltage conversion circuit of claim 5, wherein: the time-sharing integration circuit comprises a first-stage operational following amplification circuit and an integration time-sharing control circuit, wherein the first-stage operational following amplification circuit comprises a third operational amplifier (U3) and a fourth operational amplifier (U4); the negative input end of the third operational amplifier (U3) is connected with a fifth capacitor (C5) in the synchronous digital detection circuit, and the negative input end and the output end of the third operational amplifier are connected with a low-pass filter circuit; the fourth operational amplifier (U4) is connected as a follow-up amplifying circuit; the integration time-sharing control circuit comprises a third multi-path digital switch module, a sixth capacitor (C6) and an eighth resistor (R8); the third multi-way digital switch module includes a fifth digital switch (S5), a sixth digital switch (S6), a seventh digital switch (S7); the control ends of the fifth digital switch (S5), the sixth digital switch (S6) and the seventh digital switch (S7) are all connected with synchronous excitation signals; the fifth digital switch (S5) and the seventh digital switch (S7) are always in the same opening and closing state, and the sixth digital switch (S6) is always in the opening and closing state; the input ends of the fifth digital switch (S5), the sixth digital switch (S6) and the seventh digital switch (S7) are connected with the output end of a fourth operational amplifier (U4); the output end of the fifth digital switch (S5) is connected with a low-pass RC filter circuit and used for outputting an integrated direct current level; an output terminal of the sixth digital switch (S6) is grounded; the output end of the seventh digital switch (S7) is connected with a sixth capacitor (C6) and an eighth resistor (R8) in series and then is connected with a seventh resistor (R7) in the synchronous digital detector circuit to form an integral loop.
7. The capacitance-to-voltage conversion circuit of claim 6, wherein: the low-pass RC filter circuit comprises a lightning protection diode (D1), a TVS (D2), a seventh capacitor (C7) and a ninth resistor (R9); the input end of the ninth resistor (R9) is connected with the output end of a fifth digital switch (S5) of the time-sharing integrating circuit, and the output end of the ninth resistor is connected with a seventh capacitor (C7) which is grounded and is connected with the amplifying follower circuit; the lightning protection diode (D1) and the TVS tube (D2) are connected to form a parallel loop, and the parallel loop is connected to the ninth resistor (R9) in parallel.
8. The capacitance-to-voltage conversion circuit of claim 7, wherein: the amplification follower circuit comprises a fifth operational amplifier (U5), a tenth resistor (R10), an eleventh resistor (R11) and a twelfth resistor (R12); the positive input end of the fifth operational amplifier (U5) is connected with a ninth resistor (R9) of the low-pass RC filter circuit, and the negative input end of the fifth operational amplifier (U5) is connected with the output end of the low-pass RC filter circuit through a tenth resistor (R10); the output end of the fifth operational amplifier (U5) is connected with an eleventh resistor (R11) in series and then is used as a voltage output end for voltage output; and the voltage output end is connected with a twelfth resistor (R12) connected with a direct current power supply.
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| CN111948457B (en) * | 2020-08-07 | 2023-02-03 | 四川泛华航空仪表电器有限公司 | Resistance card output resistance continuity detection device |
| CN114326542B (en) * | 2022-01-18 | 2023-12-05 | 杭州晶华微电子股份有限公司 | Industrial mixed control signal generation circuit |
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| CN1017746B (en) * | 1988-05-31 | 1992-08-05 | 株式会社三丰 | Capacitance-type measuring device for absolute measurement of positions |
| US20030222661A1 (en) * | 2002-01-11 | 2003-12-04 | Fasen Donald J. | Capacitance-based position sensor with integrating demodulator |
| US8487639B1 (en) * | 2008-11-21 | 2013-07-16 | Cypress Semiconductor Corporation | Receive demodulator for capacitive sensing |
| CN101832788A (en) * | 2009-03-11 | 2010-09-15 | 中国科学院电子学研究所 | Capacitor continuous time reading circuit adopting chopped wave stabilizing technology |
| CN102072737B (en) * | 2009-11-25 | 2012-07-04 | 中国科学院电子学研究所 | High accuracy capacitive readout circuit with temperature compensation |
| CN102148563B (en) * | 2010-02-10 | 2014-01-01 | 华为技术有限公司 | Tracking power supply, power control method and communication equipment |
| US8552316B2 (en) * | 2010-06-22 | 2013-10-08 | Infineon Technologies Ag | Sensor measurement system using pulsed current signals |
| CN202502163U (en) * | 2012-03-27 | 2012-10-24 | 南京信息工程大学 | Weak capacitance detection device for capacitive MEMS device |
| CN103236829B (en) * | 2013-03-27 | 2016-03-09 | 杭州远方仪器有限公司 | A kind of square wave circuit for generating |
| CN104296786B (en) * | 2014-09-30 | 2017-01-11 | 四川泛华航空仪表电器有限公司 | Digital bridge capacitive measuring module |
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