CN108009454B - Low-power-consumption decoding method and device - Google Patents
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- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
- G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves
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Abstract
The invention discloses a low-power consumption decoding method and a low-power consumption decoding device, wherein the method comprises the following steps: determining a first count value according to a preset power-on frequency, wherein the first count value is the count value collected in the Tari stage, and the power-on frequency is not less than 500 kHz; determining the sampling frequency of the RTcal stage according to the first counting value, and executing decoding operation at the sampling frequency; and carrying out error compensation on a second counting value according to the difference between the power-on frequency and the sampling frequency, wherein the second counting value is the counting value collected in the RTcal stage. The power-on frequency of the method is far less than the traditional value, so that the power consumption can be greatly reduced; and then, the working frequency is adjusted after the counting value of the Tari stage is determined by the electrifying frequency, so that the counting value is minimized while normal decoding is ensured, and the decoding function is completed at a lower working frequency.
Description
Technical Field
The present invention relates to the field of data decoding technologies, and in particular, to a low power consumption decoding method and apparatus.
Background
Radio Frequency Identification (RFID) is a communication technology that can identify a specific target and read and write related data through Radio signals. The RFID technology is widely used and can be applied to material management, access control systems and the like. ISO/IEC18000-6 Type C (6C for short) is based on the radio frequency identification international standard of article management, and the frequency is 860 MHz-960 MHz. Communication distance is one of the important criteria for evaluating the performance of an RFID product, and the main factor affecting communication distance for a passive RFID tag is the power consumption of the tag. The lower the power consumption, the longer the communication distance; the lower the operating frequency of the tag, the lower the power consumption. If the power-on working frequency of the tag is too low, the sampling rate is insufficient, and decoding fails. The power consumption of the system can be increased due to the fact that the power-on working frequency of the tag is too high, and the bottleneck of the communication distance is formed.
In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art:
the tag chip supporting the 6C protocol needs to decode the PIE (Pulse interval encoding) format code sent by the card reader, and the old design counts the PIE code at a fixed frequency of 1.28MHz in the decoding stage. With the continuous optimization of the power consumption of the tag chip, the decoding module has become a bottleneck of power consumption optimization.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a low-power-consumption decoding method and device, thereby overcoming the defect of higher power consumption when the PIE format code is decoded in the prior art.
The embodiment of the invention provides a low-power consumption decoding method, which comprises the following steps: determining a first count value according to a preset power-on frequency, wherein the first count value is a count value acquired in a Tari stage, and the power-on frequency is not less than 500 kHz; determining the sampling frequency of an RTcal phase according to the first counting value, and executing decoding operation at the sampling frequency; and carrying out error compensation on a second counting value according to the difference between the electrifying frequency and the sampling frequency, wherein the second counting value is a counting value collected in the RTcal stage.
In one possible implementation, the power-up frequency is 520 kHz.
In one possible implementation, the determining a sampling frequency of the RTcal phase according to the first count value includes: when the first counting value is larger than a first preset threshold value, taking the frequency lower than the electrifying frequency as a sampling frequency; when the first count value is smaller than a second preset threshold value, taking the frequency higher than the power-on frequency as a sampling frequency; when the first counting value is between the first preset threshold value and a second preset threshold value, taking the electrifying frequency as a sampling frequency; wherein the second preset threshold is not less than 6.
In one possible implementation, the power-on frequency is 520 kHz; when the first count value is greater than a first preset threshold value, the sampling frequency is 320 kHz; when the first count value is smaller than a second preset threshold value, the sampling frequency is 960 kHz.
In a possible implementation manner, when the first count value is smaller than a second preset threshold, the performing error compensation on the second count value according to the difference between the power-on frequency and the sampling frequency includes: and adding an error value to the second counting value, wherein the error value is 2 or 3.
Based on the same inventive concept, an embodiment of the present invention further provides a low power consumption decoding apparatus, including: the determining module is used for determining a first count value according to a preset power-on frequency, wherein the first count value is a count value acquired in a Tari stage, and the power-on frequency is not less than 500 kHz; the frequency switching module is used for determining the sampling frequency of the RTcal stage according to the first counting value and executing decoding operation according to the sampling frequency; and the compensation module is used for carrying out error compensation on a second counting value according to the difference between the electrifying frequency and the sampling frequency, wherein the second counting value is a counting value collected in the RTcal stage.
In one possible implementation, the power-up frequency is 520 kHz.
In one possible implementation, the frequency switching module is configured to: when the first counting value is larger than a first preset threshold value, taking the frequency lower than the electrifying frequency as a sampling frequency; when the first count value is smaller than a second preset threshold value, taking the frequency higher than the power-on frequency as a sampling frequency; when the first counting value is between the first preset threshold value and a second preset threshold value, taking the electrifying frequency as a sampling frequency; wherein the second preset threshold is not less than 6.
In one possible implementation, the power-on frequency is 520 kHz; when the first count value is greater than a first preset threshold value, the sampling frequency is 320 kHz; when the first count value is smaller than a second preset threshold value, the sampling frequency is 960 kHz.
In a possible implementation manner, when the first count value is smaller than a second preset threshold, the compensation module is configured to: and adding an error value to the second counting value, wherein the error value is 2 or 3.
According to the low-power-consumption decoding method and device provided by the embodiment of the invention, the minimum value of the power-on frequency is determined through analysis, namely the power-on frequency is not less than 500kHz, the frequency is far less than the traditional 1.28MHz, and the power consumption can be greatly reduced; and then, the working frequency is adjusted after the counting value of the Tari stage is determined by the electrifying frequency, so that the counting value is minimized while normal decoding is ensured, and the decoding function is completed at a lower working frequency. Meanwhile, the accuracy of decoding can be improved by error compensation.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for low power decoding according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a data header of a PIE encoding method according to an embodiment of the present invention;
FIG. 3 is a table of values of 6C standard parameters in accordance with an embodiment of the present invention;
fig. 4 is a block diagram of an apparatus for low power decoding according to an embodiment of the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, methods, means, elements well known to those skilled in the art have not been described in detail so as not to obscure the present invention.
According to an embodiment of the present invention, a low power decoding method is provided, where the method is used for decoding a PIE symbol of the ISO18000-6type c standard, and fig. 1 is a flowchart of the method, and specifically includes steps 101-103:
step 101: and determining a first count value according to a preset power-on frequency, wherein the first count value is the count value collected in the Tari stage, and the power-on frequency is not less than 500 kHz.
Step 102: and determining the sampling frequency of the RTCal phase according to the first counting value, and executing decoding operation at the sampling frequency.
The decoding method provided by the embodiment of the invention aims at a decoder of a 6C protocol PIE symbol, and aims to greatly reduce the working frequency of a decoding stage while ensuring the decoding correctness, thereby greatly reducing the power consumption and obviously improving the communication distance and the sensitivity of a label.
Specifically, as shown in fig. 2, the data header of the PIE coding scheme is in a Preamble format and a Frame-Sync format, and the data header sent to the tag by the reader/writer according to the 18000-6type c protocol. As shown in FIG. 2, the Frame-Sync has less TRcal phase part than Preamble, and the data header is followed by the data to be transmitted; in order not to affect the decoding of the data part in any case when using that header format, the adjustment of the operating frequency needs to be done within the Frame-Sync time, i.e. at least before the end of the RTcal phase.
Since the determination of the PIE symbol is based on the count value of the counter, the selection of the count value is important. For the same PIE symbol, the higher the count value is, the higher the frequency is, the higher the power consumption is, and the smaller the count value is, the lower the frequency is, the lower the power consumption is. Selecting the smallest count value possible while ensuring correct decoding can reduce the decoding frequency. In order to be able to distinguish data0 from data1 when decoding, the count value chosen takes into account two factors:
in practical use, the counted value has a deviation of + -1, and the ideal count value of data0 is a0Then a is0max＝a0+1,a0min＝a0-1. Let the ideal count value of data1 be a1Then a is1max＝a1+1,a1min＝a1-1. Due to data1>data0, so to distinguish data0 and data1 as long as a1min-a0max is not less than 1.
From the above conditions, it can be determined that:
further from the above conditions it follows: a is1-a0≥3 (1)
Meanwhile, according to the regulations of 18000-6C, 1.5 × data0 ≦ data1 ≦ 2 × data 0.
After simplification, the following is obtained:
it can be seen that when x is 1.5Take the maximum value of 6, so as long as a0It is sufficient that the number is more than or equal to 6, namely the counting value of the data0 is 6 at the minimum, so that the counting is accurate. Due to a0The larger the value, the higher the frequency required, so it is ideal to take a0＝6，9≤a1≤12。
Meanwhile, the table for taking values of the 6C standard parameters is shown in fig. 3, as shown in fig. 3, the default working frequency of the 6C standard decoding module is limited by a PW (Pulse Width) symbol, and the values of the PW symbol are shown in table 1:
TABLE 1
As shown in table 1, the minimum value of PW is 2us, so that the rising edge of the PIE symbol can be determined as long as 1 clock is satisfied and is smaller than 2us when power is on. The default operating frequency (power-on frequency) is at least 500kHz, i.e. the power-on frequency in step 101 is not less than 500 kHz. The default power-on frequency is set to 520kHz in view of robustness in actual use.
Meanwhile, as shown in fig. 2, the count value in the Tari stage is the count value of data0, and the count value collected in the Tari stage is determined at the power-on frequency of not less than 500kHz, and the minimum count value is 6.
After the count value (i.e., the count value of data 0) acquired in the Tari stage is determined, the operating frequency can be adjusted according to the size of the count value. The working frequency of the decoding method provided by the embodiment of the invention is the power-on frequency at the beginning, and after the numerical value of the data0 is determined according to the power-on frequency, the working frequency is adjusted (the adjusted working frequency is called as the sampling frequency, the power-on frequency and the sampling frequency are essentially the same, and are both the same), specifically, the step 102 "determining the sampling frequency of the RTcal stage according to the first count value" includes:
step A1: and when the first counting value is larger than a first preset threshold value, taking the frequency lower than the power-on frequency as the sampling frequency.
Step A2: and when the first count value is smaller than a second preset threshold value, taking the frequency higher than the power-on frequency as the sampling frequency.
Step A3: and when the first counting value is between the first preset threshold value and the second preset threshold value, taking the power-on frequency as the sampling frequency.
In the embodiment of the invention, when the first count value (i.e. the count value of the data 0) is greater than the first preset threshold, it is indicated that the count value of the data0 is large enough, and at this time, the sampling can be accurately performed at a lower frequency, so that the sensitivity is ensured, and the power consumption can be reduced by adopting the lower frequency as the sampling frequency.
On the contrary, when the count value of the data0 is smaller than the second preset threshold (the second preset threshold is smaller than the first preset threshold, that is, the second preset threshold is the lower limit, and the first preset threshold is the upper limit), it is indicated that the count value of the data0 is too small, and at this time, a higher frequency is required to accurately sample, so that the higher frequency is required to be used as the sampling frequency to work.
When the first count value is between the first preset threshold and the second preset threshold, the 520kHz is smaller than the operating frequency (1.28MHz) in the prior art, so that the purpose of reducing power consumption can be achieved, and the operating frequency can be kept unchanged.
As described above, since the count value of the data0 is 6 at minimum, when the power-on frequency is equal to the sampling frequency (i.e. the situation shown in step A3), it needs to be ensured that the count value of the data0 is greater than or equal to 6, and the count value of the data0 is greater than (or greater than) the second preset threshold, so that the count value of the data0 is always greater than or equal to 6 only when the second preset threshold is not less than 6.
Step 103: and carrying out error compensation on a second counting value according to the difference between the power-on frequency and the sampling frequency, wherein the second counting value is the counting value collected in the RTcal stage.
For a signal of the same length, the count value will be smaller when counting at a low frequency and larger when counting at a high frequency, and when a frequency switch occurs, a first part of the signal which appears as a complete signal is counted at a first frequency and a second part is counted at a second frequency. Normally, the addition of the numerical values of the two parts is a counting value of a complete signal, but due to the fact that the counting frequency of the two parts is different, errors are caused, and therefore error compensation is needed. In the embodiment of the invention, the switching of the working frequency needs to be completed in an RTcal stage, namely, the former part of the RTcal stage adopts the electrifying frequency for counting, the latter part adopts the sampling frequency for counting, when the frequencies of the electrifying frequency and the sampling frequency are different, error compensation needs to be carried out, and the compensated counting value is determined according to the difference between the electrifying frequency and the sampling frequency.
According to the low-power-consumption decoding method provided by the embodiment of the invention, the minimum value of the power-on frequency is determined through analysis, namely the power-on frequency is not less than 500kHz, the frequency is far less than the traditional 1.28MHz, and the power consumption can be greatly reduced; and then, the working frequency is adjusted after the counting value of the Tari stage is determined by the electrifying frequency, so that the counting value is minimized while normal decoding is ensured, and the decoding function is completed at a lower working frequency. Meanwhile, the accuracy of decoding can be improved by error compensation.
Another embodiment of the present invention provides a method for decoding with low power consumption, which includes steps 101 and 104 shown in fig. 1, and the implementation principle and beneficial effects thereof refer to the embodiment shown in fig. 1. In addition, the power-on frequency in the present embodiment is 520 kHz; step 102 "determining the sampling frequency of the RTcal phase according to the first count value" specifically includes:
when the first count value is larger than a first preset threshold value, taking 320kHz as a sampling frequency;
when the first count value is smaller than a second preset threshold value, taking 960kHz as the sampling frequency;
when the first counting value is between a first preset threshold value and a second preset threshold value, taking the electrifying frequency as the sampling frequency; wherein the second preset threshold is not less than 6.
In the embodiment of the invention, the working frequency is set to three gears: 320kHz, 520kHz and 960 kHz. One form of frequency point gear division is specifically shown in table 2:
TABLE 2
As shown in table 2, in the embodiment of the present invention, the gear division includes all Tari lengths (i.e., 6.25 μ s to 25 μ s), the signal length in the Tari stage can be determined according to the count value acquired by the power-on frequency 520kHz, and when the length of the Tari stage is 12 to 19 μ s, the corresponding count value is 6.24 to 9.88, that is, the first preset threshold is 9.88, and the second preset threshold is 6.24 (the count value in an actual situation is an integer, the threshold set in this embodiment is set according to the length of the Tari stage, and it is required to ensure that the minimum count value at different sampling frequencies is not less than 6). When the count value of data0 is greater than 9.88, which indicates that the length of Tari stage is greater than 19 μ s, at this time, accurate counting can be achieved by using lower grade 320kHz, at this time, when counting is performed at 320kHz, the minimum count value of data0 is 6.08, which is greater than the minimum value 6 in the above analysis, that is, accurate counting can be guaranteed when counting is performed at 320 kHz. Similarly, when the length of the Tari stage is less than 12 μ s, the Tari stage is adjusted to work at 960 kHz; at this time, even if the length of the Tari phase is 6.25 μ s, the count value of data0 is the lowest at this time, which is 6.013, and thus accurate counting can still be guaranteed.
In one possible implementation manner, when the first count value is smaller than a second preset threshold, performing error compensation on the second count value according to a difference between the power-on frequency and the sampling frequency includes: an error value is added to the second count value, the error value being 2 or 3.
Specifically, the counting error in the embodiment of the present invention is mainly a synchronization error. According to the counting value of the Tari stage, clock switching is carried out in the RTcal stage, and if clock switching exists, counting errors can be caused due to the fact that the working frequencies of counters of the RTcal stage and the Tari stage are inconsistent. To avoid signal instability, the signal entering the decoding module needs two-stage synchronization for use, which introduces synchronization error. There are three cases:
(1)520kHz switching to 960kHz
At this time, because the resolution of 520kHz is not enough, a synchronization error is introduced, and the error value is estimated to be about 2.7, so that the error can be compensated by adding 2 or 3 to the count value.
(2)520kHz invariant
Since 520kHz resolution is sufficient, the synchronization error is small and can be left uncompensated here.
(3)520kHz switching to 320kHz
As shown in table 2, the clock frequency of 520kHz is about 1.923 μ s, the clock frequency of 320kHz is about 3.125 μ s, the synchronization error time is about 3.125-1.923 ═ 1.202 μ s, the count error is 1.202/3.125 ═ 0.38464, and the error is small, so that no compensation is required here.
According to the low-power-consumption decoding method provided by the embodiment of the invention, the minimum value of the power-on frequency is determined through analysis, namely the power-on frequency is not less than 500kHz, the frequency is far less than the traditional 1.28MHz, and the power consumption can be greatly reduced; and then, the working frequency is adjusted after the counting value of the Tari stage is determined by the electrifying frequency, so that the counting value is minimized while normal decoding is ensured, and the decoding function is completed at a lower working frequency. Meanwhile, the accuracy of decoding can be improved by error compensation.
The above describes a method flow of low power consumption decoding, which can also be implemented by a corresponding apparatus, and the structure and function of the apparatus are described in detail below.
Referring to fig. 4, an apparatus for low power consumption decoding provided in an embodiment of the present invention includes:
a determining module 41, configured to determine a first count value according to a preset power-on frequency, where the first count value is a count value acquired in a Tari stage, and the power-on frequency is not less than 500 kHz;
a frequency switching module 42, configured to determine a sampling frequency of the RTcal phase according to the first count value, and perform a decoding operation at the sampling frequency;
and the compensation module 43 is configured to perform error compensation on a second count value according to a difference between the power-on frequency and the sampling frequency, where the second count value is a count value acquired in the RTcal stage.
In one possible implementation, the power-up frequency is 520 kHz.
In one possible implementation, the frequency switching module is configured to:
when the first counting value is larger than a first preset threshold value, taking the frequency lower than the power-on frequency as the sampling frequency;
when the first counting value is smaller than a second preset threshold value, taking the frequency higher than the power-on frequency as the sampling frequency;
when the first counting value is between a first preset threshold value and a second preset threshold value, taking the electrifying frequency as the sampling frequency;
wherein the second preset threshold is not less than 6.
In one possible implementation, the power-on frequency is 520 kHz;
when the first count value is greater than a first preset threshold value, the sampling frequency is 320 kHz;
when the first count value is smaller than the second preset threshold, the sampling frequency is 960 kHz.
In a possible implementation manner, when the first count value is smaller than the second preset threshold, the compensation module is configured to:
an error value is added to the second count value, the error value being 2 or 3.
According to the low-power-consumption decoding device provided by the embodiment of the invention, the minimum value of the power-on frequency is determined through analysis, namely the power-on frequency is not less than 500kHz, the frequency is far less than the traditional 1.28MHz, and the power consumption can be greatly reduced; and then, the working frequency is adjusted after the counting value of the Tari stage is determined by the electrifying frequency, so that the counting value is minimized while normal decoding is ensured, and the decoding function is completed at a lower working frequency. Meanwhile, the accuracy of decoding can be improved by error compensation.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (6)
1. A method of low power decoding, comprising:
determining a first count value according to a preset power-on frequency, wherein the first count value is a count value acquired in a Tari stage, and the power-on frequency is 520 kHz;
determining the sampling frequency of an RTcal phase according to the first counting value, and executing decoding operation at the sampling frequency; and
performing error compensation on a second counting value according to the difference between the electrifying frequency and the sampling frequency, wherein the second counting value is a counting value collected in an RTcal stage;
wherein the determining a sampling frequency of an RTcal phase from the first count value comprises:
when the first counting value is larger than a first preset threshold value, taking the frequency lower than the electrifying frequency as a sampling frequency;
when the first count value is smaller than a second preset threshold value, taking the frequency higher than the power-on frequency as a sampling frequency;
when the first counting value is between the first preset threshold value and a second preset threshold value, taking the electrifying frequency as a sampling frequency;
wherein the second preset threshold is not less than 6.
2. The method of claim 1,
when the first count value is greater than a first preset threshold value, the sampling frequency is 320 kHz;
when the first count value is smaller than a second preset threshold value, the sampling frequency is 960 kHz.
3. The method of claim 2, wherein when the first count value is less than a second preset threshold, the error compensating the second count value according to the difference between the power-up frequency and the sampling frequency comprises:
and adding an error value to the second counting value, wherein the error value is 2 or 3.
4. An apparatus for low power decoding, comprising:
the determining module is used for determining a first count value according to a preset power-on frequency, wherein the first count value is a count value acquired in a Tari stage, and the power-on frequency is 520 kHz;
the frequency switching module is used for determining the sampling frequency of the RTcal stage according to the first counting value and executing decoding operation according to the sampling frequency; and
the compensation module is used for carrying out error compensation on a second counting value according to the difference between the electrifying frequency and the sampling frequency, wherein the second counting value is a counting value collected in an RTcal stage;
wherein the frequency switching module is configured to:
when the first counting value is larger than a first preset threshold value, taking the frequency lower than the electrifying frequency as a sampling frequency;
when the first count value is smaller than a second preset threshold value, taking the frequency higher than the power-on frequency as a sampling frequency;
when the first counting value is between the first preset threshold value and a second preset threshold value, taking the electrifying frequency as a sampling frequency;
wherein the second preset threshold is not less than 6.
5. The apparatus of claim 4,
when the first count value is greater than a first preset threshold value, the sampling frequency is 320 kHz;
when the first count value is smaller than a second preset threshold value, the sampling frequency is 960 kHz.
6. The apparatus of claim 5, wherein when the first count value is less than a second preset threshold, the compensation module is configured to:
and adding an error value to the second counting value, wherein the error value is 2 or 3.
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