CN107995142B

CN107995142B - 0dB power back-off common mode amplitude modulator and quadrature amplitude modulation transmitter

Info

Publication number: CN107995142B
Application number: CN201711259748.3A
Authority: CN
Inventors: 郭海燕
Original assignee: Individual
Current assignee: Individual
Priority date: 2017-12-04
Filing date: 2017-12-04
Publication date: 2020-12-22
Anticipated expiration: 2037-12-04
Also published as: CN107995142A

Abstract

The invention relates to a quadrature amplitude modulation transmitter and four 0dB power back-off common mode amplitude modulators therein, which respectively input carrier sinusoidal signals with the same amplitude and phases of 0, 180, 90 and 270 degrees. A first coil of the inductor or the transformer applies sinusoidal signals of differential carrier frequency, or the first coil applies single-ended carrier signals; the inductor or the center tap of the second coil receives the amplitude modulation signal and dynamically controls the grid levels of the two transistors. The center tap is a virtual point of the differential signal, the amplitude of the carrier frequency signal is 0, any circuit is connected, and the load of the circuit does not attenuate the carrier frequency signal. The drains of the two transistors output amplitude-modulated modulation signals. The invention can effectively combine the amplitude modulator and the power amplifier together, and realize the amplitude modulation of the output power by dynamically changing the gain and the saturated output power of the power amplifier under the condition of ensuring the maximum power addition efficiency.

Description

0dB power back-off common mode amplitude modulator and quadrature amplitude modulation transmitter

Technical Field

The invention relates to a radio frequency wireless communication technology, in particular to a 0dB power backspacing common mode amplitude modulator, a quadrature amplitude modulation transmitter and a quadrature amplitude modulation signal synthesis method.

Background

A system block diagram of a conventional quadrature amplitude modulation transmitter is shown in fig. 15. The quadrature amplitude modulation signal is generated by a quadrature amplitude modulator, the quadrature amplitude modulation signal comprising QPSK, 16QAM, 64QAM, …,4ⁱQAM (i is an integer of 1 or more). The quadrature amplitude modulation signal is input to a power amplifier to amplify the amplitude of the signal. The quadrature amplitude modulation signal after amplitude amplification is input to a band-pass filter to filter out signal energy outside a frequency band. And finally, the quadrature amplitude modulation signal is radiated and output through an antenna.

The disadvantages of the conventional quadrature amplitude modulation transmitter are mainly expressed in two aspects: 1. in order to ensure that the group delay of the carrier signal does not change during the process of amplifying the quadrature amplitude modulation signal by the power amplifier, the power amplifier needs to realize broadband input impedance matching and broadband output impedance matching. In practical circuit designs, this is usually achieved at the expense of amplifier gain and amplifier dc power consumption to achieve this broadband performance. 2. The power amplifier has a saturated output power, and when the output power of the amplifier is close to the saturated output power, the gain of the power amplifier gradually decreases (i.e., the output power varies with the input power and is nonlinear). For quadrature amplitude modulation signals, due to amplitude modulation, power amplifiers operating in a nonlinear region have different gains for input signals with different signal amplitudes, so that the quadrature amplitude modulation signals have amplitude distortion after being amplified by the power amplifiers.

The current solution in academia and industry is to reduce the power of the input signal of the power amplifier to keep the output power of the power amplifier away from the saturation power, so that the power amplifier has the same gain for input signals with different amplitudes, and the amplitude distortion existing after the quadrature amplitude modulation signal is amplified by the power amplifier is minimized. The difference between the saturated output power and the actual output power of the power amplifier is the power back-off. For quadrature amplitude modulated signals, the power back-off is typically set above 8 dB. The Power Added Efficiency (PAE) of the power amplifier is highest when the output power of the power amplifier is close to the saturation output power, that is, the efficiency of converting the direct current power consumption into the alternating current output signal power of the power amplifier is highest. If the power back-off of the power amplifier is set at 8dB, the power added efficiency of the power amplifier is 6 times or more lower than the power added efficiency when the power back-off of the power amplifier is set at 0 dB.

For any configuration of power amplifier, the output power (upper line) versus input power and the power added efficiency (lower line) versus input power can be represented by fig. 5. The power amplifier has the highest power added efficiency at a position close to the saturated output power.

For a conventional amplitude modulation transmitter, in which the power amplifier in the transmitter maintains linear amplification of the amplitude modulated signal, the output power of the transmitter is limited to below the 1dB power compression point, typically 8dB less than the saturated output power. This can severely reduce the power added efficiency of the power amplifier. The Power Added Efficiency (PAE) is calculated as:

in the power amplifier of the conventional structure, the direct current power consumption has no relation with the output power. Therefore, when the output power is reduced, the power added efficiency is reduced.

Disclosure of Invention

The invention provides a 0dB power backspacing common mode amplitude modulator and a quadrature amplitude modulation transmitter, which can effectively combine an amplitude modulator and a power amplifier together and realize amplitude modulation of output power by dynamically changing gain and saturation output power of the power amplifier under the condition of ensuring power added efficiency. The invention also provides a method for synthesizing the Quadrature Amplitude Modulation (QAM) signal.

In order to achieve the above object, an aspect of the present invention is to provide a 0dB power back-off common mode amplitude modulator, wherein:

both ends of the a coil of the first transformer T1 are connected to the carrier signal input port, and receive a sinusoidal signal of a differential carrier frequency, an alternating current component of which is coupled to the B coil through the a coil of the first transformer T1;

the gates of the transistor M1 and the transistor M2 are respectively connected with two ends of the coil B in the first transformer T1;

a node Vmod is included in the B coil of the first transformer T1, and as a virtual point of the differential signal, the gate levels of the transistor M1 and the transistor M2 are dynamically controlled by applying an amplitude modulation signal to the node Vmod, so that the amplification gain of the transistor M1 and the transistor M2 on the carrier frequency signal input to the gates is controlled, and the amplitude modulation of the carrier frequency signal is realized;

the drains of the transistor M1 and the transistor M2 are connected to a differential output port, and output amplitude-modulated modulation signals.

In an alternative 0dB power back-off common mode amplitude modulator, two ends of the a coil of the first transformer T1 are connected to the carrier signal input port, and a connection mode for receiving a sinusoidal signal of a differential carrier frequency is replaced by a connection mode in which one end of the a coil of the first transformer T1 is ac-coupled to ground through a capacitor Cp1 or directly connected to ground, and the other end of the a coil is connected to the carrier signal input port to receive a single-ended carrier signal, and the single-ended carrier signal is converted into a differential carrier signal through the a coil and the B coil of the first transformer T1 and output.

In an optional 0dB power back-off common mode amplitude modulator, the first transformer T1 is replaced by an inductor L1, and a carrier signal input port is connected across the inductor L1 to obtain a sinusoidal signal of a differential carrier frequency, and the sinusoidal signal is applied to gates of a transistor M1 and a transistor M2 which are respectively connected across the inductor L1;

the inductor L1 includes a node Vmod as a virtual ground for a differential signal, and the gate levels of the transistors M1 and M2 are dynamically controlled by applying an amplitude modulation signal to the node Vmod.

In any 0dB power back-off common mode amplitude modulator, optionally, a circuit structure capable of conducting a dc signal and providing impedance for an ac signal is disposed between the drains of the transistor M1 and the transistor M2, so as to provide a dc voltage and a current to the drains of the transistor M1 and the transistor M2.

Optionally, an electrically controlled switch is arranged between the gates of the transistor M1 and the transistor M2;

when the electric control switch is turned on, the differential signals on the gates of the transistor M1 and the transistor M2 are mutually cancelled; the electrically controlled switch does not attenuate the differential signal on the gates of transistor M1 and transistor M2 when the electrically controlled switch is open.

Optionally, the 0dB power back-off common mode amplitude modulator further includes any one or any combination of a level shifter, a first adjustable impedance module, and a second adjustable impedance module, so that in case of any input data, the phase difference between the carrier signal of the differential output port and the carrier signal of the carrier signal input port is the same, and the impedance of the differential output port remains unchanged;

the level shifter applies an amplitude modulation signal to a node Vmod connected with the level shifter, and adjusts the voltage value of the node Vmod so as to change the gains of the transistors M1 and M2 and compensate the distortion of the amplitude of the carrier signal;

the first adjustable impedance module is connected between the gates of the transistor M1 and the transistor M2; the second adjustable impedance module is connected between the drain of the transistor M1 and the drain of the transistor M2; the carrier signal phase and amplitude distortion is compensated for by the impedance provided by the first adjustable impedance block and/or the second adjustable impedance block.

Optionally, the first input port V [ 1: n ] connecting n different analog DC levels; the second input port CB [ 1: n ] are connected to n first data control lines, and n switches controlled by the n first data control lines control the first input port V [ 1: n ] whether the applied DC level is passed to an output port of the level shifter;

the third input port of the level shifter is connected with a second data control line corresponding to the potential of the node SW, and a switch controlled by the second data control line controls whether the output port of the level shifter is grounded;

among the n switches controlled by the n first data control lines and the switches controlled by the second data control line, only one switch is in a conducting state at any time.

Optionally, the first adjustable impedance module is provided with n first impedance adjustment values; only one of the first impedance adjustment values is applied to the gates of the transistor M1 and the transistor M2 at any time through the control of the n first data control lines;

and/or the second adjustable impedance module is provided with n +1 second impedance adjustment values; only one of the second impedance adjustment values is applied to the drains of the transistors M1 and M2 at any time by the control of the n first data control lines and the second data control line corresponding to the potential of the node SW.

Optionally, the transistor M1 is replaced by a first triode correspondingly, and the gate, the source and the drain of the transistor M1 are replaced by the base, the emitter and the collector of the first triode correspondingly;

the transistor M2 is replaced by a second triode correspondingly, and the grid electrode, the source electrode and the drain electrode of the transistor M2 are replaced by the base electrode, the emitter electrode and the collector electrode of the second triode correspondingly.

Another technical solution of the present invention is to provide a quadrature amplitude modulation transmitter, which includes four 0dB power back-off amplitude modulators, referred to as Ip, In, Qp, and Qn, having the same structure;

carrier signal input ports C of the four 0dB power back-off amplitude modulators, denoted as CIp, CIn, CQp and CQn, respectively, input carrier sinusoidal signals of the same amplitude and phase of 0 degrees, 180 degrees, 90 degrees and 270 degrees, respectively;

gates of the transistor M1 and the transistor M2, corresponding to nodes M1_ G and M2_ G; drains of the transistor M1 and the transistor M2, corresponding to nodes M1_ D and M2_ D;

the quadrature amplitude modulation transmitter further comprises: the second transformer T2, the band-pass filter and the antenna are shared by four 0dB power backspacing amplitude modulators Ip, In, Qp and Qn;

nodes M1_ D of the four 0dB power back-off amplitude modulators are all connected to a common node outp; nodes M2_ D of the four 0dB power back-off amplitude modulators are all connected to a common node outn;

both ends of the B coil of the second transformer T2 are connected to nodes outp and outn, respectively; the center tap of the coil B of the second transformer T2 is connected with a power supply VDD; one end of the coil A of the second transformer T2 is grounded, and the other end is connected with the input end of the band-pass filter; the output end of the band-pass filter is connected with the antenna.

Optionally, each 0dB power back-off amplitude modulator shares a third adjustable impedance module X, two ends of the third adjustable impedance module X are respectively connected to nodes outp and outn, and impedance of the third adjustable impedance module X is (4)^m+2^m) The/2 control line BX controls the impedance at the nodes outp and outn to be constant in both the two control modes described below;

two ends of the first adjustable impedance module of each 0dB power back-off amplitude modulator are respectively connected with nodes M1_ G and M2_ G in the 0dB power back-off amplitude modulator; level shifter for each of the 0dB power back-off amplitude modulatorsConnected to node Vmod to apply an amplitude modulated signal; the control lines of the first adjustable impedance module and the level shifter both comprise 2^m+1-1 drop-out line connected to port BB of the 0dB power back-off amplitude modulator; the level shifter is also connected to a port V common to four 0dB power back-off amplitude modulators, receiving an input of 2^m+1-1 analog dc level;

wherein the value of m is determined by the type of QAM: m ═ 0 for QPSK; m is 1 corresponding to 16 QAM; m is 2 for 64QAM, and so on to 4ⁱM-i-1 corresponding to QAM;

the ports S of the four 0dB power back-off amplitude modulators are respectively connected to different data control lines SIp, SIn, SQp and SQn, and the ports BB of the four 0dB power back-off amplitude modulators are respectively connected to different data control lines BIp, BIn, BQp and BQn, so as to realize amplitude modulation of carrier sinusoidal signals of four phases of 0 degrees, 180 degrees, 90 degrees and 270 degrees:

when the data control line corresponding to the port S in each 0dB power back-off amplitude modulator controls the switch between the connection nodes M1_ G and M2_ G in the 0dB power back-off amplitude modulator to be conducted and the output of the level shifter is grounded, the direct current potentials of the grid electrodes of the transistor M1 and the transistor M2 of the 0dB power back-off amplitude modulator are 0, and the carrier signals of the grid electrode difference are mutually cancelled;

alternatively, when the data control line corresponding to the port S in each 0dB power back-off amplitude modulator controls the switch between the connection nodes M1_ G and M2_ G in the 0dB power back-off amplitude modulator to be turned on and the output of the level shifter is not grounded, the output potential of the level shifter is determined by the data control line corresponding to the port BB in the 0dB power back-off amplitude modulator, and the output impedance of the first adjustable impedance in the 0dB power back-off amplitude modulator is controlled by the data control line corresponding to the port BB, thereby realizing the amplification gain control of the differential carrier signal by the transistor M1 and the transistor M2 in the 0dB power back-off amplitude modulator and further realizing the amplitude modulation of the differential carrier signal.

Optionally, in the qam transmitter, the transistor M1 is replaced by a first transistor, and the gate, the source, and the drain of the transistor M1 are replaced by the base, the emitter, and the collector of the first transistor;

Another technical solution of the present invention is to provide a method for synthesizing a qam signal, which is suitable for any one of the qam transmitters described above;

carrying out amplitude modulation on the two vectors in the I direction and the Q direction, and superposing the modulated vectors to obtain a constellation diagram, wherein the included angle between a point in the constellation diagram and a connecting line of an original point represents the phase of the carrier frequency of the modulation signal, and the distance between the point and the connecting line of the original point represents the amplitude of the carrier frequency of the modulation signal;

the points in the constellation diagram are distributed according to the distribution mode of the QAM constellation diagram described below and are matched with the following two types of control modes, including:

the points in the constellation lie on the coordinate axis in the I direction or the Q direction: when the switch between the grids of the transistors M1 and M2 in each 0dB power back-off amplitude modulator is disconnected and the level converter in the 0dB power back-off amplitude modulator outputs a certain non-0 control level under the state that different amplitude control levels are input, the switches between the grids of the transistors M1 and M2 of the other three 0dB power back-off amplitude modulators are switched on and the outputs of the level converters corresponding to the transistors M1 and M2 are grounded; then the impedance characteristics at the nodes outp and outn of the quadrature amplitude modulation transmitter, determined by the drain impedances of the transistors M1, M2 in this 0dB power back-off amplitude modulator with the switches open, are such that the output power of the transmitter is at a state of saturated output power and the power added efficiency is at a peak; and the number of the first and second groups,

the points in the constellation do not lie on the coordinate axis in the I or Q direction: dividing four groups by 0dB power backspacing amplitude modulators Ip and Qp, In and Qp, Ip and Qn, In and Qn, and sequentially enabling the switches between the grids of the transistors M1 and M2 In two 0dB power backspacing amplitude modulators In each group to be switched off and the level converter In the 0dB power backspacing amplitude modulator outputs a certain non-0 control level when the switches between the grids of the transistors M1 and M2 In the other two 0dB power backspacing amplitude modulators are switched on and the outputs of the corresponding level converters are grounded respectively under the state that different amplitude control levels are input; then the impedance characteristics at the nodes outp and outn of the quadrature amplitude modulation transmitter, determined by the drain impedances of the transistors M1, M2 in the two 0dB power back-off amplitude modulators with the switches off, are jointly such that the output power of the transmitter is in a state of saturated output power and the power added efficiency is lower than the peak value and higher than half of the peak value;

the invention also has a technical scheme that a distribution mode of the QAM constellation diagram is provided, the original QAM constellation diagram is rotated counterclockwise by (2N +1)45 degrees N to obtain a new QAM constellation diagram for N, so that the power synthesis efficiency is improved; four diagonal points corresponding to the maximum power in the original QAM signal constellation diagram are respectively synthesized by two vectors in the I direction and the Q direction; the four diagonal points corresponding to the maximum power in the new QAM constellation are respectively synthesized by a vector in the I direction or the Q direction.

Compared with the prior art, the invention has the advantages that:

the proposed common mode amplitude modulator effectively combines an amplitude modulator and a power amplifier. Amplitude modulation of the output power is achieved by dynamically changing the gain and saturated output power of the power amplifier under conditions that guarantee power added efficiency. As shown in fig. 6. When the gate voltage of the transistors M1, M2 changes from V3 to V1, it can be seen from the figure that on the one hand the differential gain of the amplifier decreases and on the other hand its saturated output power also decreases, and at the same time the dc power consumption of the transistors M1, M2 also decreases. The nonlinear amplitude modulator has the advantages that the amplifying tube can enable the output power of the nonlinear amplitude modulator to always work at a saturation output power point, and the power addition efficiency of the nonlinear amplitude modulator is maximized.

The invention arranges the inductance coil with symmetrical structure in the quadrature amplitude modulation transmitter structure with 0dB power back-off and the quadrature 0dB power back-off common mode amplitude modulator as the inductance connected with the grids of two transistors or the coil of the transformer; the center tap of the inductance coil receives an amplitude modulation signal provided by a level converter so as to dynamically control the grid levels of the two transistors. The center tap is a virtual point of the differential signal, the amplitude of the carrier frequency signal is 0, any circuit is connected, and the load of the circuit can not attenuate the carrier frequency signal.

According to the invention, the electric control switch is arranged on the grid electrodes connected with the two transistors, when the electric control switch is conducted, the differential carrier signals on the grid electrodes of the two transistors are mutually offset, and at the moment, the structure plays a good role in attenuating the differential carrier signals; when the electric control switch is switched off, the differential carrier signals on the two transistor grids are mutually isolated, and the structure plays a good role in isolating the differential carrier signals. The electronically controlled switch may therefore assist the amplitude modulation transmitter of the present invention in achieving better switching rejection.

The invention arranges the adjustable impedance structure on the grid electrode connected with the two transistors and the drain electrode connected with the two transistors. The purpose is to make the phase difference between the carrier signal of the differential output port and the carrier signal of the differential input port the same in any case of input data (corresponding to outputting any amplitude of carrier signal), and to keep the impedance of the differential output port unchanged.

The QAM constellation diagram of the invention can be obtained by rotating (2N +1) N ∈ N by 45 degrees anticlockwise through the traditional QAM constellation diagram. The novel QAM constellation diagram has higher power synthesis efficiency. In all kinds of new QAM signal vector synthesis modes, the four-corner node efficiency is doubled compared with that of the traditional QAM signal vector synthesis mode in power synthesis. It can be proved that the power efficiency of all nodes in the QAM signal vector synthesis scheme of the present invention is higher than the power efficiency of the corresponding nodes in the conventional QAM signal vector synthesis scheme.

Drawings

FIG. 1 is a schematic diagram of a 0dB power back-off common mode amplitude modulator in a first embodiment;

FIG. 2 is a waveform diagram of nodes Vmod, SW, M1_ G, M1_ D of FIG. 1;

FIG. 3 is a schematic diagram of the level shifter of FIG. 1;

FIG. 4 is an exemplary block diagram of the first adjustable impedance module shown in FIG. 1;

FIG. 4a is an exemplary block diagram of the second adjustable impedance module shown in FIG. 1;

FIG. 5 is a graph of output power, power added efficiency versus input power for a power amplifier;

FIG. 6 is a graph of output power versus input power for a transistor with a change in gate voltage;

FIG. 7 is a diagram of DC power consumption versus input power when the gate voltage of the transistor changes;

FIG. 8 is a schematic diagram of a dual-turn inductor that may be used as the B coil of the transformer of FIG. 1;

FIG. 9 is a schematic diagram of a 0dB power back-off common mode amplitude modulator in a second embodiment;

FIG. 10 is a schematic diagram of a 0dB power back-off common mode amplitude modulator in a third embodiment;

FIG. 11 is a schematic diagram of a quadrature amplitude modulation transmitter with 0dB power back-off;

FIG. 12 is a constellation diagram of a 0dB power back-off QAM transmitter representing the amplitude and phase of the modulated signal at 16 QAM;

FIG. 13 is a schematic diagram of a conventional QAM signal vector synthesis approach;

FIG. 14 is an output stage structure for generating a carrier signal of a particular amplitude;

fig. 15 is a system block diagram of a conventional quadrature amplitude modulation transmitter.

Detailed Description

As shown in fig. 1, the present invention provides a 0dB power back-off common mode amplitude modulator. The transistors M1 and M2 have the same structure and size, and the gates of the transistors M1 and M2 are connected to an electrically controlled switch, the on and off of which are controlled by the potential of the node SW. The gates of the transistor M1 and the transistor M2 are also connected to the two ends of the B coil in the transformer T1, respectively. The center tap of the B coil in the transformer T1 is a node Vmod, which is connected to the output terminal of the level shifter, and from which an amplitude modulation signal is inputted, the gate levels of the transistor M1 and the transistor M2 are dynamically controlled.

The two ends of the a coil in the transformer T1 are connected to differential input terminals, and a sinusoidal signal of a differential carrier frequency is input from this port. The drains of the transistor M1 and the transistor M2 are connected to a differential output terminal, and an amplitude-modulated modulation signal is output from this terminal.

The power supply VDD is connected to the drains of the transistor M1 and the transistor M2 through the DCF1 and the DCF2 to supply a dc voltage and a dc current thereto. DCF1 and DCF2 represent structures that can conduct a dc signal but block an ac signal. In an actual circuit, the DCF1 and the DCF2 can be replaced by an inductor, a transformer and the like.

The specific implementation process of the 0dB power back-off common mode amplitude modulator is as follows:

a sinusoidal signal of a differential carrier frequency is input from the input port to the a coil of the transformer T1, and the alternating current component of the signal is coupled from the a coil to the B coil through the transformer T1. The transient dc levels at the gates of transistor M1 and transistor M2 are determined by the amplitude modulation signal input at node Vmod.

For ease of understanding, fig. 2 shows the corresponding relationship of the waveforms at the nodes Vmod, SW, M1_ G (gate of the transistor M1) and M1_ D (drain of the transistor M1). In the figure, Vmod presents 4 analog potentials, 0, V1, V2 and V3, respectively, which correspond to four output amplitude modulations. Due to the presence of transistor non-linearity, the output amplitude does not vary linearly with the Vmod potential, but at least positively. There is always a particular Vmod potential present for a particular output amplitude to produce such an output amplitude. For the carrier frequency signal inputted in a differential mode, Vmod at the center tap of the B coil of the transformer T1 is a virtual point of the differential signal, so that the amplitude of the carrier frequency signal at node Vmod is 0, and node Vmod is connected to any circuit, and the load of the circuit will not attenuate the carrier frequency signal.

The potentials at node M1_ G and node M2_ G are the superposition of the differential mode carrier signal component coupled out of the B coil in transformer T1 and the common mode signal component input at the Vmod node. When the Vmod potential is 0, the amplitude of the output is desirably 0. However, when the signal amplitude of the input carrier signal is sufficiently large, the carrier signal can be amplified and output by the transistor even if the dc potentials of the gates of the transistor M1 and the transistor M2 are 0, and thus the output signal amplitude is not 0. In order to achieve an output signal amplitude of 0 when the Vmod potential is 0, a switching structure is introduced in the circuit structure. When the SW node control switch is turned on, the node M1_ G and the node M2_ G are at the same potential, and the input differential carrier signals are cancelled, so when the Vmod potential is 0 and the SW state is turned on, the DC potential of the gates of the transistor M1 and the transistor M2 is 0, the AC amplitude is 0, and the amplitude of the output signal is 0. When the Vmod potential is not 0, the SW node controls the switch to be switched off, and the input differential carrier signal does not have any attenuation at the input end of the transistor. When the direct current potentials of the grid electrodes of the transistors are different, the amplification gains of the transistors for the alternating current signals are different, so that the differential input signals with the same amplitude are amplified by different gains, and then differential signals with different amplitudes are output.

The structure of the level shifter is shown in FIG. 3, where input V [ 1: n ports are connected with n different analog direct current levels. Port CB [ 1: n ] ports are connected with n-channel data control lines, and respectively control V [ 1: n ] whether the dc level applied by the port can be transferred to the output port. The port SW is connected with a data control line to control whether the output port is grounded. Port CB [ 1: n ] and the switches controlled by the port SW, at any point in time, one and only one of the switches is in a conducting state. This is done by dynamically changing port CB [ 1: n ] and the data of the control line connected with the port SW can dynamically switch the DC level of the output port from time to time.

In the process of amplitude modulation, the 0dB common mode amplitude modulator can affect the impedance of the transistor M1 and the transistor M2 looking into the grid electrode and can affect the impedance of the transistor M1 and the transistor M2 looking into the drain electrode due to the change of the grid electrode potentials of the transistor M1 and the transistor M2. These impedance changes can distort the phase and amplitude of the carrier signal.

In order to compensate the distortion of the amplitude and the phase of the carrier signal, a first adjustable impedance module is connected between a node M1_ G and a node M2_ G, a second adjustable impedance module is connected between a node M1_ D and a node M2_ D, the first adjustable impedance module is controlled by n data lines and corresponds to n different potential values input by a Vmod node; the second adjustable impedance module is controlled by n +1 data lines and corresponds to n different potential values and 0 potential value input by the Vmod node.

The first adjustable impedance block may adopt the configuration shown in fig. 4, and the second adjustable impedance block may adopt the configuration shown in fig. 4a (there are actually a number of alternative configurations for both, the illustrated configuration being only one of them): in the first tunable impedance block, n impedance elements Z1, Z2. of different impedance values, Zn are connected to the port PORTn and the port PORTp, respectively, through two switches. The switch across impedance Z1 is controlled to turn on or off by control line CB [1 ]. The switch across impedance Z2 is controlled to turn on or off by control line CB [2 ]. By analogy, the switches at the two ends of the impedance element Zn are controlled to be switched on or switched off through a control line CB [ n ]. CB [ 1: n ] the switches controlled by one and only one control line are in the on state, and the switches controlled by the other control lines are in the off state. The second adjustable impedance block further includes an n +1 th impedance element Zn +1 having an impedance value different from that of the other impedance elements, connected to the port PORTn and the port PORTp through two switches, and controlled to be turned on or off by a potential of the SW node.

The adjustable impedance structure has many variant structures, the level shifter also has many variant structures, and any structure which aims to make the phase difference between the carrier signal of the differential output port and the carrier signal of the differential input port identical under any input data (corresponding to the output of the carrier signal with any amplitude) and keep the impedance of the differential output port unchanged is within the protection scope of the invention.

As shown in fig. 6 and 7, when the gate voltages of the transistors M1 and M2 change from V3 to V1, it can be seen that, on the one hand, the differential gain of the amplifier decreases, and on the other hand, the saturated output power thereof also decreases, and at the same time, the dc power consumption of the transistors M1 and M2 also decreases. The nonlinear amplitude modulator has the advantages that the amplifying tube can enable the output power of the nonlinear amplitude modulator to always work at a saturation output power point, and the power addition efficiency of the nonlinear amplitude modulator is maximized.

For the amplitude modulated signal input from node Vmod in fig. 1, we expect that the signal passed to the gate of transistor M1, M2 is free of amplitude and phase distortion. The amplitude modulation signal from the node Vmod is transmitted to the gate of the transistor M1, M2 through the B-coil inductance of the transformer T1 and the gate parasitic capacitance of the transistor M1, M2. This is a low-pass network formed by a series inductor and a parallel capacitor, and the inductance value of the inductor in the network needs to be reduced as much as possible in order to reduce the influence of the network on the amplitude and phase of the signal. Therefore, the present invention provides an inductor structure for reducing the common mode inductance value of the inductor under the condition of keeping the differential mode inductance value of the inductor unchanged, as shown in fig. 8.

Fig. 8 shows a double-coil inductor, where point a1 and point a2 are the connection points of the inner and outer coils, respectively, and point t1 is located in the middle of the inner coil; point b1 and point b2 are the two end points of the outer ring. It is known that the inductance of the metal line from the point a1 to the point t1 is the same as the inductance of the metal line from the point a2 to the point t1, and is L₁. The inductance of the wire from point a1 to point b2 is the same as the inductance of the wire from point a2 to point b1, L₂. The mutual inductance of the wires a1-t1 and a2-b1 is the same as the mutual inductance of the wires a2-t1 and a1-b2, and is M₁₂，M₁₂Can be expressed as:

then, for the differential signals input from the point b1 and the point b2, at this time point t1 is the virtual point of the inductor, the equation of the differential mode impedance can be expressed as:

Z_odd＝jωL₂+jωM₁₂+jωL₁+jωM₁₂+jωL₁+jωM₁₂+jωL₂+jωM₁₂

＝jω(2L₁+2L₂+4M₁₂)

for the common mode signals input from points b1 and b2, point t1 is not the virtual ground point of the inductor at this time. the common mode impedance from point t1 to points b1 and b2 is given by the formula:

Z_odd＝jωL₂-jωM₁₂+jωL₁-jωM₁₂+jωL₁-jωM₁₂+jωL₂-jωM₁₂

＝jω(2L₁+2L₂-4M₁₂)

therefore, the common mode impedance from point t1 to points b1 and b2 becomes small due to mutual inductance, and due to the closely symmetrical structural characteristics of the coils, the common mode impedance is L₁≈L₂≈L,k₁₂≈1。k₁₂Is the mutual inductance. Therefore, it is not only easy to use

2L₁+2L₂-4M ₁₂0. Thus the common mode impedance Z of the actual double-coil inductor structure_oddWill exhibit a ratio j ω (L)₁+L₂) Much less perceptual.

For a multi-turn (p) inductor, the ith turn of the inductor has two symmetrical structures and the inductance value is L_iIs (1 is not less than i is not more than p), L_iAnd L_jHas a mutual inductance of M_ij，(1≤j≤p,j≠i)。

For a multi-turn inductor, when the number of turns p is even, the common-mode impedance can be expressed as:

when L is₁≈L₂≈…≈L_pApproximately equals L, and when the mutual inductance coefficient k between any two metal wires is close to 1, Z_oddThe same holds true. Therefore, the common-mode impedance Z of the actual p-turn (p is even number) inductance structure_oddWill exhibit a ratio

Much less perceptual.

For a multi-turn inductor, when the number of turns p is odd, the common-mode impedance can be expressed as:

when L is₁≈L₂≈…≈L_pApproximately equals L, and when the mutual inductance coefficient k between any two metal wires is close to 1, Z_oddJ ω 2L. When the number of turns p is sufficiently large, the common-mode impedance Z_oddWill also exhibit a ratio

Much less perceptual.

The common-mode mutual inductance generated by the inductor exemplified in fig. 8 and any inductor of symmetrical structure having an inductance value L with the p-turn inductor can be expressed by the following relation_iThe mutual inductance of the metal wire is M_i,(1≤i≤p)：

For a multi-turn inductor, when the number of turns p is even, the common-mode mutual inductance can be expressed as:

the sign of the front of the formula is determined by the direction of current flowing through the symmetrical structure inductor. When M is₁≈M₂≈…≈M_pWhen M is in contact with_odd0. Therefore, the common-mode mutual inductance M of the actual p-turn (p is an even number) inductor structure and the inductor with any symmetrical structure_oddWill exhibit a ratio

Much less perceptual.

For a multi-turn inductor, when the number of turns p is odd, the common-mode mutual inductance can be expressed as:

the sign of the front of the formula is determined by the direction of current flowing through the symmetrical structure inductor. When M is₁≈M₂≈…≈M_pWhen M is in contact with_odd≈±2jωM_p. When the number of turns p is sufficiently large, the common mode is mutually induced_oddWill also exhibit a ratio

Much less perceptual.

Therefore, when the inductor structure is applied to the mutual inductance network, the mutual inductance of the inductor structure and the common-mode current of other inductors in the mutual inductance network can be reduced under the condition of keeping the characteristics (differential mode inductance enhancement and common-mode inductance elimination) of the inductor structure, and the coupling of the common-mode current in the mutual inductance network is effectively inhibited. In other alternative examples, each turn of the inductor may also comprise two symmetrical metal wires with different inductance values.

Therefore, to ensure that the Vmod node signal is passed to transistor M1, the signal at the gate of M2 is free of amplitude and phase distortion, we introduce the inductive structure exemplified by fig. 8 into the 0dB common mode amplitude modulator structure proposed by the present invention. The B coil of the transformer T1 shown in fig. 1 adopts an inductance structure exemplified by fig. 8, the coil can be an inductance coil with any number of turns, and the midpoint of the innermost coil (e.g., T1 in fig. 8) is connected to the Vmod node in fig. 1; of the two ends of the outermost circle, one end (as indicated by point b1 in fig. 8) is connected to the M1_ G node in fig. 1, and the other end (as indicated by point b2 in fig. 8) is connected to the M2_ G node in fig. 1. The a coil of the transformer T1 in fig. 1 may employ any symmetrical configuration of inductance.

Fig. 9 shows an alternative structure of a 0dB power back-off common mode amplitude modulator structure. Wherein the input carrier signal becomes a single-ended signal, one end of the a coil of the transformer T1 is connected to the input port, and the other end is ac-coupled to ground through the large capacitor Cp1 or directly connected to ground. Thus, the transformer T1 acts as a balun and can convert a single-ended carrier signal into a differential carrier signal for output. The other structure in fig. 9 is identical to that in fig. 1.

Fig. 10 shows another alternative structure for a 0dB power back-off common mode amplitude modulator structure. The transformer T1 in fig. 1 is replaced by an inductor L1 in the embodiment in fig. 10, L1 adopts an inductor structure (no limitation of the number of turns) exemplified in fig. 8, a center tap of L1 is connected to a node Vmod, and two ends of L1 are respectively connected to nodes M1_ G and M2_ G (gates of transistors M1 and M2). The differential input signals are directly input from the nodes M1_ G and M2_ G. The other structure in fig. 10 is identical to that in fig. 1.

In other alternatives, similar modulation control functions can be achieved by replacing the transistors M1, M2 with two transistors in the 0dB power back-off amplitude modulator structures shown in fig. 1, 9, and 10.

Based on the 0dB power back-off amplitude modulator structure proposed by the present invention, the present invention further proposes a quadrature amplitude modulation transmitter structure with 0dB power back-off, as shown in fig. 11. The transmitter structure comprises four 0dB power back-off amplitude modulators Ip, In, Qp and Qn with the same structure, an adjustable impedance module X, a transformer T2, a band-pass filter and an antenna. Each 0dB power back-off amplitude modulator is identical in structure, and the embodiment shown in fig. 1, or fig. 9, or fig. 10 is adopted. Optionally, a pair of cross-coupling capacitors Cc1 and Cc2 and a preamplifier (not shown) are added on the basis of the original structure. In other examples, the connection relationship and the control method when the transistors M1 and M2 are replaced by triodes are similar, and are not described in detail.

In the example of fig. 11, each 0dB power back-off amplitude modulator uses the embodiment of fig. 9 in which the input is a single-ended carrier signal, and the specific connection relationship is as follows:

port C is connected directly to one end of the a coil of transformer T1, or port C is connected to the input of a preamplifier, the output of which is connected to one end of the a coil of transformer T1; the other end of the a coil of the transformer T1 is connected to ground through an ac coupling capacitor Cp 1. Both ends of the B coil of the transformer T1 are connected to nodes M1_ G and M2_ G, respectively. The gate and drain of transistor M1 are connected to nodes M1_ G and M1_ D, respectively. The gate and drain of transistor M2 are connected to nodes M2_ G and M2_ D, respectively. The two ends of the capacitor Cc1 are connected to nodes M1_ G and M2_ D, respectively. The two ends of the capacitor Cc2 are connected to nodes M2_ G and M1_ D, respectively. The two ends of the switch SW1 are connected to nodes M1_ G and M2_ G, respectively. The control line of switch SW1 is connected to port S. Two ends of the first adjustable impedance module are respectively connected with nodes M1_ G and M2_ G.

The control line of the first adjustable impedance block and the level shifter is 2^m+1-1 bus line, the control line being connected to port BB. Where m is related to the type of QAM (quadrature amplitude modulation): for QPSK (quadrature phase shift keying modulation), m is 0; for 16QAM (quadrature amplitude modulation), m is 1; for 64QAM (quadrature amplitude modulation), m is 2; and so on to 4ⁱAnd m-i-1 corresponding to QAM. Level shifters share 2^m+1-1 routeSimulating the DC level, and connecting to port V. The output port of the level shifter is connected to the center tap of the B coil of the transformer T1.

The system connection of the transmitter is as follows:

the ports S of the four 0dB power back-off amplitude modulators are respectively represented as: SIp, SIn, SQp and SQn. Ports C of the four 0dB power back-off amplitude modulators are respectively represented as: CIp, CIn, CQp and CQn. The ports BB of the four 0dB power back-off amplitude modulators are respectively represented as: BIp, BIn, BQp and BQn. The ports V of the four 0dB power backspacing amplitude modulators are connected together and share 2 of the input^m+1The-1 way analog dc level, and therefore still denoted V.

The nodes M1_ D of the four 0dB power back-off amplitude modulators are all connected to node outp. The nodes M2_ D of the four 0dB power back-off amplitude modulators are all connected to node outn. The two ends of the adjustable impedance module X are respectively connected with nodes outp and outn, and the impedance of the adjustable impedance module X is represented by (4)^m+2^m) And/2 control line BX. The two ends of the B coil of the transformer T2 are connected to the nodes outp and outn, respectively. The center tap of the coil B of the transformer T2 is connected with a power supply VDD. One end of the a coil of the transformer T2 is grounded, and the other end is connected to the input end of the band pass filter. The output end of the band-pass filter is connected with the antenna.

The transmitter is implemented as follows:

the ports CIp, CIn, CQp, CQn input carrier sinusoids of the same amplitude but with phases of 0 degrees, 180 degrees, 90 degrees and 270 degrees, respectively. The four-phase sinusoidal signal is amplified by pre-amplifiers In Ip, In, Qp and Qn respectively and then input to a 0dB power back-off amplitude modulator for amplitude modulation. Data of the four amplitude modulators are superposed at nodes outp and outn, differential signals are converted into single-ended signals through a balun formed by a transformer T2, then the single-ended signals are input to a band-pass filter for filtering, and finally the single-ended signals are output from an antenna. The amplitude modulators In Ip, In, Qp, Qn are controlled using different data control lines SIp, SIn, SQp, SQn and BIp, BIn, BQp, BQn.

Since the four 0dB power back-off amplitude modulators respectively input the carrier sinusoidal signals of 4 phase signals (0 degree, 180 degree, 90 degree and 270 degree), the control signals input through the ports S and BB can respectively control the four 0dB power back-off amplitude modulators to perform amplitude modulation on the carrier sinusoidal signals of 4 phases.

Taking the control of the data control line SIp and the data control line BIp to the 0dB power back-off amplitude modulator Ip as an example: when the switch connecting nodes M1_ G and M2_ G controlled by the SIp is turned on and the output of the level shifter is grounded, the gate dc potentials of the transistor M1 and the transistor M2 in Ip are 0 at this time, and the carrier signals of the gate differences are cancelled out. Thus, the transistor M1 and the transistor M2 are in a fully off state, where the amplitude of the 0 degree carrier sinusoidal signal output by the 0dB power back-off amplitude modulator Ip is 0. When the switches of the connection nodes M1_ G and M2_ G controlled by the SIp are turned on and the output of the level shifter is not grounded, the output potential of the level shifter is determined by the data control line BIp, and the output impedance of the adjustable impedance 1 in Ip is correspondingly controlled by the data control line BIp. Thus, the amplification gain of the differential carrier signal is controlled by the transistor M1 and the transistor M2, and the amplitude of the differential carrier signal is modulated. The control principle of the other 3 0dB power back-off amplitude modulators In, Qp, Qn can be analogized. The four 0dB power back-off amplitude modulators synthesize QAM modulated signals according to the QAM signal vector synthesis approach described below.

Fig. 13 shows a conventional QAM signal vector composition scheme, and fig. 12 shows a QAM signal vector composition scheme according to the present invention. Taking 16QAM as an example, other QAM types may be analogized. QAM is a kind of vector modulation, and the basic vectors are two vectors in the I direction and the Q direction in the figure. And then amplitude modulation is carried out on the two vectors, and the modulated vectors are superposed to obtain a constellation diagram. The QAM constellation diagram of the invention can be obtained by rotating (2N +1) N ∈ N by 45 degrees anticlockwise through the traditional QAM constellation diagram. The novel QAM constellation diagram has higher power synthesis efficiency.

The reasons for the following analyses: whether based on a transistor structure or a triode structure, which outputs a carrier signal (vector) of a specific amplitude, the output stage of which can be represented by fig. 14, i.e. a current source outputting an alternating current I at the carrier frequency_DSA resistance value of R in parallel with the current source_loadThe resistance of (2). For conventional QAM signalsThe maximum power point of the constellation diagram is four diagonal points (1, 3,5 and 7 points in figure 13). Taking the power synthesis of point 5 as an example, the vector of point 5 is synthesized by two vectors in the I direction and the Q direction, and synthesized by the output signals of the two output stages shown in FIG. 14, and the current of the output stage in the I direction and the output stage in the Q direction are equal to each other, I is the position of point 5 in the constellation diagram_DS0. The currents of the two output stages are superposed at an output node to obtain a current with the amplitude of

The current of (2). According to the position of the No. 5 point in the constellation diagram, the resistance of the I-direction output stage and the Q-direction output stage is equal to R_load0. The resistors of the two output stages are connected in parallel at an output node to obtain a resistance value R_load0A resistance of/2. Therefore, from the power calculation formula:

P＝I²R

it can be known that the power corresponding to node 5 is I_DS0 ²R_load0. If the I-direction output stage or the Q-direction output stage works independently, the corresponding power is I_DS0 ²R_load0. Therefore, node 5 loses I in power synthesis_DS0 ²R_load0I.e., its dc-to-ac conversion efficiency becomes 50% of the original. It can be proved that

nodes

1,3 and 7 also have the same characteristics, and similarly, in all kinds of traditional QAM signal vector synthesis modes, the efficiency of the four-corner node is reduced by 50% during power synthesis. And the four-corner node is the highest power point in the traditional QAM signal vector synthesis mode, which means that the power efficiency of other points in the constellation diagram is also reduced on the premise of ensuring the linearity of the constellation diagram.

In the QAM signal vector combining scheme of the present invention (for ease of understanding, 16QAM is used as an example for illustration, see fig. 12, and so on for other kinds of QAM modulation), the vector of node No. 5 is generated from only one vector in the Q direction, and from one output signal of the output stage shown in fig. 14, and the power is I_DS0 ²R_load0. No power loss exists in the whole process, so that the power efficiency ratio is higher than that of No. 5 section in FIG. 13The power efficiency of the spot is doubled. The

nodes

1,3 and 7 can be proved to have the same characteristics, and similarly, in all kinds of new QAM signal vector synthesis modes, the efficiency of the four-corner node is doubled compared with that of the traditional QAM signal vector synthesis mode in the power synthesis process. It can be proved that the power efficiency of all nodes in the QAM signal vector synthesis scheme of the present invention is higher than the power efficiency of the corresponding nodes in the conventional QAM signal vector synthesis scheme.

The control mode for 16QAM modulation is as follows, and other QAM modulations can be analogized by the same way: the amplitude and phase of the modulated signal can be represented by a point on a constellation diagram, wherein the angle between the point and the line connecting the origin represents the phase of the carrier frequency of the modulated signal, and the distance between the point and the line connecting the origin represents the amplitude of the carrier frequency of the modulated signal. For 16QAM, m is 1. Therefore, the number of control lines of the ports BIp, BIn, BQp, BQn is 3. Port V has 3 different analog dc levels in total. The number of control lines of the port BX is also 3. A digital level 1 in the control line indicates that its corresponding switch is on, and a digital level 0 indicates that its corresponding switch is off. The 16 points on the 16QAM constellation have been marked with reference numbers. The following table shows the digital levels on the corresponding control lines when implementing constellation positions No. 1 to No. 16.

	BIp[1：3]	BIn[1：3]	BQp[1：3]	BQn[1：3]	SIp	SIn	SQp	SQn	BX[1：3]
										1	001	000	000	000	0	1	1	1	100
2	100	000	000	000	0	1	1	1	010
										3	000	001	000	000	1	0	1	1	100
4	000	100	000	000	1	0	1	1	010
										5	000	000	001	000	1	1	0	1	100
6	000	000	100	000	1	1	0	1	010
										7	000	000	000	001	1	1	1	0	100
8	000	000	000	100	1	1	1	0	010
										9	010	000	100	000	0	1	0	1	001
10	100	000	010	000	0	1	0	1	001
										11	000	010	100	000	1	0	0	1	001
12	000	100	010	000	1	0	0	1	001
										13	010	000	000	100	0	1	1	0	001
14	100	000	000	010	0	1	1	0	001
										15	000	010	000	100	1	0	1	0	001
16	000	100	000	010	1	0	1	0	001

In the case of nos. 1 and 2, the SIn, SQp, and SQn control switches are all turned on except for the SIp control switch. This causes the transistors M1, M2 In, Qp, Qn to all be In the off state, no dc power is consumed, and no carrier signal is output. Meanwhile, the drain impedances of the transistors M1, M2 In, Qp, Qn exhibit high-impedance characteristics. So that the impedance characteristics at the transmitter nodes outp and outn are mainly determined by the drain impedances of the transistors M1, M2 in Ip. The case of high amplitude No. 1 corresponds to BIp [ 1: 3] control level is 001; the case of low amplitude No. 2 corresponds to BIp [ 1: 3] is 100. In both cases the 0dB power back-off transmitter output power of the present invention is at the state of saturated output power and the power added efficiency is at the peak. The cases of

numbers

3, 4, 5, 6, 7, 8 can be analogized in turn.

For cases 9, 10: these two modulated signals are the result of vector synthesis of the signal output via Ip and the signal output via Qp. Thus the switches controlled by SIp and SQp are open and the switches controlled by SIn and SQn are closed. This causes the transistors M1, M2 In, Qn to all be In the off state, no dc power is consumed, and no carrier signal is output. Meanwhile, the drain impedances of the transistors M1 and M2 In and Qn exhibit high-impedance characteristics. So that the impedance characteristics at the transmitter nodes outp and outn are mainly determined by the drain impedances of the transistors M1, M2 in Ip and Qp. Case No. 9 corresponds to BIp [ 1: 3] is 010, BQp [ 1: 3] is 100; case No. 10 corresponds to BIp [ 1: 3] is 100, BQp [ 1: 3] is 010. In both cases, the output power of the 0dB power back-off transmitter of the present invention is in the state of saturated output power, but due to the energy loss of IQ vector superposition, the power added efficiency will drop to some extent, but will still remain more than half of the peak value of the power added efficiency. The cases of 11, 12, 13, 14, 15, 16 can be analogized in turn.

In order to keep the transmitter output impedance matching constant, the impedances at nodes outp and outn are kept constant by means of an adjustable impedance X. For the cases of No. 1, No. 3, No. 5, No. 7, although the phases of the signals at the nodes outp and outn are different, the impedance characteristics at that point are the same, and therefore the control word BX [ 1: 3] are uniformly set to 100. For the cases of nos. 2, 4, 6, 8, although the phases of the signals at the nodes outp and outn are different, the impedance characteristics at that point are the same, and therefore the control word BX [ 1: 3] are set to 010 collectively. For the cases of 9, 10, 11, 12, 13, 14, 15, 16, although the phases of the signals at the nodes outp and outn are different, the impedance characteristics at that point are the same, and thus the control word BX [ 1: 3] are set to 001.

It should be noted that the above-mentioned control word codes are not unique, and all control modes for controlling the 0dB power back-off amplitude modulator to perform vector synthesis according to the distribution of the QAM constellation diagram shown in fig. 12 should be within the protection scope of the present invention.

While the foregoing describes an embodiment of forming an qam transmitter with the structure shown in fig. 9, the device connection, the common port correspondence relationship, the control method, and the like of forming the transmitter with four 0dB power back-off common mode amplitude modulators with the same structure as shown in fig. 1 or fig. 10 can be adjusted by those skilled in the art, and thus, the details are not repeated.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims

1. A0 dB power back-off common mode amplitude modulator is characterized in that,

2. The 0dB power back-off common mode amplitude modulator of claim 1,

the connection mode of connecting two ends of the coil a of the first transformer T1 to the carrier signal input port to receive the sinusoidal signal of the differential carrier frequency is replaced by a connection mode of alternating-current coupling one end of the coil a of the first transformer T1 to the ground through the capacitor Cp1 or directly connecting the coil a to the ground, and connecting the other end of the coil a to the carrier signal input port to receive the single-ended carrier signal, and converting the single-ended carrier signal into the differential carrier signal through the coil a and the coil B of the first transformer T1 to be output.

3. The 0dB power back-off common mode amplitude modulator of claim 1,

replacing the first transformer T1 with an inductor L1, wherein two ends of the inductor L1 are connected to a carrier signal input port to obtain a sinusoidal signal of a differential carrier frequency, and the sinusoidal signal is applied to gates of a transistor M1 and a transistor M2 which are respectively connected to two ends of the inductor L1;

4. The common mode amplitude modulator with 0dB power back-off as claimed in any one of claims 1-3,

a circuit structure capable of conducting a dc signal and providing impedance for an ac signal is disposed between the drains of the transistor M1 and the transistor M2, and dc voltage and current are provided to the drains of the transistor M1 and the transistor M2.

5. The 0dB power back-off common mode amplitude modulator of any one of claims 1-3,

an electric control switch is arranged between the grid electrodes of the transistor M1 and the transistor M2;

6. The 0dB power back-off common mode amplitude modulator of any one of claims 1-3,

the 0dB power backspacing common mode amplitude modulator also comprises any one or any combination of a level shifter, a first adjustable impedance module and a second adjustable impedance module, so that under the condition of any input data, the phase difference between the carrier signal of the differential output port and the carrier signal of the carrier signal input port is the same, and the impedance of the differential output port is kept unchanged;

the level shifter applies an amplitude modulation signal to a node Vmod connected with the level shifter, adjusts the voltage value of the node Vmod, changes the gains of the transistors M1 and M2, and performs amplitude modulation on a carrier signal;

the first adjustable impedance module is connected between the gates of the transistor M1 and the transistor M2; the second adjustable impedance module is connected between the drain of the transistor M1 and the drain of the transistor M2; and compensating the distortion of the phase and the amplitude distortion of the carrier signal through the impedance provided by the first adjustable impedance module and/or the second adjustable impedance module.

7. The 0dB power back-off common mode amplitude modulator of claim 6,

the first input port V [ 1: n ] connecting n different analog DC levels;

the second input port CB [ 1: n ] are connected to n first data control lines, and n switches controlled by the n first data control lines control the first input port V [ 1: n ] whether the applied DC level is passed to an output port of the level shifter;

8. The 0dB power back-off common mode amplitude modulator of claim 7,

the first adjustable impedance module is provided with n first impedance adjusting values; only one of the first impedance adjustment values is applied to the gates of the transistor M1 and the transistor M2 at any time through the control of the n first data control lines;

9. The 0dB power back-off common mode amplitude modulator of any one of claims 1-3,

correspondingly replacing the transistor M1 with a first triode, and correspondingly replacing the grid electrode, the source electrode and the drain electrode of the transistor M1 with the base electrode, the emitter electrode and the collector electrode of the first triode;

10. The 0dB power back-off common mode amplitude modulator of claim 4,

11. The 0dB power back-off common mode amplitude modulator of claim 5,

12. The 0dB power back-off common mode amplitude modulator of claim 6,

13. The 0dB power back-off common mode amplitude modulator of claim 7,

14. The 0dB power back-off common mode amplitude modulator of claim 8,

15. A quadrature amplitude modulation transmitter comprising four identically constructed 0dB power back-off amplitude modulators of any of claims 1-14, designated Ip, In, Qp, and Qn;

the quadrature amplitude modulation transmitter further comprises: the third adjustable impedance module X, the second transformer T2, the band-pass filter and the antenna are shared by the four 0dB power backspacing amplitude modulators Ip, In, Qp and Qn;

two ends of the third adjustable impedance module X are respectively connected with nodes outp and outn; both ends of the B coil of the second transformer T2 are connected to nodes outp and outn, respectively; the center tap of the coil B of the second transformer T2 is connected with a power supply VDD; one end of the coil A of the second transformer T2 is grounded, and the other end is connected with the input end of the band-pass filter; the output end of the band-pass filter is connected with the antenna.

16. The quadrature amplitude modulation transmitter of claim 15,

the impedance of the third adjustable impedance module X is composed of (4)^m+2^m) The/2 control line BX controls to keep the impedance of the nodes outp and outn constant under the two control modes; the two types of control modes comprise:

when the switch between the grids of the transistors M1 and M2 in each 0dB power back-off amplitude modulator is disconnected and the level converter in the 0dB power back-off amplitude modulator outputs a certain non-0 control level under the state that different amplitude control levels are input, the switches between the grids of the transistors M1 and M2 of the other three 0dB power back-off amplitude modulators are switched on and the outputs of the level converters corresponding to the transistors M1 and M2 are grounded; then the impedance characteristics at the nodes outp and outn of the quadrature amplitude modulation transmitter, determined by the drain impedances of the transistors M1, M2 in this 0dB power back-off amplitude modulator with the switches open, are such that the output power of the transmitter is at a state of saturated output power and the power added efficiency is at a peak; and the number of the first and second groups,

dividing four groups by 0dB power backspacing amplitude modulators Ip and Qp, In and Qp, Ip and Qn, In and Qn, and sequentially enabling the switches between the grids of the transistors M1 and M2 In two 0dB power backspacing amplitude modulators In each group to be switched off and the level converter In the 0dB power backspacing amplitude modulator outputs a certain non-0 control level when the switches between the grids of the transistors M1 and M2 In the other two 0dB power backspacing amplitude modulators are switched on and the outputs of the corresponding level converters are grounded respectively under the state that different amplitude control levels are input; then the impedance characteristics at the nodes outp and outn of the quadrature amplitude modulation transmitter, determined by the drain impedances of the transistors M1, M2 in the two 0dB power back-off amplitude modulators with the switches off, are jointly such that the output power of the transmitter is in a state of saturated output power and the power added efficiency is lower than the peak value and higher than half of the peak value;

two ends of the first adjustable impedance module of each 0dB power back-off amplitude modulator are respectively connected with nodes M1_ G and M2_ G in the 0dB power back-off amplitude modulator; the level shifter of each of said 0dB power back-off amplitude modulators is connected to node Vmod for applying an amplitude modulated signal; the control lines of the first adjustable impedance module and the level shifter both comprise 2^m+1-1 wire harness, connectionPort BB to the 0dB power back-off amplitude modulator; the level shifter is also connected to a port V common to four 0dB power back-off amplitude modulators, receiving an input of 2^m+1-1 analog dc level;

wherein the value of m is determined by the type of QAM: m ═ 0 for QPSK; m is 1 corresponding to 16 QAM; m is 2 for 64QAM, and so on to 4¹M-i-1 corresponding to QAM;

when the data control line corresponding to the port S in each 0dB power back-off amplitude modulator controls the switch between the connection nodes M1_ G and M2_ G in the 0dB power back-off amplitude modulator to be conducted and the output of the level shifter is grounded, the direct current potentials of the grid electrodes of the transistor M1 and the transistor M2 of the 0dB power back-off amplitude modulator are 0, the carrier signals of grid electrode difference are mutually cancelled, and the amplitude of the carrier signal output by the 0dB power back-off amplitude modulator is 0;

alternatively, when the data control line corresponding to the port S in each 0dB power back-off amplitude modulator controls the switch between the connection nodes M1_ G and M2_ G in the 0dB power back-off amplitude modulator to be off and the output of the level shifter is not grounded, the output potential of the level shifter is determined by the data control line corresponding to the port BB in the 0dB power back-off amplitude modulator, and the output impedance of the first adjustable impedance in the 0dB power back-off amplitude modulator is controlled by the data control line corresponding to the port BB, thereby realizing the amplification gain control of the differential carrier signal by the transistor M1 and the transistor M2 in the 0dB power back-off amplitude modulator, and the compensation of the phase and amplitude distortion of the carrier signal, and further realizing the amplitude modulation of the differential carrier signal.

17. A method for synthesizing a qam signal, which is applied to the qam transmitter according to claim 15 or 16;

the distribution of points in the constellation map matches two types of control patterns, including:

the points in the constellation do not lie on the coordinate axis in the I or Q direction: dividing four groups by 0dB power backspacing amplitude modulators Ip and Qp, In and Qp, Ip and Qn, In and Qn, and sequentially enabling the switches between the grids of the transistors M1 and M2 In two 0dB power backspacing amplitude modulators In each group to be switched off and the level converter In the 0dB power backspacing amplitude modulator outputs a certain non-0 control level when the switches between the grids of the transistors M1 and M2 In the other two 0dB power backspacing amplitude modulators are switched on and the outputs of the corresponding level converters are grounded respectively under the state that different amplitude control levels are input; the impedance characteristics at the nodes outp and outn of the quadrature amplitude modulation transmitter are then determined by the drain impedances of the transistors M1, M2 in the two 0dB power back-off amplitude modulators with the switches off, such that the output power of the transmitter is in a state of saturated output power and the power added efficiency is lower than the peak value and higher than half the peak value.