CN107994017A - SiGe material CMOS device - Google Patents
SiGe material CMOS device Download PDFInfo
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- CN107994017A CN107994017A CN201711244586.6A CN201711244586A CN107994017A CN 107994017 A CN107994017 A CN 107994017A CN 201711244586 A CN201711244586 A CN 201711244586A CN 107994017 A CN107994017 A CN 107994017A
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- 239000000463 material Substances 0.000 title claims abstract description 40
- 229910000577 Silicon-germanium Inorganic materials 0.000 title 1
- 229910006990 Si1-xGex Inorganic materials 0.000 claims abstract description 59
- 229910007020 Si1−xGex Inorganic materials 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 43
- 230000008569 process Effects 0.000 claims abstract description 23
- 239000011800 void material Substances 0.000 claims abstract description 19
- 238000002161 passivation Methods 0.000 claims abstract description 6
- 238000002425 crystallisation Methods 0.000 claims description 11
- 230000008025 crystallization Effects 0.000 claims description 10
- 241000931526 Acer campestre Species 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000001953 recrystallisation Methods 0.000 claims description 3
- 230000037230 mobility Effects 0.000 abstract description 10
- 230000008901 benefit Effects 0.000 abstract description 5
- 238000002360 preparation method Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 72
- 229910052681 coesite Inorganic materials 0.000 description 11
- 229910052906 cristobalite Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052682 stishovite Inorganic materials 0.000 description 11
- 229910052905 tridymite Inorganic materials 0.000 description 11
- 239000011241 protective layer Substances 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000005499 laser crystallization Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 241000033695 Sige Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003902 lesion Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of sige material cmos device, including：Si1‑xGex/ Si void substrate (101)；Si1‑xGexChannel layer (102), is arranged at the Si1‑xGexOn/Si void substrate (101)；Dielectric layer (103), is arranged at the Si1‑xGexOn channel layer (102)；Isolated area (104), is arranged at the Si1‑xGexChannel layer (102) and the dielectric layer (103) are internal；N well regions (105), are arranged at the Si of the isolated area (104) side1‑xGexIn channel layer (102)；PMOS area (106) and NMOS area (107), are respectively arranged at the both sides of the isolated area (104)；Passivation layer (108), is arranged on the dielectric layer (103).Cmos device provided by the invention is with Si1‑xGexMaterial is cmos device raceway groove, its NMOS interfacial characteristics is good, and carrier mobility is high, and PMOS carrier mobilities are significantly higher than Si devices, and device operating rate is high, and frequency characteristic is good；And its preparation process has fairly obvious advantage with existing Si process compatibles in terms of technique manufactures, reduces cost.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of sige material cmos device.
Background technology
Since integrated circuit comes out, always with Moore's Law high speed development forward, it can be accommodated on one piece of integrated circuit
Transistor size double within every 18 months, one times of performance boost, but price reduction half.At present, Moore's Law is still sent out
Wave and act on, instruct integrated circuit to advance.However as the fast development of microelectric technique, device feature size constantly contracts
Small, circuit speed is constantly accelerated, static leakage, and the physics limit such as short-channel effect, mobil-ity degradation, power density increase makes device
Part performance constantly deteriorates, its physics of the gradual convergence of integrated circuit and technological limits, traditional silicon-based devices and technique are gradually shown
Its shortcomings and deficiencies so that Moore's Law can not continue development and go down.
Integrated circuit is mainly made of CMOS, and CMOS is made of complementary NMOS and PMOS.The speed of integrated circuit
It is closely bound up with the carrier mobility of MOS device, and the size of device and the area of integrated circuit are closely bound up, how to carry
The channel mobility of high MOS device, the size for reducing device are integrated circuit development institute urgent problems.In order to solve core
The problem of piece speed and area, introduce the crucial solution party that new high mobility material is current large scale integrated circuit research
Case.
Therefore.Preparation volume smaller, device drive ability are stronger, and device operating rate and circuit work frequency are faster
Cmos device becomes more and more important.
The content of the invention
In order to improve the performance of cmos device, the present invention provides a kind of sige material cmos device；The invention solves
Technical problem be achieved through the following technical solutions：
The embodiment provides a kind of sige material cmos device, including：
Si1-xGex/ Si void substrate 101；
Si1-xGexChannel layer 102, is arranged at the Si1-xGexOn/Si void substrate 101；
Dielectric layer 103, is arranged at the Si1-xGexOn channel layer 102；
Isolated area 104, is arranged at the Si1-xGexInside channel layer 102 and the dielectric layer 103；
N well regions 105, are arranged at the Si of 104 side of isolated area1-xGexIn channel layer 102；
PMOS area 106 and NMOS area 107, are respectively arranged at the both sides of the isolated area 104；
Passivation layer 108, is arranged on the dielectric layer 103.
In one embodiment of the invention, the Si1-xGex/ Si void substrate 101 includes Si substrates 1011 from lower to upper
And Si1-xGexEpitaxial layer 1012, using laser, crystallization process handles the Si substrates 1011 and the Si again1-xGexEpitaxial layer
The Si is formed after 10121-xGex/ Si void substrate 101.
In one embodiment of the invention, crystallization process is to irradiate the Si substrates 1011 using laser to the laser again
On the Si1-xGexEpitaxial layer 1012, makes the Si1-xGexThe fusing recrystallization of epitaxial layer 1012, wherein, optical maser wavelength is
795nm, laser power density 2.85kW/cm2, laser spot size 10mm × 1mm, laser traverse speed 20mm/s.
In one embodiment of the invention, the Si1-xGexX value ranges are 0.7~0.9 in epitaxial layer.
In one embodiment of the invention, the Si1-xGexThe thickness of epitaxial layer is 450~500nm.
In one embodiment of the invention, the Si1-xGexChannel layer 102 is p-type Si1-xGexChannel layer, doping concentration
For 1 × 1016~5 × 1016cm-3。
In one embodiment of the invention, the Si1-xGexThe thickness of channel layer 102 is 900~950nm.
In one embodiment of the invention, the PMOS area 106 include PMOS source area, PMOS drain regions, PMOS grids,
PMOS source region electrode and PMOS drain regions electrode；Wherein, the PMOS source area and the PMOS drain regions are arranged at the N well regions 105
Interior, the PMOS grids are arranged on the N well regions 105.
In one embodiment of the invention, the NMOS area 107 include NMOS source regions, NMOS drain regions, NMOS gate,
NMOS source regions electrode and NMOS drain regions electrode；Wherein, the NMOS source regions and the NMOS drain regions are arranged at the Si1-xGexDitch
In channel layer 102, the NMOS gate is arranged at the Si1-xGexOn channel layer 102.
Compared with prior art, the invention has the advantages that：
1st, the present invention is with Si1-xGexMaterial is cmos device raceway groove, its NMOS interfacial characteristics is good, and carrier mobility is high,
PMOS carrier mobilities are significantly higher than Si devices, and device operating rate is high, and frequency characteristic is good；
2nd, Si provided by the invention1-xGex/ Si void substrate can effectively be reduced in the case where not increasing substrate thickness
Si1-xGexThe dislocation density and surface roughness of/Si void substrates；
3rd, cmos device provided by the invention, preparation process with existing Si process compatibles, in technique manufacture, reduce cost
Aspect has fairly obvious advantage.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
By the detailed description below with reference to attached drawing, other side of the invention and feature become obvious.But it should know
Road, which is only the purpose design explained, not as the restriction of the scope of the present invention, this is because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale attached drawing, they only try hard to concept
Ground illustrates structure and flow described herein.
Fig. 1 is a kind of sige material cmos device structure diagram provided in an embodiment of the present invention；
Fig. 2 a- Fig. 2 x are a kind of preparation technology flow chart of sige material cmos device provided in an embodiment of the present invention；
Fig. 3 is a kind of laser provided in an embodiment of the present invention brilliant process schematic diagram again；
Fig. 4 is a kind of laser provided in an embodiment of the present invention brilliant process unit schematic diagram again.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of sige material cmos device structure diagram provided in an embodiment of the present invention, including：
Si1-xGex/ Si void substrate 101；
Si1-xGexChannel layer 102, is arranged at the Si1-xGexOn/Si void substrate 101；
Dielectric layer 103, is arranged at the Si1-xGexOn channel layer 102；
Isolated area 104, is arranged at the Si1-xGexInside channel layer 102 and the dielectric layer 103；
N well regions 105, are arranged at the Si of 104 side of isolated area1-xGexIn channel layer 102；
PMOS area 106 and NMOS area 107, are respectively arranged at the both sides of the isolated area 104；
Passivation layer 108, is arranged on the dielectric layer 103.
Further, the Si1-xGex/ Si void substrate 101 includes Si substrates 1011 and Si from lower to upper1-xGexEpitaxial layer
1012, using laser, crystallization process handles the Si substrates 1011 and the Si again1-xGexDescribed in being formed after epitaxial layer 1012
Si1-xGex/ Si void substrate 101.
Specifically, crystallization process is the Si irradiated using laser on the Si substrates 1011 to the laser again1-xGex
Epitaxial layer 1012, makes the Si1-xGexThe fusing recrystallization of epitaxial layer 1012, wherein, optical maser wavelength 795nm, laser power is close
Spend for 2.85kW/cm2, laser spot size 10mm × 1mm, laser traverse speed 20mm/s.
Preferably, the Si1-xGexX value ranges are 0.7~0.9 in epitaxial layer；
Preferably, the Si1-xGexThe thickness of epitaxial layer is 450~500nm.
Wherein, the Si1-xGexChannel layer 102 is p-type Si1-xGexChannel layer, doping concentration are 1 × 1016~5 ×
1016cm-3。
Preferably, the Si1-xGexThe thickness of channel layer 102 is 900~950nm.
Specifically, the PMOS area 106 includes PMOS source area, PMOS drain regions, PMOS grids, the PMOS source region electrode
And PMOS drain regions electrode；Wherein, the PMOS source area and the PMOS drain regions are arranged in the N well regions 105, described
PMOS grids are arranged on the N well regions 105.
Specifically, the NMOS area 107 includes NMOS source regions, NMOS drain regions, NMOS gate, the NMOS source regions electrode
And NMOS drain regions electrode；Wherein, the NMOS source regions and the NMOS drain regions are arranged at the Si1-xGexChannel layer 102
Interior, the NMOS gate is arranged at the Si1-xGexOn channel layer 102.
Cmos device provided in this embodiment has carrier mobility height, device compared with traditional Si based CMOS devices
The advantages that operating rate is high, and frequency characteristic is good, and device interfaces characteristic is good, so as to greatly improve the working frequency of integrated circuit,
The advantages that reducing the physical size of integrated circuit device, and then reducing the area of integrated circuit.
Embodiment two
The present embodiment is described in detail the preparation process of the cmos device of the present invention on the basis of above-described embodiment
It is as follows.
Refer to Fig. 2 a- Fig. 2 x, Fig. 2 a- Fig. 2 x is a kind of system of sige material cmos device provided in an embodiment of the present invention
Standby process flow chart, includes the following steps：
S101, such as Fig. 2 a, choose single crystal Si substrate 001；
Preferably, the thickness of Si substrates 001 is 2 μm；
S102, using RCA methods cleaning Si substrates 001, then with 10% hydrofluoric acid clean, remove 001 table of Si substrates
Face oxide layer；
S103, such as Fig. 2 b, are 99.999% by purity using the method for magnetron sputtering at a temperature of 400 DEG C~500 DEG C
Intrinsic Si1-xGexTarget material sputtering is grown on Si substrates 001, forms high-Ge component Si1-xGexEpitaxial layer 002, Si1-xGex
The thickness of epitaxial layer 002 is 450~500nm；
Preferably, the Si1-xGexX values are 0.89 in epitaxial layer 002；
Wherein, the operation pressure of the magnetically controlled sputter method is 1.5 × 10-3Mb, growth rate 5nm/min.
S104, such as Fig. 2 c, using CVD techniques, in Si0.11Ge0.89Epitaxial layer grows SiO on 002 surface2Protective layer 003,
SiO2The thickness of protective layer 003 is 100nm~160nm；
Preferably, SiO2The thickness of protective layer 003 is 130nm；
S105, laser crystallization Si again0.11Ge0.89Epitaxial layer 002；Wherein, laser again crystallization process before processing, it is necessary to elder generation
By SiO2Protective layer 003, Si0.11Ge0.89The whole substrate material of epitaxial layer 002 and Si substrates 001 is heated to 600 DEG C~650
DEG C, then continuous laser irradiates SiO2Protective layer 003, Si0.11Ge0.89The whole substrate material of epitaxial layer 002 and Si substrates 001,
Wherein, optical maser wavelength 795nm, laser power density 2.85kW/cm2, laser spot size 10mm × 1mm, laser movement
Speed is 20mm/s；
Specifically, Fig. 3 is referred to, Fig. 3 is a kind of laser provided in an embodiment of the present invention brilliant process schematic diagram again, is led to
Cross the high-Ge component Si on superlaser irradiation Si substrates1-xGexEpi-layer surface, recrystallizes its rapid melting；Laser is brilliant again
Change in process treatment process, the phase transformation twice of solid-liquid-solid phase occurs for epitaxial layer, passes through laterally release high-Ge component Si1- xGexMisfit dislocation between Si, can significant increase high-Ge component Si/Si1-xGexThe crystal quality of epitaxial layer, and then prepare
High carrier mobility, high performance cmos device.
Further, the present invention uses LIMO 795nm continuous wave lasers, refers to Fig. 4, Fig. 4 carries for the embodiment of the present invention
A kind of laser supplied brilliant process unit schematic diagram again.Laser is pointed into sample stage by total reflection prism, and passes through convex lens focus
Onto sample, so as to prevent the liquid in thermal histories after film melts to be affected by gravity and flow the shadow to crystallization generation
Ring.During laser crystallization, stepper motor drives sample stage movement, is often moved to a position and carries out a laser irradiation, makes the position
It is set to as the blockage with high-energy, then stops the laser irradiation, sample stage is further continued for laser photograph when is moved to the next position
Penetrate.So circulation causes laser to be irradiated to whole film surface successively, so far completes continuous laser crystallization process again.
Wherein, laser crystallization Si again0.11Ge0.89Epitaxial layer 002 needs accurately to control laser physics parameter such as laser power,
Irradiate speed etc., and SiO2Protective layer 003, Si0.11Ge0.89The initial temperature and epitaxial layer of epitaxial layer 002 and Si substrates 001
Thickness.Setting for laser power is, it is necessary to which laser energy can make Si0.11Ge0.89The temperature of epitaxial layer 002 is at least up to fusing point,
And as high as possible but it is unlikely to exceed ablation point.Such heat treatment process, can significantly improve Si0.11Ge0.89Epitaxial layer 002
Crystal quality.SiO2Protective layer 003, Si0.11Ge0.89The initial temperature of epitaxial layer 002 and Si substrates 001 is also to need emphasis
The experimental parameter of consideration, SiO is preheated before laser again crystallization2Protective layer 003, Si0.11Ge0.89Epitaxial layer 002 and Si substrates 001
Threshold value laser power of the laser again needed for crystallization can be significantly reduced.Meanwhile Si substrates 001 and Si0.11Ge0.89Epitaxial layer 002 is deposited
In thermal mismatching, system preheating can also effectively prevent that material cracks show caused by temperature is instantaneously sharply increased when laser irradiates
As；
Natural cooling SiO after S106, laser irradiation2Protective layer 003, Si0.11Ge0.89Epitaxial layer 002 and Si substrates 001
Whole substrate material.Continuous laser irradiates so that high-Ge component Si0.11Ge0.89Epitaxial layer 002 is tied again after fusing and cooling occurs
Brilliant process so that epitaxial layer dislocation density substantially reduces；
S107, such as Fig. 2 d, the SiO is etched using dry etch process2Protective layer 003, after obtaining crystallization
Si0.11Ge0.89The Si that epitaxial layer 002 is formed with Si substrates 0010.11Ge0.89/ Si void substrate materials；
S108, such as Fig. 2 e, at a temperature of 500~600 DEG C, using CVD techniques, in Si0.11Ge0.89/ Si void substrate surface is given birth to
Long thickness is the p-type Si of 900~950nm0.11Ge0.89Channel layer 004, doping concentration are 1 × 1016~5 × 1016cm-3；
S109, such as Fig. 2 f, using dry etch process, in Si0.11Ge0.89Etched on channel layer 004 depth for 100~
The shallow slot of 150nm；
S110, such as Fig. 2 g, at a temperature of 750 DEG C~850 DEG C, using CVD techniques, in Si0.11Ge0.89004 surface of channel layer
Grow SiO2Material 005, will fill up in the shallow slot；
S111, such as Fig. 2 h, using CVD techniques, in SiO2005 surface growth thickness of material is the Si of 20~30nm3N4Material
006；
S112, such as Fig. 2 i, part SiO is removed using CMP process2Material and Si3N4Material, remove thickness be about 20~
30nm；
S113, such as Fig. 2 j, using anisotropic dry etch process, etch away Si0.11Ge0.89004 surface of channel layer
SiO2Material, retains the SiO in shallow slot2Material forms shallow trench isolation areas；
S114, such as Fig. 2 k, including Si0.11Ge0.89/ Si void substrate, Si0.11Ge0.89Channel layer and shallow trench isolation areas
Whole substrate surface smears the first photoresist 008, expose regional area photoresist and using ion implantation technology injection P from
Son, forms N traps 007；
S115, such as Fig. 2 l, remove the first photoresist 008；
S116, in 600 DEG C~1000 DEG C of H2Whole substrate Si surfaces caused by repair ion implanting are heated in environment
Lens lesion；
S117, such as Fig. 2 m, in the HfO that whole substrate surface growth thickness is 2~10nm2Material 009；
S118, such as Fig. 2 n, at a temperature of 750~850 DEG C, using CVD techniques, in the HfO2009 surface of material is grown
Thickness is the TiN materials 010 of 110nm；
S119, such as Fig. 2 o, utilize selective etch technique etched portions TiN materials and HfO2Material, forms NMOS gate
With PMOS grids, the active area of formation NMOS and PMOS；
S120, such as Fig. 2 p, using CVD techniques, in the NMOS gate and PMOS gate surfaces growth SiO2Oxide layer
011, and the SiO in the region using selective etch technique etching in addition to the NMOS gate and PMOS grids2Oxide layer；
S121, such as Fig. 2 q, cover NMOS area, using ion implantation technology, in N traps using the second photoresist 012
PMOS active areas carry out BF2 +Injection forms PMOS source area and drain region 013；
S122, such as Fig. 2 r, cover N well region, using ion implantation technology, to the NMOS using the 3rd photoresist 014
Active area carries out As ion implantings and forms NMOS source regions and drain region 015；
S123, such as Fig. 2 s, remove the SiO of NMOS gate and the PMOS gate surface2Oxide layer 011；
S124, such as Fig. 2 t, using CVD techniques, in the BPSG dielectric layers that whole substrate surface growth thickness is 20~30nm
016；
S125, such as Fig. 2 u, NMOS source and drain contact hole and PMOS source drain contact are formed using nitric acid and hf etching BPSG
Hole；
S126, such as Fig. 2 v, using electron beam evaporation process, grow contact electrode 017 in whole substrate surface；Contact electrode
Material is metal W；Wherein, metal W fill up NMOS source and drain contact hole and PMOS source miss after contact hole exposed portion thickness for 10~
20nm；
S127, such as Fig. 2 w, the metal W for specifying region is etched using selective etch technique, and is put down using CMP process
Smoothization processing；
S128, such as Fig. 2 x, using CVD techniques, grow the passivation layer 018 of SiN materials in whole substrate surface, passivation layer
Thickness is 20~30nm, ultimately forms laser crystallization high-Ge component Si again0.11Ge0.89Cmos device.
Above content is that a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to is assert
The specific implementation of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (9)
- A kind of 1. sige material cmos device, it is characterised in that including：Si1-xGex/ Si void substrate (101)；Si1-xGexChannel layer (102), is arranged at the Si1-xGexOn/Si void substrate (101)；Dielectric layer (103), is arranged at the Si1-xGexOn channel layer (102)；Isolated area (104), is arranged at the Si1-xGexChannel layer (102) and the dielectric layer (103) are internal；N well regions (105), are arranged at the Si of the isolated area (104) side1-xGexIn channel layer (102)；PMOS area (106) and NMOS area (107), are respectively arranged at the both sides of the isolated area (104)；Passivation layer (108), is arranged on the dielectric layer (103).
- 2. sige material cmos device according to claim 1, it is characterised in that the Si1-xGex/ Si void substrate (101) Include Si substrates (1011) and Si from lower to upper1-xGexEpitaxial layer (1012), using laser, crystallization process handles the Si linings again Bottom (1011) and the Si1-xGexEpitaxial layer (1012) forms the Si afterwards1-xGex/ Si void substrate (101).
- 3. sige material cmos device according to claim 2, it is characterised in that crystallization process is utilization to the laser again Laser irradiates the Si on the Si substrates (1011)1-xGexEpitaxial layer (1012), makes the Si1-xGexEpitaxial layer (1012) Fusing recrystallization, wherein, optical maser wavelength 795nm, laser power density 2.85kW/cm2, laser spot size 10mm × 1mm, laser traverse speed 20mm/s.
- 4. sige material cmos device according to claim 3, it is characterised in that the Si1-xGexX values in epitaxial layer For 0.7~0.9.
- 5. sige material cmos device according to claim 4, it is characterised in that the Si1-xGexThe thickness of epitaxial layer is 450~500nm.
- 6. sige material cmos device according to claim 1, it is characterised in that the Si1-xGexChannel layer (102) is P Type Si1-xGexChannel layer, doping concentration are 1 × 1016~5 × 1016cm-3。
- 7. the sige material cmos device according to claim 1 or 6, it is characterised in that the Si1-xGexChannel layer (102) Thickness be 900~950nm.
- 8. sige material cmos device according to claim 1, it is characterised in that the PMOS area (106) includes PMOS source area, PMOS drain regions, PMOS grids, PMOS source region electrode and PMOS drain regions electrode；Wherein, the PMOS source area and described PMOS drain regions are arranged in the N well regions (105), and the PMOS grids are arranged on the N well regions (105).
- 9. sige material cmos device according to claim 1, it is characterised in that the NMOS area (107) includes NMOS source regions, NMOS drain regions, NMOS gate, NMOS source regions electrode and NMOS drain regions electrode；Wherein, NMOS source regions and described NMOS drain regions are arranged at the Si1-xGexIn channel layer (102), the NMOS gate is arranged at the Si1-xGexChannel layer (102) on.
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Application publication date: 20180504 |