CN107979369A - Keep the method and phase-locked loop circuit adjustment method of phase lock loop circuit loop bandwidth - Google Patents
Keep the method and phase-locked loop circuit adjustment method of phase lock loop circuit loop bandwidth Download PDFInfo
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- CN107979369A CN107979369A CN201711207444.2A CN201711207444A CN107979369A CN 107979369 A CN107979369 A CN 107979369A CN 201711207444 A CN201711207444 A CN 201711207444A CN 107979369 A CN107979369 A CN 107979369A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The embodiment of the present invention provides a kind of method for keeping phase lock loop circuit loop bandwidth, including：Determine reference charge pump electric current, reference frequency gain and reference frequency dividing average value that phase-locked loop circuit is under reference state；The product divided by reference frequency dividing average value for determining reference charge pump electric current and reference frequency gain are reference state value；Determine the frequency curve of the voltage controlled oscillator of phase-locked loop circuit；First control voltage of voltage controlled oscillator and the second control voltage when phase-locked loop circuit being arranged to integral frequency divisioil pattern, and obtaining integer part ± 1 with reference to frequency dividing average value respectively；Determine the real-time frequency gain of voltage controlled oscillator；Determine the real-time frequency dividing average value corresponding to real-time frequency gain；According to real-time frequency gain, frequency dividing average value and reference state value determine real-time charge pump current in real time.The method of the embodiment of the present invention can keep the loop bandwidth substantially constant of phase-locked loop circuit, solve due to the problem of loop bandwidth fluctuates, causes loss of data.
Description
Technical field
The present embodiments relate to electronic circuit technology field, more particularly to a kind of phase lock loop circuit loop bandwidth that keeps
Method and phase-locked loop circuit adjustment method.
Background technology
Current wireless communications chips widely use frequency modulating technology and carry out digital radio communication system, for example, common
The communication chips such as WIFI, bluetooth.When wireless communications chips use frequency modulating technology, there is two ways to realize baseband signal extremely
The frequency modulation(PFM) of radiofrequency signal：A kind of mode is that digital baseband signal is passed through DAC (Digital to Analog
Converter：Digital analog converter) analog baseband signal is converted into, then pass through analog baseband signal and up-conversion mixer
Mixing operations are converted into rf modulated signal, are launched finally by radio-frequency power amplifier chip；Another side
Formula is that the phase-locked loop frequency integrator that fractional frequency division is directly modulated using digital baseband signal obtains rf modulated signal, this can be with
DAC and up-conversion mixer are saved, great improvement is brought to the power consumption and area of radio transceiver movement piece, at present
As the implementation of frequency modulator mainstream.
It is described above that the phase-locked loop frequency integrator of fractional frequency division is directly modulated using digital baseband signal
Mode, generally inputs digital baseband signal at the digital Sigma-Delta modulator of phaselocked loop.From Sigma-Delta tune
The ssystem transfer function of the input terminal of device processed to the output terminal of phase-locked loop frequency integrator shows as the characteristic of low pass.Therefore,
Ensure launching by rf modulated signal for baseband signal free of losses, it is ensured that the loop bandwidth of phaselocked loop is more than chip
Communication speed.
The open loop expression formula of cycle of phase-locked loop is：
The closed loop expression formula of cycle of phase-locked loop is：
The loop bandwidth of phaselocked loop is can be seen that by Icp (electric current of charge pump), N (frequency dividers from both the above expression formula
Frequency dividing multiple) and Kvco (frequency gain of VCO) and Hlpf(s) (transmission function of loop filter) determines.Wherein, Hlpf
(s) generally formed by having no chance device, there is larger stability；The value of N changes with the frequency shift of wireless telecommunications.
In order to reduce the phase noise of phaselocked loop local oscillation signal, it is necessary to reduce VCO (Voltage Controlled
Oscillator：Voltage controlled oscillator) frequency gain, while ensure that VCO covers sufficiently large frequency range, generally in VCO
Portion uses switched capacitor array so that VCO has a plurality of frequency curve.Mutually overlap mutually between side frequency curve and ensure that VCO connects
Continuous coverage goal frequency range, while the frequency gain (Kvco) of every frequency curve is smaller.But the Kvco of different frequency curve is deposited
In difference, the higher curve of frequency has larger Kvco.VCO with a plurality of frequency curve can be in the initial rank of phase-locked loop operation
Section is corrected VCO, and to determine which bar frequency curve selected, when phaselocked loop needs to be locked in upper frequency, VCO has been corrected
Into afterwards, the higher curve of frequency can be selected；Otherwise the relatively low curve of frequency can be selected.
According to foregoing description, when wireless communications chips are operated in different frequency, if Icp maintains fixed value, phase is locked
The loop bandwidth of ring can change because of the change of N and Kvco, if the bandwidth of phaselocked loop is less than the transmission rate of wireless signal,
Data will be caused to produce loss.
Loss of data is produced to solve the problems, such as that bandwidth of phase lock loop reduces, current way will generally when chip designs
The loop bandwidth of phaselocked loop is designed to be much larger than message transmission rate, ensures to reduce even if the bandwidth emission of phaselocked loop also big all the time
In the transmission rate of data, but bring the waste of chip power-consumption and area.
The content of the invention
The embodiment of the present invention provides a kind of method and phase-locked loop circuit adjustment method for keeping phase lock loop circuit loop bandwidth,
At least to solve one of above-mentioned technical problem.
The embodiment of the present invention provides a kind of method for keeping phase lock loop circuit loop bandwidth, including：
The state selected when the phase-locked loop circuit is operated in the predeterminated frequency is reference state；
Determine reference charge pump electric current, reference frequency gain and ginseng that the phase-locked loop circuit is under the reference state
Examination mark frequency average value；
Determine obtained by product divided by the reference frequency dividing average value of the reference charge pump electric current and reference frequency gain
Ratio as referring to state value；
Determine the frequency curve of the voltage controlled oscillator of the phase-locked loop circuit；
The phase-locked loop circuit is arranged to integral frequency divisioil pattern, and obtains the integer with reference to frequency dividing average value respectively
Partly ± 1 when, the voltage controlled oscillator first control voltage and second control voltage；
The reference of difference and the phase-locked loop circuit based on the described first control voltage and the second control voltage
Clock frequency determines the real-time frequency gain of the voltage controlled oscillator；
Determine the real-time frequency dividing average value corresponding to the real-time frequency gain；
According to the real-time frequency gain, frequency dividing average value and reference state value determine to keep under current state in real time
The real-time charge pump current of the loop bandwidth.
In certain embodiments, the predeterminated frequency is the centre frequency of the working frequency of the phase-locked loop circuit.
In certain embodiments, the frequency curve of the voltage controlled oscillator for determining the phase-locked loop circuit includes：
The frequency curve of the voltage controlled oscillator of the phase-locked loop circuit is determined by the zero offset capability of voltage controlled oscillator.
In certain embodiments, the phase-locked loop circuit is arranged to integral frequency divisioil pattern, and obtains the reference respectively
When dividing integer part ± 1 of average value, the first control voltage of the voltage controlled oscillator and the second control voltage include：
The phase-locked loop circuit is arranged to integral frequency divisioil pattern；
Take the integer part with reference to frequency dividing average value to add 1 as the first reference and divide average value, and obtain institute at this time
State the first control voltage of voltage controlled oscillator；
Take the integer part with reference to frequency dividing average value to subtract 1 as second with reference to frequency dividing average value, and obtain institute at this time
State the second control voltage of voltage controlled oscillator.
In certain embodiments, it is described true according to the real-time frequency gain, real-time frequency dividing average value and reference state value
Determine the real-time charge pump current of the loop bandwidth can be kept to include under current state：
The product divided by the average value of frequency dividing in real time for making real-time charge pump current and the real-time frequency gain are equal to institute
Reference state value is stated, to be determined to keep the real-time charge pump current of the loop bandwidth.
In certain embodiments, the phase-locked loop circuit is the frequency synthesizer of fractional frequency division.
On the other hand, the present invention also provides a kind of phase-locked loop circuit adjustment method, including：Using any of the above-described reality of the present invention
The voltage controlled oscillator for applying the method acquisition phase-locked loop circuit of the holding phase lock loop circuit loop bandwidth described in example is operated in
Charge pump current during any frequency range.
The method of the embodiment of the present invention can keep the loop bandwidth substantially constant of phase-locked loop circuit, solve due to loop
Bandwidth fluctuation, the problem of causing loss of data.Real-time charge pump current (Icp) value of the present invention is not fixed, but root
Factually the frequency gain of the real-time frequency gain on border, real-time frequency dividing average value and voltage controlled oscillator is come to real-time charge pump current
Carry out adjusting output in real time, so that the substantially constant of PLL loop bandwidth is maintained, to solve bandwidth of phase lock loop due to ripple
The problem of reducing and producing loss of data is moved, while also solves the problems, such as chip power-consumption in the prior art and area loss.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, drawings in the following description are this hairs
Some bright embodiments, for those of ordinary skill in the art, without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the flow chart of an embodiment of the method for the holding phase lock loop circuit loop bandwidth of the present invention；
Fig. 2 is the flow chart of another embodiment of the method for the holding phase lock loop circuit loop bandwidth of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiments obtained without creative efforts, belong to the scope of protection of the invention.
It should be noted that in the case where there is no conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.Below with reference to the accompanying drawings and the present invention will be described in detail in conjunction with the embodiments.
As shown in Figure 1, in one embodiment, the method for holding phase lock loop circuit loop bandwidth of the invention includes：
S11, the state selected when the phase-locked loop circuit is operated in the predeterminated frequency are reference state；Wherein, it is described
Predeterminated frequency is the centre frequency of the working frequency of the phase-locked loop circuit.
S12, determine that the reference charge that the phase-locked loop circuit is under the reference state pumps electric current, reference frequency gain
Average value is divided with reference；
S13, the product for determining the reference charge pump electric current and reference frequency gain divided by the reference frequency dividing average value
The ratio of gained is used as and refers to state value；
S14, determine the phase-locked loop circuit voltage controlled oscillator frequency curve；Specifically, voltage controlled oscillator is passed through
Zero offset capability determines the frequency curve of the voltage controlled oscillator of the phase-locked loop circuit；
S15, by the phase-locked loop circuit be arranged to integral frequency divisioil pattern, and obtains respectively described with reference to frequency dividing average value
During integer part ± 1, the first control voltage of the voltage controlled oscillator and the second control voltage；
S16, the difference based on the described first control voltage and the second control voltage and the phase-locked loop circuit
Reference clock frequency determines the real-time frequency gain of the voltage controlled oscillator；
S17, determine to divide average value corresponding to the real-time of the real-time frequency gain；
S18, according to the real-time frequency gain, determine can under current state for frequency dividing average value and reference state value in real time
Keep the real-time charge pump current of the loop bandwidth.
The method of the embodiment of the present invention can keep the loop bandwidth substantially constant of phase-locked loop circuit, solve due to loop
Bandwidth fluctuation, the problem of causing loss of data.Real-time charge pump current (Icp) value of the present invention is not fixed, but root
Factually the frequency gain of the real-time frequency gain on border, real-time frequency dividing average value and voltage controlled oscillator is come to real-time charge pump current
Carry out adjusting output in real time, so that the substantially constant of PLL loop bandwidth is maintained, to solve bandwidth of phase lock loop due to ripple
The problem of reducing and producing loss of data is moved, while also solves the problems, such as chip power-consumption in the prior art and area loss.
As shown in Fig. 2, in certain embodiments, the phase-locked loop circuit is arranged to integral frequency divisioil pattern, and obtain respectively
When taking integer part ± 1 of the reference frequency dividing average value, the first control voltage of the voltage controlled oscillator and the second control electricity
Briquetting includes：
S21, by the phase-locked loop circuit be arranged to integral frequency divisioil pattern；
S22, take the integer part with reference to frequency dividing average value to add 1 as the first reference frequency dividing average value, and obtains this
First control voltage of Shi Suoshu voltage controlled oscillators；
S23, take the integer part with reference to frequency dividing average value to subtract 1 as second with reference to frequency dividing average value, and obtains this
Second control voltage of Shi Suoshu voltage controlled oscillators.
It is Nint+Nfrac (Nfrac that frequency dividing average value is referred in the present embodiment<1), wherein, Nint represents frequency divider integer
Partial frequency dividing ratio, Nfrac represent the frequency dividing ratio of frequency divider fractional part, Ndiv are arranged respectively to Nint ± 1 and may insure
The frequency and reality that PLL (Phase Locked Loop, phaselocked loop) is locked when calculating Kvco (frequency gain of voltage controlled oscillator)
Border frequency is closest, in the case of avoiding Fref frequencies larger, causes frequency range at this time single more than VCO (voltage controlled oscillator)
The frequency range of a curve covering.
In certain embodiments, it is described true according to the real-time frequency gain, real-time frequency dividing average value and reference state value
Determine the real-time charge pump current of the loop bandwidth can be kept to include under current state：
The product divided by the average value of frequency dividing in real time for making real-time charge pump current and the real-time frequency gain are equal to institute
Reference state value is stated, to be determined to keep the real-time charge pump current of the loop bandwidth.
On the other hand, the present invention also provides a kind of phase-locked loop circuit adjustment method, including：Using any of the above-described reality of the present invention
The voltage controlled oscillator for applying the method acquisition phase-locked loop circuit of the holding phase lock loop circuit loop bandwidth described in example is operated in
Charge pump current during any frequency range.
In the specific embodiment of the invention, the phaselocked loop in wireless communications chips is the frequency synthesizer of fractional frequency division, is locked
The local frequency that phase ring finally locks determines by inputting certain numerical value to the Sigma-Delta modulator of numeral, the numerical value
It is exactly the frequency dividing average value of the frequency divider of phase-locked loop circuit, and the frequency dividing average value is calculated by following formula：
Fpll=Ndiv*Fref=(Nint+Nfrac) * Fref
Wherein Nint represents the frequency dividing ratio of frequency divider integer part, and Nfrac represents the frequency dividing ratio of frequency divider fractional part.On
The frequency dividing average value for stating frequency divider is calculated by the digital baseband circuit of chip.
Using the centre frequency of wireless communications chips working frequency range as the state of referring to, set parameter under the state as
Icp0, N0, Kvco0 (correspond respectively to reference charge pump electric current, with reference to frequency dividing average value and reference frequency gain).With Icp*
The calculated value of Kvco/N is as basic parameter Pref computational methods.Pref0=Icp0*Kvco0/N0.
In this embodiment, after the frequency dividing average value of the frequency divider of phaselocked loop determines, phaselocked loop passes through VCO first
Zero offset capability (generally by dichotomy find VCO control voltage be equal to VDD/2 when, VCO frequency and target frequency most connect
Near frequency curve) determine the frequency curve of VCO.At this time, the frequency gain of the VCO frequency curve is unknown.
After the frequency curve of VCO determines, phaselocked loop is made to enter integral frequency divisioil pattern, at this time Sigma-Delta modulator
The value of Ndiv directly will be arranged to Nint+1, then made phaselocked loop be locked by Bypass, detect phase lock loop locks it
Afterwards, using voltage detector, such as an adc circuit, the control voltage Vtune of VCO is converted into digital signal, and be stored in
In some RAM of chip, Vtune1 is denoted as.Then the value of Ndiv is arranged to Nint-1, makes phaselocked loop be locked again, examined
After measuring phase lock loop locks, using voltage detector, the control voltage Vtune of VCO is converted into digital signal, and be stored in
In some RAM of chip, Vtune2 is denoted as.Obtain being calculated according to following equation after above-mentioned two difference Vtune values and work as
The frequency gain of preceding VCO frequency curve：
Kvco=2*Fref/ (Vtune1-Vtune2)
Basic parameter Pref can be calculated as Pref=Icp*Kvco/Ndiv at this time, make Pref be equal to Pref0, can
Using be calculated the current value of Icp as
Icp=(Icp0*Kvco0/N0)/(Kvco/Ndiv)
Icp, which takes, can ensure that basic parameter Pref is equal to Pref0 when above-mentioned value, namely maintain the loop band of phaselocked loop
Width is steady state value.
Above-mentioned specific embodiment be real time correction Icp mode, in addition can also chip manufacturing come out after,
Corresponding Icp adjusted values under chip all working frequency are obtained by the correction to chip full frequency band before dispatching from the factory, and by above-mentioned Icp
In the ROM not lost there are chip power-down with the correspondence of working frequency, when client using when can directly invoke, avoid
Calculated in real time in use and influence the operating rate of circuit.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used
To modify to the technical solution described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical solution spirit and
Scope.
Claims (7)
1. a kind of method for keeping phase lock loop circuit loop bandwidth, including：
The state selected when the phase-locked loop circuit is operated in predeterminated frequency is reference state；
Determine reference charge pump electric current, reference frequency gain and reference point that the phase-locked loop circuit is under the reference state
Frequency average value；
Determine the product of the reference charge pump electric current and reference frequency gain divided by the ratio with reference to obtained by frequency dividing average value
It is worth for reference state value；
Determine the frequency curve of the voltage controlled oscillator of the phase-locked loop circuit；
The phase-locked loop circuit is arranged to integral frequency divisioil pattern, and obtains the integer part with reference to frequency dividing average value respectively
First control voltage of the voltage controlled oscillator and the second control voltage when ± 1；
The reference clock of difference and the phase-locked loop circuit based on the described first control voltage and the second control voltage
Frequency determines the real-time frequency gain of the voltage controlled oscillator；
Determine the real-time frequency dividing average value corresponding to the real-time frequency gain；
According to the real-time frequency gain, described in frequency dividing average value and reference state value determine can to keep under current state in real time
The real-time charge pump current of loop bandwidth.
2. according to the method described in claim 1, wherein, the predeterminated frequency is in the working frequency of the phase-locked loop circuit
Frequency of heart.
3. according to the method described in claim 1, wherein, the frequency of the voltage controlled oscillator for determining the phase-locked loop circuit is bent
Line includes：
The frequency curve of the voltage controlled oscillator of the phase-locked loop circuit is determined by the zero offset capability of voltage controlled oscillator.
4. according to the method described in claim 1, wherein, the phase-locked loop circuit is arranged to integral frequency divisioil pattern, and difference
When obtaining integer part ± 1 of the reference frequency dividing average value, the first control voltage of the voltage controlled oscillator and the second control
Voltage includes：
The phase-locked loop circuit is arranged to integral frequency divisioil pattern；
Take the integer part with reference to frequency dividing average value to add 1 as the first reference and divide average value, and obtain the pressure at this time
Control the first control voltage of oscillator；
Take the integer part with reference to frequency dividing average value to subtract 1 as second with reference to frequency dividing average value, and obtain the pressure at this time
Control the second control voltage of oscillator.
5. according to the method described in claim 1, wherein, it is described according to the real-time frequency gain, in real time frequency dividing average value and
Reference state value determines that the real-time charge pump current of the loop bandwidth can be kept to include under current state：
The product divided by the average value of frequency dividing in real time for making real-time charge pump current and the real-time frequency gain are equal to the ginseng
State value is examined, to be determined to keep the real-time charge pump current of the loop bandwidth.
6. according to the method any one of claim 1-5, wherein, the phase-locked loop circuit is comprehensive for the frequency of fractional frequency division
Clutch.
7. a kind of phase-locked loop circuit adjustment method, including：The lock is obtained using the method any one of claim 1-6
The voltage controlled oscillator of phase loop circuit is operated in charge pump current during any frequency range.
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