CN107977537A - A kind of logical product yield monitoring of structures and its design method - Google Patents
A kind of logical product yield monitoring of structures and its design method Download PDFInfo
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- CN107977537A CN107977537A CN201711461971.6A CN201711461971A CN107977537A CN 107977537 A CN107977537 A CN 107977537A CN 201711461971 A CN201711461971 A CN 201711461971A CN 107977537 A CN107977537 A CN 107977537A
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- structures
- product yield
- monitoring
- logical product
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The present invention discloses a kind of logical product yield monitoring of structures and its design method.The logical product yield monitoring of structures, including：Monitoring memory cell, the monitoring memory cell by logical operation standard cell design into reverser combination of two formed；Peripheral circuit, is matched the monitoring memory cell with peripheral circuit by circuit-level simulation program, and logical product yield is monitored with realizing.Logical product yield monitoring of structures of the present invention can not only make up traditional SRAM test structures defect, but also just be introduced in the development phase, just to solve Product-level yield issues before product yield imports, be effectively compressed the product volume production cycle, reach quick upper amount purpose.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of logical product yield monitoring of structures and its design side
Method.
Background technology
As advanced process is developed, technical difficulty exponentially rises.What is needed most in process exploitation is monitoring technique
" eyes ", that is, need various test structures (Test key/Test vehicle) to confirm process abnormality point in first time,
And then improve shorten the process exploitation cycle in time.
At present, because prepared by the country, manufacturer's technological accumulation is limited, and input human resources on process exploitation are tight
The problems such as weight deficiency, extremely lack the development and usage of a set of complete advanced process exploitation test structure, to realize advanced process
The sustainable development of technological development, avoids bringing doctrine without understanding reason, captures a technology node without method system
Instrument provides support for process exploitation of lower generation.So the domestic manufacturer for preparing more takes and has experience specialized company, example at present
As PDF suppliers cooperate, borrow other people and test the intellectual property of detection structure, help process exploitation.However, prepare factory in cooperation
The business secret of the critical process of business certainly will cause cooperation to be difficult to efficiently inevitably there are risk of leakage, can not be with having by oneself
Intellectual property's exploitation is autonomous, controllable high-efficiency compares favourably.
In the industry cycle, core detection instrument of the SRAM test structures as process exploitation is used in Yield lmproved at present, but
At present since process node is approached to technological limits, multidimensional effect continuously emerges, and SRAM test structures fully effective cannot detect
The health degree of technique, it is very high to be easy to cause SRAM yields, but product import after product yield be far below SRAM yields, cause yield
Lifting is very slow, and SRAM can not detect product yield problem.
Therefore in view of the problems of the existing technology, this case designer is by the experience of the industry for many years is engaged in, actively research
Improvement, then there is a kind of logical product yield monitoring of structures of the invention and its design method.
The content of the invention
The present invention be directed in the prior art, traditional SRAM test structures cannot fully effective characterization processes health degree,
It is very high to be easy to cause SRAM yields, but product yield is far below SRAM yields after product importing, causes Yield lmproved very slow, and
SRAM can not detect that the defects of product yield problem provides a kind of logical product yield monitoring of structures.
The further object of the present invention is that traditional SRAM test structures cannot fully effective characterization processes in the prior art
Health degree, it is very high to be easy to cause SRAM yields, but product import after product yield be far below SRAM yields, cause Yield lmproved
The defects of very slow, and SRAM can not detect product yield problem, provides a kind of design side of logical product yield monitoring of structures
Method.
To realize the purpose of the present invention, the present invention provides a kind of logical product yield monitoring of structures, and the logical product is good
Rate monitoring of structures, including：Monitoring memory cell, the monitoring memory cell by logical operation standard cell design into reverser
Combination of two is formed；Peripheral circuit, is matched the monitoring memory cell with peripheral circuit by circuit-level simulation program, with reality
Now logical product yield is monitored.
Alternatively, the logical product is 28nm/14nm technology nodes.
Alternatively, the logical operation standard block may be designed to the unit of monitoring logical product yield.
Alternatively, the logical operation standard block is NAND structures, AND structures, NOR structures, OR structures.
Alternatively, the device operating voltages (V of the reverserdd), circuit common ground terminal voltage (Vss) input terminal according to
It is configured according to the design of corresponding reverser.
Alternatively, the species of the reverser is N kinds, the species of the detection storage unit that combination of two is formed be N ×
(N-1)/2！Kind.
Alternatively, there is the same area that same type monitoring memory cell is arranged on the logical product yield monitoring of structures
Block.
To realize the further object of the present invention, the present invention provides a kind of design method of logical product yield monitoring of structures,
The design method of the logical product yield monitoring of structures, including：
Perform step S1：It is reverser by logical operation standard cell design；
Perform step S2：By by the logical operation standard cell design into reverser, combination of two formed have deposits
Store up the monitoring memory cell of function；
Perform step S3：The monitoring memory cell is matched with peripheral circuit by circuit-level simulation program, to realize
Logical product yield is monitored.
In conclusion logical product yield monitoring of structures of the present invention can not only make up traditional SRAM test structures defect,
And just introduced in the development phase, just to solve Product-level yield issues before product yield imports, it is effectively compressed product volume
The cycle is produced, reaches quick upper amount purpose.
Brief description of the drawings
Fig. 1 show the flow chart of the design method of logical product yield monitoring of structures of the present invention；
Fig. 2 show logical product yield monitoring of structures layout；
Fig. 3 show the reverser being designed to as the NAND structures of logical operation standard block；
Fig. 4 show the reverser being designed to as the AND structures of logical operation standard block；
Fig. 5 show the reverser being designed to as the NOR structures of logical operation standard block；
Fig. 6 show the reverser being designed to as the OR structures of logical operation standard block；
Fig. 7 show NAND type storage unit；
Fig. 8 show NOR type storage unit；
Fig. 9 show NAND＆NOR type storage units；
Figure 10 show AND＆NAND type storage units.
Embodiment
For the present invention will be described in detail create technology contents, construction feature, institute's reached purpose and effect, below in conjunction with reality
Apply example and coordinate attached drawing to be described in detail.
As advanced process is developed, technical difficulty exponentially rises.What is needed most in process exploitation is monitoring technique
" eyes ", that is, need various test structures (Test key/Test vehicle) to confirm process abnormality point in first time,
And then improve shorten the process exploitation cycle in time.
At present, because prepared by the country, manufacturer's technological accumulation is limited, and input human resources on process exploitation are tight
The problems such as weight deficiency, extremely lack the development and usage of a set of complete advanced process exploitation test structure, to realize advanced process
The sustainable development of technological development, avoids bringing doctrine without understanding reason, captures a technology node without method system
Instrument provides support for process exploitation of lower generation.So the domestic manufacturer for preparing more takes and has experience specialized company, example at present
As PDF suppliers cooperate, borrow other people and test the intellectual property of detection structure, help process exploitation.However, prepare factory in cooperation
The business secret of the critical process of business certainly will cause cooperation to be difficult to efficiently inevitably there are risk of leakage, can not be with having by oneself
Intellectual property's exploitation is autonomous, controllable high-efficiency compares favourably.
In the industry cycle, core detection instrument of the SRAM test structures as process exploitation is used in Yield lmproved at present, but
At present since process node is approached to technological limits, multidimensional effect continuously emerges, and SRAM test structures fully effective cannot detect
The health degree of technique, it is very high to be easy to cause SRAM yields, but product import after product yield be far below SRAM yields, cause yield
Lifting is very slow, and SRAM can not detect product yield problem.
Referring to Fig. 1, Fig. 1 show the flow chart of the design method of logical product yield monitoring of structures of the present invention.It is described
The design method of logical product yield monitoring of structures, including：
Perform step S1：It is reverser by logical operation standard cell design；
Perform step S2：By by the logical operation standard cell design into reverser, combination of two formed have deposits
Store up the monitoring memory cell of function；
Perform step S3：The monitoring memory cell is matched with peripheral circuit by circuit-level simulation program, to realize
Logical product yield is monitored.
Referring to Fig. 2, and combine refer to Fig. 1, Fig. 2 show logical product yield monitoring of structures layout.The logic
Product yield monitoring of structures, including：Monitoring memory cell, the monitoring memory cell by logical operation standard cell design into
Reverser combination of two is formed；Peripheral circuit, by circuit-level simulation program by the monitoring memory cell and peripheral circuit
Match somebody with somebody, logical product yield is monitored with realizing.The logical product is 28nm/14nm technology nodes.
In order to more intuitively disclose the technical solution of the present invention, the beneficial effect of the present invention is highlighted, in conjunction with specific implementation
Exemplified by mode, the logical product yield monitoring of structures and monitoring method are illustrated.In a specific embodiment, it is described to patrol
It is only to enumerate to collect the species of computing standard block, the building form of reverser, number of devices etc., is not construed as to the technology of the present invention
The limitation of scheme.
Fig. 3~Figure 10 is referred to, and combines and refers to Fig. 1, Fig. 2, Fig. 3 show the NAND as logical operation standard block
The reverser that structure is designed to.Fig. 4 show the reverser being designed to as the AND structures of logical operation standard block.Fig. 5 institutes
It is shown as the reverser being designed to as the NOR structures of logical operation standard block.Fig. 6 is shown as logical operation standard block
The reverser that is designed to of OR structures.Fig. 7 show NAND type storage unit.Fig. 8 show NOR type storage unit.Shown in Fig. 9
For NAND＆NOR type storage units.Figure 10 show AND＆NAND type storage units.The logical product yield monitoring of structures it
Design method, including：
Perform step S1：It is reverser by logical operation standard cell design；
Without limitation, the logical operation standard block include but not limited to NAND structures, AND structures, NOR structures,
OR structures.Meanwhile as logical operation standard block NAND structures be designed to reverser, as logical operation standard block
AND the structures reverser, the reverser that is designed to of NOR structures as logical operation standard block that are designed to, and conduct
Device operating voltages (the V for the reverser that the OR structures of logical operation standard block are designed todd), circuit common ground terminal voltage
(Vss) input terminal according to corresponding reverser design be configured.
More specifically, exemplified by the reverser being designed to using the NAND structures as logical operation standard block, in order to more preferable
Adhere to technique, the device operating voltages (V of the reverserdd), circuit common ground terminal voltage (Vss) input terminal according to described in
Corresponding reverser design is configured.The one input end for the reverser that i.e. described NAND structures are designed to sets device to work
Voltage (Vdd), or another input terminal of reverser that the NAND structures are designed to sets device operating voltages (Vdd), its reason
The one input end in standard unit picture, another input terminal may non complete symmetry, residing surrounding environment phase not to the utmost
Together, therefore above two sets and is both needed to consider.
Perform step S2：By by the logical operation standard cell design into reverser, combination of two formed have deposits
Store up the monitoring memory cell of function；
As those skilled in the art, it is readily appreciated that ground, if the species of the reverser is N kinds, combination of two is formed
The species of detection storage unit be { N × (N-1)/2！Kind.It is apparent that in the invention, by logical operation standard list
Meta design into reverser do not limit and be made of NAND structures, NOR structures, AND structures, OR structural circuits, can also be patrolled by other
Collect the setting of computing standard block to provide, the purpose is to good into can effectively monitor logical product by logical operation standard cell design
The unit of rate.
Perform step S3：The monitoring memory cell is matched with peripheral circuit by circuit-level simulation program, to realize
Logical product yield is monitored.
It is simple easy to illustrate on the premise of it can be achieved to monitor logical product yield as specific embodiment,
The monitoring memory cell can be replaced to the storage unit of tradition SRAM test structures in the invention, while according to circuit-level
Simulation program matches the monitoring memory cell with peripheral circuit, and logical product yield is monitored with realizing.Due to the prison
It is more to survey storage unit species, it is preferable that there will be same type monitoring memory cell to be arranged on the logical product yield prison
The same block of geodesic structure, clarifies and senses (Sensing)/load (Loading) matching easy to problem.
It is apparent that the follow-up DFT and test mode of logical product yield monitoring of structures of the present invention can be with traditional SRAM
Test mode is identical, and it will not be described here.
In conclusion logical product yield monitoring of structures of the present invention can not only make up traditional SRAM test structures defect,
And just introduced in the development phase, just to solve Product-level yield issues before product yield imports, it is effectively compressed product volume
The cycle is produced, reaches quick upper amount purpose.
Those skilled in the art, can be to this hair it will be appreciated that without departing from the spirit or scope of the present invention
Bright carry out various modifications and variations.Thus, if any modification or modification fall into the protection of the appended claims and equivalent
In the range of when, it is believed that the present invention covers these modifications and variations.
Claims (8)
- A kind of 1. logical product yield monitoring of structures, it is characterised in that the logical product yield monitoring of structures, including：Monitoring memory cell, the monitoring memory cell by logical operation standard cell design into reverser combination of two shape Into；Peripheral circuit, is matched the monitoring memory cell with peripheral circuit by circuit-level simulation program, to realize to logic Product yield monitors.
- 2. logical product yield monitoring of structures as claimed in claim 1, it is characterised in that the logical product is 28nm/14nm Technology node.
- 3. logical product yield monitoring of structures as claimed in claim 1, it is characterised in that the logical operation standard block can be set Count into the unit of monitoring logical product yield.
- 4. logical product yield monitoring of structures as claimed in claim 3, it is characterised in that the logical operation standard block is NAND structures, AND structures, NOR structures, OR structures.
- 5. logical product yield monitoring of structures as claimed in claim 1, it is characterised in that the device operating voltages of the reverser (Vdd), circuit common ground terminal voltage (Vss) input terminal according to corresponding reverser design be configured.
- 6. logical product yield monitoring of structures as claimed in claim 1, it is characterised in that the species of the reverser is N kinds, two The species for the detection storage unit that two combinations are formed is { N × (N-1)/2！Kind.
- 7. logical product yield monitoring of structures as claimed in claim 1, it is characterised in that there is same type monitoring memory cell It is arranged on the same block of the logical product yield monitoring of structures.
- A kind of 8. design method of logical product yield monitoring of structures as claimed in claim 1, it is characterised in that the logic production The design method of product yield monitoring of structures, including：Perform step S1：It is reverser by logical operation standard cell design；Perform step S2：By by the logical operation standard cell design into reverser, combination of two formed have storage work( The monitoring memory cell of energy；Perform step S3：The monitoring memory cell is matched with peripheral circuit by circuit-level simulation program, to realize to patrolling Collect product yield monitoring.
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| CN201711461971.6A CN107977537A (en) | 2017-12-28 | 2017-12-28 | A kind of logical product yield monitoring of structures and its design method |
Applications Claiming Priority (1)
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| CN201711461971.6A CN107977537A (en) | 2017-12-28 | 2017-12-28 | A kind of logical product yield monitoring of structures and its design method |
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| US20140078799A1 (en) * | 2008-05-09 | 2014-03-20 | William L. Erdman | Inverter modulator with variable switching frequency responsive to a sensed parameter |
| CN105719699A (en) * | 2016-01-15 | 2016-06-29 | 西安紫光国芯半导体有限公司 | DRAM back-end testing yield improvement method |
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|---|---|---|---|---|
| US20140078799A1 (en) * | 2008-05-09 | 2014-03-20 | William L. Erdman | Inverter modulator with variable switching frequency responsive to a sensed parameter |
| CN102637012A (en) * | 2012-04-01 | 2012-08-15 | 深圳市联赢激光股份有限公司 | Double-path power negative feedback system for laser processing equipment |
| CN105719699A (en) * | 2016-01-15 | 2016-06-29 | 西安紫光国芯半导体有限公司 | DRAM back-end testing yield improvement method |
| CN107039441A (en) * | 2016-01-29 | 2017-08-11 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device, integrated circuit structure and semiconductor device |
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| 李二亮: "基于Mix-IS算法的SRAM设计及良率分析", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
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Application publication date: 20180501 |
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