CN1079599A - The method and apparatus of automatic loop control - Google Patents
The method and apparatus of automatic loop control Download PDFInfo
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- CN1079599A CN1079599A CN 93102658 CN93102658A CN1079599A CN 1079599 A CN1079599 A CN 1079599A CN 93102658 CN93102658 CN 93102658 CN 93102658 A CN93102658 A CN 93102658A CN 1079599 A CN1079599 A CN 1079599A
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Abstract
Automatic loop control has dual mode: first kind for example is the loop control signal of using in the phase-locked loop, utilize edge phase sensitive formula phase discriminator with ternary output level to provide, second kind provide out one with the proportional control signal of the error that records.The function of the analogue integrator (EF) that the present invention utilizes is to error (ε d) evaluation of the digital form that records and level and smooth, and above-mentioned functions is controlled by a tristate buffer (TB) that switches with pulse density modulated (PDM) speed.In PDM, use a twisted bus, to increase pulse frequency and to reduce the active time constant of integrator.
Description
The present invention relates to the method and apparatus of automatic loop control.
Realize that automatic loop control can have dual mode.
First kind of mode be as example application in phase-locked loop (PLL), the loop control signal of utilizing edge phase sensitive formula phase discriminator (edges sensitive phase comparator) with ternary output level to provide.The operation principle of this phase discriminator is shown in Fig. 1 a and Fig. 1 b.In each cycle of reference frequency 12 and 22, the output 13 and 23 of phase discriminator is high level 15 or low level 25 in a period of time, this depend on survey input 11 and 21 with benchmark input 12 and 22 between the symbol of phase difference, its size and described phase difference are proportional.Among Fig. 1 a, the input signal leading of surveying in reference-input signal; Among Fig. 1 b, the input signal of surveying lags behind reference-input signal.
In loop control circuit, an external capacitor forms a low pass filter via resistor charge or discharge.When phase discriminator output was high impedance, relevant control store voltages was to this capacitor.Because static phase error equals zero, so resistance, capacitor equivalent are in the effect of integrator.If the work of phase discriminator is carried out continuously, the performance of this kind loop control system is good.If phase demodulation work is for example only carried out in each video line, then in order to try to achieve stability, the response time must be very long.So, to the response of phase hit with variation.
The second way provide out one with the proportional control signal of the error that records.Under the situation that digital error is measured, need the digital-to-analogue conversion function here.This can for example use D/A (DAC), pulse width modulation (PWM) or pulse density modulated (PDM) and realize.The shortcoming of this kind scheme is to lack integral action.Therefore, this phase-locked loop will have static phase error.
The method that an object of the present invention is to disclose the advantage of the comprehensive known method of a kind of energy and improve the automatic loop control circuit.This purpose realizes by adopting automatic loop control method of the present invention, wherein, corresponding output signal after input signal is proofreaied and correct by means for correcting (AD) and the error between the reference signal are by evaluation, and (LSG) removes to control described means for correcting via local signal generator; It is characterized in that described error (ε
d) measure with digital form, be used for controlling buffer unit (TB), the output of buffer unit can switch to a high impedance value, and adds to described local signal generator by integrating gear (EF), wherein, described switching is caused by pulse density modulated device (PDM).
The present invention combines a tristate buffer and the level that switches with PDM speed, provides level and smooth loop control signal.When phase difference when being called the set-point of dead band value, buffer remains on high impedance status.The static phase error of measuring from digital error will be zero.So it is unlimited that the loop DC current gain can reach.Under the situation of PLL, if the phase discriminator that uses provides digital control word to represent phase error
d(digital value), then the present invention can provide and above-mentioned first kind of loop performance that scheme is the same.Non-linear in the error measure can be used for compensation or produce by PDM.
On the principle, method of the present invention includes: an automatic loop control, and wherein, input signal (301) is proofreaied and correct by means for correcting (AD); About the phase error between output signal (303) and the reference signal (304), it by evaluation after remove to control described means for correcting (AD) by local signal generator device (LSG), wherein, described error (ε
d) measure with digital form, and be used for controlling buffer unit (TB), the output of buffer unit (TB) switches to high impedance status, and it arrives described local signal generator device (LSG) by integrating gear (EF), and described switching is caused by the PDM effect.
The plurality of advantages of the additional embodiment of method of the present invention is owing to its many feature draws, described being characterised in that: in described pulse density modulated device (PDM), used a twisted bus;
In described integrating gear (EF), include one or more resistors and capacitor;
Described error (ε
d, 42) sign symbol to described buffer device (TB) as an one input signal;
The polarity of described input signal can utilize a marking signal (41) to give paraphase;
A dead band value (DZV) realizes logical combination in described pulse density modulated device (PDM), in order to control described switching;
Described input signal is made up of the TV signal row, described error ε
dBe that each TV signal row is measured once;
Described pulse density modulated device (PDM) includes the combination of biasing, non-consistent gain, nonlinear functions or these characteristics.
Another object of the present invention is to disclose a kind of a kind of device that utilizes the method for the invention.This purpose realizes by adopting circuit arrangement of the present invention.
On the principle, circuit arrangement of the present invention includes: the means for correcting (AD) of input signal (301); To the error measuring means (EM) that the relevant output signal (303) and the phase error between the reference signal (304) of described means for correcting are measured, wherein said error (ε
d) measure with digital form, and be used for controlling buffer unit (TB), the output of buffer unit switches to high impedance status, it leads to local signal generator device (LSG) by integrating gear (EF), and this local signal generator device is controlled described means for correcting, and wherein said again switching is caused by PDM device (PDM).
The plurality of advantages of the appended embodiment of apparatus of the present invention is because many characteristics of this device obtain.Be characterized in: described pulse density modulated device (PDM) comprises a counter, and it is connected on the comparator via a twisted bus.
Please refer to down accompanying drawing and read the narration of following preferred embodiment of the present invention.
Fig. 1 a and Fig. 1 b illustrate the phase demodulation situation of known phase discriminator;
Fig. 2 illustrates a kind of automatic control loop that adopts the level and smooth loop control of the present invention;
Fig. 3 illustrates from digital error is measured how to receive the loop control signal;
Fig. 4 illustrates the embodiment of first PDM;
Fig. 5 illustrates the embodiment of second PDM.
In Fig. 2, input signal 301 for example is the TV signal of a transmission, and it is fed to input signal correcting circuit AD, and this correcting circuit can include an A/D converter A/D, for input signal with and provide output signal 303.An error measure circuit EM produces digital error word ε according to above-mentioned output signal and a reference signal 304
dReference signal 304 can comprise for example a reference voltage, a reference frequency; Under the phase-locked loop situation of MAC television system, if reference signal is included in the output signal 303, then reference signal also can comprise input signal 301 and/or output signal 303.
In loop control circuit (SLC), the digital error word converts corresponding simulation error value ε to
d, the load of this circuit SLC is a resistor ﹠ capacitor filter EF, this load is connected the outside of the relevant pin of integrated circuit.The work of loop control circuit (SLC) as shown in Figure 3.Local signal generator (LSG) receives filtered simulation error value, controls correcting circuit (AD) according to this.Under the situation of phase-locked loop, local signal generator (LSG) is a voltage controlled oscillator or VCXO, and it provides sampling clock to A/D converter (A/D).Error measure is finished by phase discriminator.
Among Fig. 3, digital error word ε
dBe fed to absolute value circuit (ABS), sign symbol of its output error and absolute value.By means of refined property sign 41, the symbol 42 of error ε can be by anti-phase in XOR gate, and be used as the data input of tristate buffer (TB).Therefore, rely on loop characteristics, can easily make control anti-phase.By evaluation, the output signal 44 of PDM removes to control tristate buffer (TB) to the absolute value of error ε in pulse density modulated circuit (PDM).If output signal 44 for example is zero, then buffer (TB) presents high output impedance, and it can maintain certain hour in the forward stroke interval of a for example television line, and the analogue value is stored among the filter EF.Dead band value (DZV) 43 is presented to pulse density modulated circuit (PDM), so that loop is loose to certain determined value to the reaction of error ε, also promptly so as to introducing hysteresis quality.As (DZV) when equalling zero, only the error ε by (PDM) conversion acts on the output signal 44.
The PDM(pulse density modulated) is a kind of PWM(pulse width modulation) with the counter-rotating bus (inverted bus) from the counter to the comparator.During whole counting, produce the pulse of regular interval.The frequency of counter clock must be higher than ε
dRenewal frequency, with at ε
dEach before and after in time between upgrading, should can finish once complete counter works circulation at least.
Fig. 4 and Fig. 5 illustrate two kinds of different embodiment of pulse density modulated circuit PDM used among Fig. 3.Among Fig. 4, clock CL is counted by a n bit counter C, for example since initial moment counting of a television line.The n bit output cnt of counter
0Cnt
N-1N bit input A with respect to comparator 51
0A
N-1Reversed (twist).The advantage of doing like this is at whole 2 of each circulation inside counting device C of counter
nOutput valve is all scanned then, can form higher pulse frequency, thereby the time constant of integrator can be reduced.The second road n bit of comparator 51 input B is from the absolute value of error ε, its also feed simultaneously input A of second n bit comparator 52.Under linear mode, error n LSB will provide n pulse in duty cycle of counter.The input B of comparator 52 goes up feed-in dead band value (DZV).Counter (C) and comparator 51 are finished the PDM function.Dead band value and PDM signal with door 53 in mutually " with ", (TB) provides impedance control signal 44 to tristate buffer.If | ε | be equal to or less than DZV, buffer output will switch to high impedance value.If | ε | greater than DZV, buffer output is switched with PDM speed between error symbol (if polar end 41=" 1 " then is opposite symbol) and high impedance; The number of pulse equals | ε |.
Among Fig. 5, clock CL is also counted by n bit counter (C).The n bit of counter output reverses accordingly with respect to the n bit input A of adder 61.The n bit input B of adder 61 goes up feed-in dead band value DZV.Overflow in the output of this adder under the situation of n bit range, in amplitude limiter circuit (CP), be limited.The output of this amplitude limiter circuit and error ε compare in comparator 62.Have only error (DZV+n LSB) will in duty cycle of counter, provide n output pulse 63.
Because digitally coded error amount makes the reaction speed of loop can be easily modulated according to the amplitude of error ε.By set up a look-up table or increase any allly if can make that the PDM effect produces biasing, non-ly consistently gains, the further feature of nonlinear functions or the combination of these several specific characters, just can revise this modulation, but must select this function to satisfy stability criterion; Can know that the combination of resistor ﹠ capacitor filter and buffer high impedance level is equivalent to an integrator.
Almost all handling is the pure digi-tal formula.The D/A function is realized by PDM; When buffer (TB) be outputted to high impedance the time, the PDM pulse is carried out filtering by the resistor ﹠ capacitor filter that plays the memory effect.This means that the present invention can be used for having the automatic loop control of unlimited loop DC current gain (static receiver error equals zero).This automatic loop control can easily be integrated in the integrated circuit of a pure digi-tal.
The present invention can be applied to have in arbitrary automatic control loop of digital error measurement result, for example:
Clamp (DC level regeneration);
The control of AGC(automatic gain);
The PLL(clock regeneration).
The present invention can be applied to handle in the receiver or miscellaneous equipment of TV signal, for example:
The TV of digital transmission, the advanced television standard;
MAC family comprises GDMAC, MUSE;
HDTV;
PAL, SECAM, NTSC with digital performance.
Claims (10)
1, a kind of automatic loop control method, wherein, input signal (301) is proofreaied and correct by means for correcting (AD), and the phase error between corresponding output signal (303) and the reference signal (304) is by evaluation, and (LSG) controls described means for correcting via local signal generator; It is characterized in that described error (ε
d) measure with digital form, be used for controlling buffer unit (TB), the output of buffer unit can switch to a high impedance value, and leads to described local signal generator by integrating gear (EF), wherein, described switching is caused by pulse density modulated device (PDM).
2, according to the method described in the claim 1, it is characterized in that, in described pulse density modulated device (PDM), used a twisted bus.
3, method according to claim 1 and 2 is characterized in that, in described integrating gear (EF), includes one or more resistors and capacitor.
4, according to described any method of claim 1 to 3, it is characterized in that described error (ε
d, 42) an input signal of the described buffer device of symbol (TB).
5, method according to claim 4 is characterized in that, the polarity of described input signal can utilize a sign (41) to give anti-phase.
According to each described method in the claim 1 to 5, it is characterized in that 6, a dead band value (DZV) is carried out logical combination in described pulse density modulated device (PDM), in order to control described switching.
7, according to each described method in the claim 1 to 6, it is characterized in that described input signal is made up of the TV signal row, described error ε
dMeasure once at each TV signal row.
According to each described method in the claim 1 to 7, it is characterized in that 8, described pulse density modulated device (PDM) includes the combination of biasing or non-consistent gain or nonlinear functions or these characteristics.
9, a kind of circuit arrangement that is used for according to each described method of claim 1 to 8, it is characterized in that comprising for a means for correcting (AD) of input signal (301) usefulness and the error measuring means (EM) that the phase error between described means for correcting corresponding output signal (303) and the reference signal (304) is measured, wherein, described error (ε
d) measure with digital form, be used for controller buffer device (TB), the output of buffer can switch to a high impedance value, and lead to local signal generator (LSG) by integrating gear (EF), this local signal generator removes to control described means for correcting, wherein, described switching is caused by pulse density modulated device (PDM).
10, circuit arrangement according to claim 9 is characterized in that, described pulse density modulated device (PDM) includes a counter (C), and it is connected on the comparator (51,61) via a twisted bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93102658A CN1032889C (en) | 1992-03-18 | 1993-03-16 | Method and apparatus for automatic loop control |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR92400735.4 | 1992-03-18 | ||
| CN93102658A CN1032889C (en) | 1992-03-18 | 1993-03-16 | Method and apparatus for automatic loop control |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1079599A true CN1079599A (en) | 1993-12-15 |
| CN1032889C CN1032889C (en) | 1996-09-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN93102658A Expired - Fee Related CN1032889C (en) | 1992-03-18 | 1993-03-16 | Method and apparatus for automatic loop control |
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| Country | Link |
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| CN (1) | CN1032889C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829085B (en) * | 2005-04-15 | 2010-05-12 | 开曼群岛威睿电通股份有限公司 | Tri-state pulse density modulator |
| CN102195622A (en) * | 2010-03-10 | 2011-09-21 | Nxp股份有限公司 | Pulse density modulation method and apparatus |
| CN106571813A (en) * | 2015-10-09 | 2017-04-19 | 张伟林 | Novel edge-type high-resistance digital phase discriminator |
| CN106571815A (en) * | 2015-10-09 | 2017-04-19 | 张伟林 | Level-type high-resistance digital phase discriminator |
-
1993
- 1993-03-16 CN CN93102658A patent/CN1032889C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829085B (en) * | 2005-04-15 | 2010-05-12 | 开曼群岛威睿电通股份有限公司 | Tri-state pulse density modulator |
| CN102195622A (en) * | 2010-03-10 | 2011-09-21 | Nxp股份有限公司 | Pulse density modulation method and apparatus |
| CN106571813A (en) * | 2015-10-09 | 2017-04-19 | 张伟林 | Novel edge-type high-resistance digital phase discriminator |
| CN106571815A (en) * | 2015-10-09 | 2017-04-19 | 张伟林 | Level-type high-resistance digital phase discriminator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1032889C (en) | 1996-09-25 |
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Granted publication date: 19960925 Termination date: 20100316 |