CN107947787A - A kind of system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter - Google Patents

A kind of system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter Download PDF

Info

Publication number
CN107947787A
CN107947787A CN201711165106.7A CN201711165106A CN107947787A CN 107947787 A CN107947787 A CN 107947787A CN 201711165106 A CN201711165106 A CN 201711165106A CN 107947787 A CN107947787 A CN 107947787A
Authority
CN
China
Prior art keywords
mrow
mover
phase
msup
omega
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711165106.7A
Other languages
Chinese (zh)
Inventor
蒋珺
王成胜
段巍
李凡
兰志明
杨琼涛
唐磊
赵悦
苑莉
王盼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Aritime Intelligent Control Co Ltd
Original Assignee
Beijing Aritime Intelligent Control Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Aritime Intelligent Control Co Ltd filed Critical Beijing Aritime Intelligent Control Co Ltd
Priority to CN201711165106.7A priority Critical patent/CN107947787A/en
Publication of CN107947787A publication Critical patent/CN107947787A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
    • H02M5/40—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc
    • H02M5/42—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters
    • H02M5/44—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac
    • H02M5/453—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M5/458—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M5/4585—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only having a rectifier with controlled elements

Abstract

The invention discloses a kind of system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter, belong to high-power three-level back-to-back PWM converter field.The adaptive phase locked loop method provided in the present invention refers to according to the current situation of power grid, can interpolate that and selects a kind of higher phase-locked loop method of efficiency.Under grid balance state, selection uses zero passage phase-locked loop method, and the method is based primarily upon voltage complete period conversion circuit, by catching voltage zero-crossing point of power grid, reduces procedure quantity.When power grid undergos mutation and becomes asymmetry, the failure of zero passage phase-locked loop method, selects the phase-locked loop method based on double Second Order Generalized Integrators to ensure real-time and accurately to obtain the phase angle and frequency of power grid at this time.The present invention can substantially increase the work efficiency and accuracy rate of control system using adaptive phase locked loop method, while its rapidity is ensured, make control system operation more reliable and more stable.

Description

A kind of system self-adaption applied to high-power three-level back-to-back PWM converter is locked Phase ring method
Technical field
The invention belongs to high-power three-level back-to-back PWM converter field, and in particular to one kind is applied to high-power three The system self-adaption phase-locked loop method of level back-to-back PWM converter.
Background technology
With the continuous development of electric electronic current change technology, electronic power convertor is led in metallurgical, locomotive more and more Draw, the field such as flexible transmission, energy storage devices, harmonics and reactive compensation device, Switching Power Supply, electric automobile, household electrical appliance Obtain important application.The problem of high-power high voltage current transformer is run at present mainly include be difficult to realize braking energy feedback power grid, Grid side current harmonics is big, grid side power factor is low, current transformer commutation course is complicated, DC bus-bar voltage is by supply and AC electricity Operating voltage that pressure limits and cannot provide higher for load etc..
It is the problem that existing most of current transformer is faced to realize four quadrant running, using diode and thyristor The current transformer of rectification may only carry out unidirectional flow of power, and the energy for loading feedback can only be by the copped wave electricity of dc bus side Road is discharged in the form of resistance thermal energy, just has to consider asking for energy feedback especially in the occasion for needing frequent acceleration and deceleration Topic, otherwise largely braking electric energy is converted into useless thermal energy, not only causes energy waste, but also bring shakiness to system operation Fixed factor.
Low net side power factor is also the big problem that is faced of current current transformer, using diode or thyristor rectifier Current transformer can make network side current waveform Severe distortion, cause power factor relatively low, highest power factor is only possible to left for 0.8 It is right.The consumption of a large amount of reactive powers can bring extra burden to power grid, not only increase the loss of transmission line of electricity, and seriously Ground have impact on power supply quality.
The high-power back-to-back PWM Voltage type converters of tri- level of IGCT are approximate with four-quadrant operation, current on line side with it The characteristics such as sine and power factor are controllable are subject to the extensive concern of scholars.In the control system of three-level pwm current transformer, The main purpose of design phaselocked loop is to obtain the phase angle of power grid and frequency, and can make output result tracking is upper actual true in time Value, so as to facilitate the implementation of control strategy and control algolithm.It is that laboratory condition (or is referred to as to manage that three phase network is full symmetric Think state), power grid is all balance when most of, however, in practical engineering application, power grid also inevitably occurs that some are non- Ideal situation, such as three-phase power grid voltage are uneven, and the phase angle of power grid changes suddenly, a certain phase voltage is fallen, it is short to occur Road failure, frequency discontinuity etc., remain that PWM converter can adapt to these situation safe and stable operations at this time.For reality This existing target, phaselocked loop export the important prerequisite that accurate power grid angle is system worked well, and the performance of phaselocked loop is direct The control performance of PWM converter is influenced, therefore just needs to have performance more preferably PHASE-LOCKED LOOP PLL TECHNIQUE.
The content of the invention
The purpose of the present invention is to propose to a kind of system self-adaption lock applied to high-power three-level back-to-back PWM converter Phase ring method, in order to reach the rapidity of calculating and accuracy, whether phase-locked loop module can quickly identify power grid in balance State simultaneously selects a kind of maximally efficient phase-locked loop method, thus real-time and precise track grid phase, be whole current transformer control System processed is submitted necessary information, and realizes system stable operation.
The adaptive phase locked loop method provided in the present invention, refers to, according to the current situation of power grid, can interpolate that and select A kind of higher phase-locked loop method of efficiency.Under grid balance state, selection uses zero passage phase-locked loop method, the main base of the method In voltage complete period conversion circuit, by catching voltage zero-crossing point of power grid, procedure quantity is reduced.Become not when power grid is undergone mutation When symmetrical, the failure of zero passage phase-locked loop method, selects the phase-locked loop method based on double Second Order Generalized Integrators to ensure reality at this time When obtain the phase angle and frequency of power grid exactly.
The zero passage phase-locked loop method, the sinusoidal signal of supply voltage is through overvoltage complete period conversion circuit, sine letter Number square-wave signal is converted into, exports high level when voltage is in positive half period, when negative half-cycle exports low level, output waveform It is input in digital processing unit CPU；CPU gathers zero cross signal at positive zero crossing k π, while forms rising edge pulse and open Dynamic counter, which is begun counting up, receives next rising edge pulse arrival, and CPU is emptied after next pulse signal is received Counter simultaneously starts counting up again, is exported so that sinusoidal voltage phase is changed into lock phase triangular wave, that is, network voltage Phase information.
The phase-locked loop method based on double Second Order Generalized Integrators：
First to three-phase power grid voltage vector VabcProgress Clark converts to obtain two component v in two-phase rest frameα And vβ；Positive-sequence component is extracted by improved SOGI-QSG respectively from the network voltage under two-phase rest frameWith
Then transformation (α β-dq) of the rest frame to synchronous coordinate system is carried out, i.e. Park conversion, obtains positive-sequence component With
Again willPi regulator is inputted, when Frequency Locking,For a DC quantity, pi regulator has direct current floating tune Characteristic is saved, therefore by rightPI adjust, can makeTend to 0, so as to achieve the purpose that to lock phase, output and the electricity of pi regulator Net reference frequency ωffIt is added, is denoted as frequencies omega0.By frequencies omega0Improved SOGI-QSG is fed back to as resonant frequency；Will frequency Rate ω0The angle, θ obtained by common integrator+′As the rotation angle needed for Park conversion, the phaselocked loop side being thusly-formed The closed loop DAZ gene of power network signal finally can be achieved in method.
Compared with the prior art, its major advantage is the present invention：
Traditional phase-locked loop module can only use single method, can not be switched over for particular problem, cause to use The limitation either wasting of resources.This deficiency can effectively be evaded using adaptive phase locked loop method, substantially increase control system The work efficiency and accuracy rate of system, while its rapidity is ensured, make control system operation more reliable and more stable.
Brief description of the drawings
Fig. 1 is three level back-to-back PWM converter system construction drawings；
Fig. 2 is adaptive phase locked loop method flow schematic diagram in the present invention；
Fig. 3 is simulation model of the zero passage phaselocked loop in MATLAB；
Fig. 4 is the schematic diagram of zero passage phase-locked loop method；
Fig. 5 is a kind of improved orthogonal signal generator (abbreviation SOGI-QSG) based on Second Order Generalized Integrator；
Fig. 6 is improved phaselocked loop (abbreviation DSOGI-PLL) control structure block diagram based on double Second Order Generalized Integrators.
Embodiment
Phase-locked loop method provided by the invention mainly includes operation of power networks situation and judges and adapt to that the matching of each situation improves Type algorithm.Below in conjunction with the accompanying drawings, to a kind of system applied to high-power three-level back-to-back PWM converter provided by the invention Adaptive phase locked loop method illustrates.
Fig. 1 is three level back-to-back PWM converter system construction drawings.Using DSP as main control chip, receive and adopted from AD The three-phase primary voltage u that model collectssABC, inlet wire current (ia,ib,ic) and DC voltage signal (udc1,udc2) and make Respective handling, phase-lock-loop algorithm, rectifier double-loop control strategy and three level SVPWM algorithms are completed in dsp, finally Export 6 tunnel pulses.The function of fpga chip is mainly pulse distribution, minimum pulse width and the processing in dead band, it is ensured that each power Switching tube effectively conducting and shut-off.In order to strengthen Man machine interaction, all control signals are incorporated on touch-screen simultaneously real The real-time display of existing parameter and adjustment.
Fig. 2 is the adaptive phase locked loop method provided by the invention applied to high-power three-level back-to-back PWM converter Flow diagram, the adaptive phase locked loop method, first AD sampling plates collection three-phase power grid voltage usABC, utilize DSP journeys Sequence judges whether electric network state balances, and zero passage phase-locked loop method is selected under grid balance state, directly reads the output of AD sampling plates Power grid phase angle, this method procedure quantity is less, effectively can quickly track power grid.Become not releveling when fluctuation occurs for power grid When, zero passage phaselocked loop can not meet application demand, and control system, which automatically switches, selects the lock phase based on double Second Order Generalized Integrators Ring method, this method are still able to ensure that the accuracy and rapidity of tracking electric network information in the case where power grid is mutated, make control The reliable and stable operation of system processed.
Fig. 3 is the simulation model of zero passage phase-locked loop module established in Matlab simulation softwares, the time delay module in Fig. 3 Analog voltage complete period conversion circuit, edging trigger module, counting module and pulse signal generator form voltage zero-cross processing Device (CPU), edging trigger module be used for CPU catch rising edge signal, pulse signal generator be the system crystal oscillator of CPU (i.e. For the clock of counting module, whether oscillograph B is used for watchdog pulse signal correct), in the counting clock of pulse signal generator Under cycle, CPU from capture a rising edge signal start counting up it is cumulative, until next rising edge signal arrive reset again Count, so as to form lock phase triangular wave.Exported after triangular signal amplifies K times with sinusoidal signal, voltage complete period conversion circuit Shown together on oscillograph A, easy to observe contrast.This phase-locked loop structures are a kind of open loop lock phase skills the most simple and effective Art, can rapidly and accurately lock the phase of network voltage under grid balance state.
Fig. 4 is the schematic diagram of zero passage phase-locked loop method, and main function is each of seizure supply voltage (A phases) sinusoidal waveform A zero crossing, then just obtains corresponding frequency by the time interval of two neighboring zero crossing is inverted, so as to reach tracking phase The purpose of position.Sine voltage signal [+2 π of k π, k π) during include two zero crossings, first step voltage complete period conversion circuit Sinusoidal signal is converted into square-wave signal, exports high level when voltage is in positive half period, when negative half-cycle, exports low level, Output waveform is input in digital processing unit CPU；Second step CPU gathers zero cross signal, while pulse at positive zero crossing k π Signal generator, which forms rising edge pulse signal and starts counter, begins counting up the next rising edge pulse signal of reception Arrive, CPU empties counter after next rising edge pulse signal is received and start counting up again, so that by sinusoidal voltage Phase changes into the triangular wave output of lock phase, that is, the phase information of network voltage.
Fig. 5 (referred to as changes for a kind of improved orthogonal signal generator based on Second Order Generalized Integrator provided by the invention Into SOGI-QSG) model in s domains, v (s) represents the input of orthogonal signal generator, frequency ω in figure；v′(s)、 Qv ' (s) represents two outputs of orthogonal signal generator；εv(s) error amount (ε is representedv(s)=v (s)-v'(s))；K represents to increase Benefit, fault in enlargement signal, easy to control；kεv(s) input as SOGI is subtracted each other with feedback signal qv ' (s)；Represent that second order is wide The resonant frequency of adopted integrator (SOGI), s is complex variable, also referred to as complex frequency.The then input and output of the orthogonal signal generator Transmission function D (s), Q (s) in s domains can be expressed as：
The sinusoidal signal v (s) that frequency is ω is expressed as vectorForm, similarlyRepresent D (s),Represent Q (s),Represent v'(s),Represent qv'(s) vector form, then by formula (1), formula (2) can calculate improve after SOGI-QSG width Frequency and phase-frequency characteristic：
During stable stateThenIt is that the sinusoidal of ω is believed that this, which shows that system can be realized to frequency in Setting signal, Number DAZ gene.In addition, by vector in formula (4)Angle relationshipIt is not difficult to find out, qv ' is total Be than 90 ° of v ' hysteresis and with k,ω is unrelated, that is, exports signal v ' and qv ' is orthogonal.When the resonant frequency of Second Order Generalized IntegratorWith ω it is unequal when, Second Order Generalized Integrator output signal amplitude and phase tracking error occurs, will can lock for this Resonant frequency of the frequency that phase ring obtains as Second Order Generalized Integrator, it is adaptive that such Second Order Generalized Integrator also achieves frequency The function of answering.The passband of system is wider after improvement, and in phase locking process, system is easily stablized.K values are smaller, and filter effect is got over It is good, but response speed can be influenced, therefore compromise and chooseEven in voltage distortion, frequency discontinuity, rich in unreasonablys such as harmonic waves In the case of thinking, SOGI-QSG still has good band-pass filtering property, and preferable steady-state behaviour and dynamic property after improvement.
Fig. 6 is improved phaselocked loop (the Double Second Order based on double Second Order Generalized Integrators Generalized Integrator Phase Locking Loop, abbreviation DSOGI-PLL) control structure block diagram, when voltage not During balance, using symmetrical component method, by three-phase power grid voltage vector VabcIn positive-sequence componentExtract, be now in three In phase coordinate system (being known as abc coordinate systems), Clark conversion (abc- α β) is then carried out, then two-phase rest frame (is known as α β to sit Mark system) under network voltage positive-sequence componentIt is represented by：
In formulaExpression carries out original signal in time domain 90 ° of relative displacement (hysteresis)；[Tαβ] represent Clark Transformation matrix；[T+] represent decomposition transform matrix；[Vαβ] represent two-phase rest frame under network voltage vector.
From formula (5), the extraction to network voltage positive-sequence component is completed, it is necessary to carry out 90 ° to input voltage signal Phase angle shift, two-phase quadrature voltage signal is obtained with this.In general, this 90 ° of phase angle shifts based on sinusoidal signal can be with Using schemes such as cycle delay, differential and all-pass filters, but change response of these schemes to frequency is slower, especially Differential scheme is more sensitive to voltage harmonic, can use 90 ° of phase angle shift schemes based on Second Order Generalized Integrator (SOGI) for this To produce two-phase orthogonal signal, this scheme can not only realize 90 ° of phase angle shifts to input voltage signal, can also filter out Higher hamonic wave.
Therefore in Fig. 6, the first step is first to three-phase power grid voltage vector VabcClark is carried out to convert to obtain two-phase static coordinate Two component v in systemαAnd vβ；Second step extracts output v' by improved SOGI-QSGα、qv'αAnd v'β、qv'β, according to public affairs Formula (5), further can extract positive-sequence component from the network voltage under rest frameWithDue to actual power grid Voltage is oriented with the d axis in synchronous coordinate system (being known as dq coordinate systems), when phaselocked loop accurately tracks grid phase, q axis point Measure as 0, so the 3rd step carries out the transformation (α β-dq) that rest frame arrives synchronous coordinate system, i.e. Park converts (TdqBecome for Park Change matrix)；4th step, willPi regulator is inputted, when Frequency Locking,For a DC quantity, pi regulator have direct current without Static difference control characteristic, therefore by rightPI adjust, can makeTend to 0, thus achieve the purpose that lock phase, pi regulator it is defeated Go out and power grid rated frequency ωffIt is added (ωffAs feedforward term, Phase Locked Loop Synchronization can be accelerated to pull in speed), it is denoted as frequencies omega0, By frequencies omega0Improved SOGI-QSG is fed back to as resonant frequency, then the angle, θ obtained by integration+′Converted as Park The closed loop DAZ gene to power network signal finally can be achieved in required rotation angle, the phase-locked loop method being thusly-formed.

Claims (4)

  1. A kind of 1. system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter, it is characterised in that： The system self-adaption phase-locked loop method, according to the current situation of power grid, under grid balance state, selects to lock using zero passage Phase ring method；When power grid undergos mutation and becomes asymmetry, the failure of zero passage phase-locked loop method, is selected wide based on double second orders at this time The phase-locked loop method of adopted integrator.
  2. 2. a kind of system self-adaption applied to high-power three-level back-to-back PWM converter according to claim 1 is locked Phase ring method, it is characterised in that：The zero passage phase-locked loop method, the sinusoidal signal of supply voltage are changed through the overvoltage complete period Circuit, sinusoidal signal are converted into square-wave signal, export high level when voltage is in positive half period, and when negative half-cycle exports low electricity Flat, output waveform is input in digital processing unit CPU；Digital processing unit CPU gathers zero cross signal at positive zero crossing k π, together When form rising edge pulse and start counter and begin counting up and receive next rising edge pulse and arrive, digital processing unit CPU empties counter after next pulse signal is received and starts counting up again, so that sinusoidal voltage phase be changed into Lock the output of phase triangular wave, that is, the phase information of network voltage.
  3. 3. a kind of system self-adaption applied to high-power three-level back-to-back PWM converter according to claim 1 is locked Phase ring method, it is characterised in that：The phase-locked loop method based on double Second Order Generalized Integrators：
    First to three-phase power grid voltage vector VabcProgress Clark converts to obtain two component v in two-phase rest frameαAnd vβ； Positive-sequence component is further extracted by improved SOGI-QSG respectively from the network voltage under two-phase rest frameWith
    Then transformation (α β-dq) of the rest frame to synchronous coordinate system is carried out, i.e. Park conversion, obtains positive-sequence componentWith
    Again willPi regulator is inputted, when Frequency Locking,For a DC quantity, pi regulator has direct current floating regulation spy Property, therefore by rightPI adjust, makeTend to 0, so as to achieve the purpose that to lock phase, output and the power grid benchmark of pi regulator Frequencies omegaffIt is added, is denoted as frequencies omega0；By frequencies omega0Improved SOGI-QSG is fed back to as resonant frequency；By frequencies omega0Through Cross the angle, θ that common integrator obtains+′As the rotation angle needed for Park conversion, the phase-locked loop method being thusly-formed finally may be used Realize the closed loop DAZ gene to power network signal.
  4. 4. a kind of system self-adaption applied to high-power three-level back-to-back PWM converter according to claim 3 is locked Phase ring method, it is characterised in that：The improved SOGI-QSG, the input and output of the orthogonal signal generator are in s domains Transmission function D (s), Q (s) are expressed as：
    <mrow> <mi>D</mi> <mrow> <mo>(</mo> <mi>s</mi> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <mrow> <msup> <mi>v</mi> <mo>&amp;prime;</mo> </msup> <mrow> <mo>(</mo> <mi>s</mi> <mo>)</mo> </mrow> </mrow> <mrow> <mi>v</mi> <mrow> <mo>(</mo> <mi>s</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>=</mo> <mfrac> <mrow> <mi>k</mi> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mi>s</mi> </mrow> <mrow> <msup> <mi>s</mi> <mn>2</mn> </msup> <mo>+</mo> <mi>k</mi> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mi>s</mi> <mo>+</mo> <msup> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mn>2</mn> </msup> </mrow> </mfrac> <mo>-</mo> <mo>-</mo> <mo>-</mo> <mrow> <mo>(</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow>
    <mrow> <mi>Q</mi> <mrow> <mo>(</mo> <mi>s</mi> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <mrow> <msup> <mi>qv</mi> <mo>&amp;prime;</mo> </msup> <mrow> <mo>(</mo> <mi>s</mi> <mo>)</mo> </mrow> </mrow> <mrow> <mi>v</mi> <mrow> <mo>(</mo> <mi>s</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>=</mo> <mfrac> <mrow> <mi>k</mi> <msup> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mn>2</mn> </msup> </mrow> <mrow> <msup> <mi>s</mi> <mn>2</mn> </msup> <mo>+</mo> <mi>k</mi> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mi>s</mi> <mo>+</mo> <msup> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mn>2</mn> </msup> </mrow> </mfrac> <mo>-</mo> <mo>-</mo> <mo>-</mo> <mrow> <mo>(</mo> <mn>2</mn> <mo>)</mo> </mrow> </mrow>
    Wherein, v (s) represents the input of orthogonal signal generator；V'(s), qv ' (s) represent two of orthogonal signal generator it is defeated Go out；K represents gain；kεv(s) input as SOGI is subtracted each other with feedback signal qv ' (s)；εv(s)=v (s)-v'(s),Represent The resonant frequency of Second Order Generalized Integrator, s are complex variable；The sinusoidal signal v (s) that frequency is ω is then expressed as vector's Form, similarlyRepresent D (s),Represent Q (s),Represent v'(s),Represent qv ' (s) vector form, then by formula (1), Formula (2) calculates the amplitude-frequency and phase-frequency characteristic of SOGI-QSG after improvement：
    <mrow> <mover> <msup> <mi>v</mi> <mo>&amp;prime;</mo> </msup> <mo>&amp;OverBar;</mo> </mover> <mo>=</mo> <mover> <mi>D</mi> <mo>&amp;OverBar;</mo> </mover> <mover> <mi>v</mi> <mo>&amp;OverBar;</mo> </mover> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <mo>|</mo> <mover> <mi>D</mi> <mo>&amp;OverBar;</mo> </mover> <mo>|</mo> <mo>=</mo> <mfrac> <mrow> <mi>k</mi> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mi>&amp;omega;</mi> </mrow> <msqrt> <mrow> <msup> <mrow> <mo>(</mo> <mi>k</mi> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mi>&amp;omega;</mi> <mo>)</mo> </mrow> <mn>2</mn> </msup> <mo>+</mo> <msup> <mrow> <mo>(</mo> <msup> <mi>&amp;omega;</mi> <mn>2</mn> </msup> <mo>-</mo> <msup> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mn>2</mn> </msup> <mo>)</mo> </mrow> <mn>2</mn> </msup> </mrow> </msqrt> </mfrac> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <mo>&amp;angle;</mo> <mover> <mi>D</mi> <mo>&amp;OverBar;</mo> </mover> <mo>=</mo> <mi>a</mi> <mi>r</mi> <mi>c</mi> <mi>t</mi> <mi>a</mi> <mi>n</mi> <mrow> <mo>(</mo> <mfrac> <mrow> <msup> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mn>2</mn> </msup> <mo>-</mo> <msup> <mi>&amp;omega;</mi> <mn>2</mn> </msup> </mrow> <mrow> <mi>k</mi> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mi>&amp;omega;</mi> </mrow> </mfrac> <mo>)</mo> </mrow> </mrow> </mtd> </mtr> </mtable> </mfenced> <mo>-</mo> <mo>-</mo> <mo>-</mo> <mrow> <mo>(</mo> <mn>3</mn> <mo>)</mo> </mrow> </mrow>
    <mrow> <mover> <mrow> <msup> <mi>qv</mi> <mo>&amp;prime;</mo> </msup> </mrow> <mo>&amp;OverBar;</mo> </mover> <mo>=</mo> <mover> <mi>Q</mi> <mo>&amp;OverBar;</mo> </mover> <mover> <mi>v</mi> <mo>&amp;OverBar;</mo> </mover> <mfenced open = "{" close = ""> <mtable> <mtr> <mtd> <mrow> <mo>|</mo> <mover> <mi>Q</mi> <mo>&amp;OverBar;</mo> </mover> <mo>|</mo> <mo>=</mo> <mfrac> <mover> <mi>&amp;omega;</mi> <mo>^</mo> </mover> <mi>&amp;omega;</mi> </mfrac> <mo>|</mo> <mover> <mi>D</mi> <mo>&amp;OverBar;</mo> </mover> <mo>|</mo> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow> <mo>&amp;angle;</mo> <mover> <mi>Q</mi> <mo>&amp;OverBar;</mo> </mover> <mo>=</mo> <mo>&amp;angle;</mo> <mover> <mi>D</mi> <mo>&amp;OverBar;</mo> </mover> <mo>-</mo> <mfrac> <mi>&amp;pi;</mi> <mn>2</mn> </mfrac> </mrow> </mtd> </mtr> </mtable> </mfenced> <mo>-</mo> <mo>-</mo> <mo>-</mo> <mrow> <mo>(</mo> <mn>4</mn> <mo>)</mo> </mrow> </mrow>
    During stable stateThenIt is the sinusoidal signal of ω that this, which shows that system can be realized to frequency in Setting signal, DAZ gene；When the resonant frequency of Second Order Generalized IntegratorWith ω it is unequal when, frequencies omega that phaselocked loop is obtained0As The resonant frequency of Second Order Generalized Integrator.
CN201711165106.7A 2017-11-21 2017-11-21 A kind of system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter Pending CN107947787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711165106.7A CN107947787A (en) 2017-11-21 2017-11-21 A kind of system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711165106.7A CN107947787A (en) 2017-11-21 2017-11-21 A kind of system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter

Publications (1)

Publication Number Publication Date
CN107947787A true CN107947787A (en) 2018-04-20

Family

ID=61929573

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711165106.7A Pending CN107947787A (en) 2017-11-21 2017-11-21 A kind of system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter

Country Status (1)

Country Link
CN (1) CN107947787A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108599165A (en) * 2018-05-16 2018-09-28 哈尔滨理工大学 Three level active filters, its application system and method based on Compound Control Strategy
CN109412191A (en) * 2018-12-05 2019-03-01 华南理工大学 A kind of phase-lock technique, device and equipment for HVDC transmission system
CN109524963A (en) * 2018-11-05 2019-03-26 中国大唐集团科学技术研究院有限公司华东电力试验研究院 A kind of DSOGI phaselocked loop based on differential harmonic elimination
CN109617550A (en) * 2018-11-27 2019-04-12 深圳市鼎泰佳创科技有限公司 The control method of single-phase phase-locked loop based on Second Order Generalized Integrator
CN110854888A (en) * 2019-10-16 2020-02-28 安徽兆晟新能源科技有限公司 Improved control method of energy storage converter based on generalized second-order integrator under weak grid
CN111273093A (en) * 2020-02-25 2020-06-12 固德威电源科技(广德)有限公司 Phase sequence identification and phase locking method for three-phase grid-connected inverter
CN112421665A (en) * 2020-11-09 2021-02-26 西安热工研究院有限公司 MMC interconnection converter alternating current phase-locked loop control method
CN116405026A (en) * 2023-06-08 2023-07-07 四川大学 Multiphase second-order generalized integrator phase-locked loop and implementation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030121307A1 (en) * 2000-12-14 2003-07-03 Frank Schmid Method for adjusting the phase-locking loop of an electronic evaluation device and corresponding electronic evaluation device
CN104410408A (en) * 2014-12-25 2015-03-11 国家电网公司 Single phase locking method and device
CN104702113A (en) * 2015-02-16 2015-06-10 湘潭大学 Device and method for realizing ZVC (Zero Voltage Switching) soft switch based on frequency tracking
CN105158597A (en) * 2015-08-05 2015-12-16 西南交通大学 Method for improving power grid voltage phase monitoring dynamic performance of single-phase digital phase-locked loop

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030121307A1 (en) * 2000-12-14 2003-07-03 Frank Schmid Method for adjusting the phase-locking loop of an electronic evaluation device and corresponding electronic evaluation device
CN104410408A (en) * 2014-12-25 2015-03-11 国家电网公司 Single phase locking method and device
CN104702113A (en) * 2015-02-16 2015-06-10 湘潭大学 Device and method for realizing ZVC (Zero Voltage Switching) soft switch based on frequency tracking
CN105158597A (en) * 2015-08-05 2015-12-16 西南交通大学 Method for improving power grid voltage phase monitoring dynamic performance of single-phase digital phase-locked loop

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
张兴等: "PWM整流器及其控制", 《PWM整流器及其控制》 *
蒋珺: "大功率三电平PWM整流器的研究与设计", 《中国优秀硕士学位论文全文数据库工程科技Ⅱ辑》 *

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108599165A (en) * 2018-05-16 2018-09-28 哈尔滨理工大学 Three level active filters, its application system and method based on Compound Control Strategy
CN108599165B (en) * 2018-05-16 2022-06-17 哈尔滨理工大学 Three-level active filter based on composite control strategy, application system and method thereof
CN109524963A (en) * 2018-11-05 2019-03-26 中国大唐集团科学技术研究院有限公司华东电力试验研究院 A kind of DSOGI phaselocked loop based on differential harmonic elimination
CN109617550A (en) * 2018-11-27 2019-04-12 深圳市鼎泰佳创科技有限公司 The control method of single-phase phase-locked loop based on Second Order Generalized Integrator
CN109617550B (en) * 2018-11-27 2023-07-07 深圳市鼎泰佳创科技有限公司 Control method of single-phase-locked loop based on second-order generalized integrator
CN109412191B (en) * 2018-12-05 2021-06-11 华南理工大学 Phase locking method, device and equipment for high-voltage direct-current power transmission system
CN109412191A (en) * 2018-12-05 2019-03-01 华南理工大学 A kind of phase-lock technique, device and equipment for HVDC transmission system
CN110854888A (en) * 2019-10-16 2020-02-28 安徽兆晟新能源科技有限公司 Improved control method of energy storage converter based on generalized second-order integrator under weak grid
CN110854888B (en) * 2019-10-16 2023-09-01 安徽兆晟新能源科技有限公司 Improved control method of energy storage converter based on generalized second-order integrator under weak current network
CN111273093A (en) * 2020-02-25 2020-06-12 固德威电源科技(广德)有限公司 Phase sequence identification and phase locking method for three-phase grid-connected inverter
CN111273093B (en) * 2020-02-25 2022-05-10 固德威电源科技(广德)有限公司 Phase sequence identification and phase locking method for three-phase grid-connected inverter
CN112421665A (en) * 2020-11-09 2021-02-26 西安热工研究院有限公司 MMC interconnection converter alternating current phase-locked loop control method
CN112421665B (en) * 2020-11-09 2023-02-24 西安热工研究院有限公司 MMC interconnection converter alternating current phase-locked loop control method
CN116405026A (en) * 2023-06-08 2023-07-07 四川大学 Multiphase second-order generalized integrator phase-locked loop and implementation method thereof
CN116405026B (en) * 2023-06-08 2023-08-22 四川大学 Multiphase second-order generalized integrator phase-locked loop and implementation method thereof

Similar Documents

Publication Publication Date Title
CN107947787A (en) A kind of system self-adaption phase-locked loop method applied to high-power three-level back-to-back PWM converter
CN106100402B (en) A kind of T-type three-level inverter and its neutral balance control method
CN101951174B (en) Constant-frequency direct power control method for PWM converter under condition of power grid voltage imbalance
CN103475033B (en) Current control method and system for three-phase LCL type grid-connected inverter without phase locking link
CN105375804A (en) Model prediction current control method based on NPC topology grid connected inverter under asymmetric voltage
CN107196329A (en) A kind of electrified railway electric energy administers the grid-connected phase-lock technique of adjusting means
CN105071405A (en) Microgrid system with asymmetric non-linear load and power balancing control method
CN103267897B (en) Three-phase-locked loop based on reversed Park conversion
CN108448643B (en) Virtual synchronous machine motor synchronizing under unbalanced power grid based on current resonance is incorporated into the power networks control method
CN105140921A (en) Electric spring topological structure implemented based on current source type inverter and control method of electric spring topological structure
CN108847669B (en) Multi-synchronous rotation coordinate system-based multifunctional grid-connected inverter harmonic treatment method
CN105406484B (en) A kind of angle-style cascades the line voltage adjusting method of synchronous compensator
CN104578168A (en) Smooth switching control method for operating mode of micro-grid inverter of different capacity micro sources
CN105958544A (en) Non-AC voltage sensor control method of grid-connected inverter
CN105490285A (en) Reactive power compensation device of double-H-bridge modular multilevel converter (MMC) structure under three-phase unbalance and control method of reactive power compensation device
CN104410083B (en) Capacitance midpoint potential balancing device on SVG (Static VAR Generator) direct current side and control method of capacitance midpoint potential balancing device
CN109217361A (en) A kind of novel photovoltaic grid-connected inverter composite control method based on OSAP and improvement bi-mode control
CN107611971A (en) For the net side inverter resonance full-order sliding mode control method of Voltage Harmonic distortion operating mode
CN110266008A (en) Based on the improved more level active power filters of neutral-point-clamped type
CN105071390B (en) Control method of H-bridge three-level active power filter and system
CN103219745B (en) Grid-connected inverter control algorithm based on orthogonal sine wave extractor
CN101820281A (en) Single-phase phase locked loop based on double-park transformation phase discriminator and implement method thereof
CN104734537A (en) Control method for wind power current converter based on positive-and-negative sequence current inner-loop control
CN104426160A (en) Positive and negative sequence decoupling control method for low-voltage ride-through compatible with grid-connected photovoltaic inverter
CN103117562A (en) Control method of high-voltage cascade energy feedback converter power module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180420