CN107946249B - Fan-out type wafer level chip packaging structure and packaging method - Google Patents

Fan-out type wafer level chip packaging structure and packaging method Download PDF

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CN107946249B
CN107946249B CN201711173949.1A CN201711173949A CN107946249B CN 107946249 B CN107946249 B CN 107946249B CN 201711173949 A CN201711173949 A CN 201711173949A CN 107946249 B CN107946249 B CN 107946249B
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chip
layer
conductive
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wafer level
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CN107946249A (en
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姚大平
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
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Abstract

The invention provides a fan-out wafer level chip packaging structure and a packaging method, wherein the fan-out wafer level chip packaging structure comprises: the conductive layer is provided with a groove for arranging a chip; the conducting layer is arranged on the substrate; the insulating layer is arranged between the conductive layer and the substrate and is used for filling a gap between the conductive layer and the substrate; the packaging body is arranged on the upper surface of the conducting layer; the chip is packaged in the packaging body, and the bonding pad of the chip is exposed out of the packaging body; the conductive column is arranged in the packaging body, one end of the conductive column is coupled with the conductive layer, and the other end of the conductive column is exposed out of the packaging body; the conductive post is connected with the ground wire. The chip is arranged in the groove in the conducting layer, and the conducting layer is connected with the ground wire through the conducting posts, so that the electromagnetic shielding structure in the fan-out wafer level chip packaging structure is formed, the possibility that the chip is interfered by electromagnetic waves of devices inside the packaging structure and external devices can be reduced, the preparation difficulty is low, and the production cost is low.

Description

Fan-out type wafer level chip packaging structure and packaging method
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out wafer level chip packaging structure with an electromagnetic shielding structure and a packaging method.
Background
With the popularization of wireless electronic devices, the integration level of radio frequency chips is higher and higher, and fan-out type packaging technology is increasingly adopted in radio frequency chip packaging. With the increasing number of radio frequency devices in the package, the problem of direct electromagnetic interference between the devices and between the modules is more prominent, and the implementation of the electromagnetic shielding structure in the fan-out packaging process is more and more important. In a conventional method, an electromagnetic shielding metal shell is applied outside a package body after the package is completed, but the metal shell increases the package cost, increases the volume of the package, and greatly reduces the advantage of small volume of the fan-out package. In another mode, the electromagnetic shielding layer is directly applied to the packaging body by vacuum coating or spraying, and the like, and the method does not basically change the volume of the final packaging body. However, the method of externally implementing the shielding cannot avoid interference between the internal devices of the package.
In the prior art, chinese patent publication No. CN107248509A discloses an EMI protection chip package structure, which includes: a rewiring layer including a first surface and a second surface which are aligned first; a metal bump formed on a first surface of the rewiring layer; the semiconductor chip is electrically connected to the second surface of the rewiring layer; the electromagnetic shielding frame is formed on the second surface of the rewiring layer and surrounds the semiconductor chip; the packaging material covers the semiconductor chip and the electromagnetic shielding frame, and the electromagnetic shielding frame is exposed on the surface of the packaging material; and the electromagnetic shielding layer is formed on the surface of the packaging material and is connected with the electromagnetic shielding frame to form the electromagnetic shielding structure of the semiconductor chip. However, the shielding frame surrounding the chip is prepared with high precision and difficulty, so that the production cost of the whole packaging structure can be increased.
Therefore, how to reduce the difficulty in manufacturing the electromagnetic shielding structure in the fan-out wafer level chip packaging structure and reduce the production cost of the fan-out wafer level chip packaging structure becomes an urgent problem to be solved.
Disclosure of Invention
Therefore, the technical problems to be solved by the invention are to solve the problems that the preparation difficulty of the electromagnetic shielding structure in the fan-out type wafer level chip packaging structure is high, and the production cost of the fan-out type wafer level chip packaging structure is high.
To this end, according to a first aspect, an embodiment of the present invention provides a fan-out wafer level chip package structure, including: the conductive layer is provided with a groove for arranging a chip; the conducting layer is arranged on the substrate; the insulating layer is arranged between the conductive layer and the substrate and is used for filling a gap between the conductive layer and the substrate; the packaging body is arranged on the upper surface of the conducting layer; the chip is packaged in the packaging body, and the bonding pad of the chip is exposed out of the packaging body; the conductive column is arranged in the packaging body, one end of the conductive column is coupled with the conductive layer, and the other end of the conductive column is exposed out of the packaging body; the conductive post is connected with the ground wire.
Optionally, one or more grooves are provided, and the chips are arranged in one-to-one correspondence with the grooves.
Optionally, one or more conductive pillars are disposed around each chip.
Optionally, the chip is disposed on the bottom of the recess by an adhesive.
Optionally, the fan-out wafer level chip package structure further includes: and the redistribution layer is arranged on the packaging body, the bonding pad of the chip and the conductive column and is coupled with the chip and the conductive column.
According to a second aspect, an embodiment of the present invention provides a fan-out wafer level chip packaging method, including the following steps: providing a substrate, and arranging an insulating layer on the upper surface of the substrate; forming a groove on the insulating layer; arranging a conductive layer on the upper surface of the insulating layer, the bottom of the groove and the side wall of the groove; attaching a chip to the conducting layer at the bottom of the groove, wherein the device surface of the chip is far away from the conducting layer; arranging a packaging body on the conductive layer to package the chip, wherein a bonding pad of the chip is exposed out of the packaging body; forming a conductive column in the packaging body around the chip, wherein one end of the conductive column is coupled with the conductive layer, and the other end of the conductive column is exposed out of the packaging body; and connecting the conductive column with the ground wire.
Optionally, the groove penetrates through the insulating layer, and the bottom of the groove is the upper surface of the substrate.
Optionally, one or more grooves are formed, and the chips and the grooves are arranged in a one-to-one correspondence manner; one or more conductive posts are arranged around each chip.
Optionally, the conductive layer is an aluminum, copper, aluminum alloy, or copper alloy layer.
Optionally, the fan-out wafer level chip packaging method further includes the following steps: and arranging a redistribution layer on the packaging body, the bonding pad of the chip and the conductive column, and arranging a solder ball on the redistribution layer, wherein the solder ball is coupled with the chip and the conductive column through the redistribution layer.
The technical scheme provided by the embodiment of the invention has the following advantages:
1. the invention provides a fan-out wafer level chip packaging structure, which comprises: the conductive layer is provided with a groove for arranging a chip; the conducting layer is arranged on the substrate; the insulating layer is arranged between the conductive layer and the substrate and is used for filling a gap between the conductive layer and the substrate; the packaging body is arranged on the upper surface of the conducting layer; the chip is packaged in the packaging body, and the bonding pad of the chip is exposed out of the packaging body; the conductive column is arranged in the packaging body, one end of the conductive column is coupled with the conductive layer, and the other end of the conductive column is exposed out of the packaging body; the conductive post is connected with the ground wire.
Through setting up the chip in the recess on the conducting layer to this conducting layer is connected with the ground wire through leading electrical pillar, thereby forms the inside electromagnetic shield structure that is in fan-out type wafer level chip packaging structure, can reduce the chip and receive the electromagnetic wave interference's of packaging structure internal part device and external device possibility, and the preparation degree of difficulty is less, and manufacturing cost is lower, has solved and has used the electromagnetic shield frame as electromagnetic shield structure among the prior art, and the preparation degree of difficulty is great, the higher problem of manufacturing cost. Meanwhile, the conductive layer extends inside the whole packaging structure and has good thermal conductivity, so that the conductive layer can be used as a heat dissipation structure, and the heat dissipation performance of the fan-out wafer level chip packaging structure is improved.
In addition, the substrate is used as a part of the packaging structure, and can play a role in supporting the whole packaging structure, so that the stability of the fan-out type wafer level chip packaging structure is improved. Meanwhile, the substrate has good thermal conductivity, so that the substrate can be used as a heat dissipation plate of a chip in the packaging structure, the heat dissipation path of the chip is shortened, the heat dissipation area is enlarged, and the heat dissipation efficiency of the packaging structure is further improved.
2. The fan-out wafer level chip packaging structure provided by the invention has one or more grooves, and the chips and the grooves are arranged in a one-to-one correspondence manner. Through setting up chip and recess one-to-one, regard the recess as the setpoint that sets up the chip, can improve this fan-out type wafer level chip package structure's positioning accuracy, simultaneously, the recess can also restrict the chip and set up the biggest displacement of the in-process of packaging body, improves this fan-out type wafer level chip package structure's preparation precision.
3. The invention provides a fan-out wafer level chip packaging method, which comprises the following steps: providing a substrate, and arranging an insulating layer on the upper surface of the substrate; forming a groove on the insulating layer; arranging a conductive layer on the upper surface of the insulating layer, the bottom of the groove and the side wall of the groove; attaching a chip to the conducting layer at the bottom of the groove, wherein the device surface of the chip is far away from the conducting layer; arranging a packaging body on the conductive layer to package the chip, wherein a bonding pad of the chip is exposed out of the packaging body; forming a conductive column in the packaging body around the chip, wherein one end of the conductive column is coupled with the conductive layer, and the other end of the conductive column is exposed out of the packaging body; and connecting the conductive column with the ground wire.
The conducting layers are arranged on the upper surface of the insulating layer, the bottom of the groove and the side walls of the groove, so that the limitation to temperature in the preparation process of the conducting layers can be reduced, the selection flexibility of a conducting layer setting method is improved, and the preparation requirements on different thicknesses and different resistance values of the conducting layers can be met. In addition, all steps of the fan-out type wafer level chip packaging method are completed on the substrate, so that the possibility that the fan-out type wafer level chip packaging structure prepared by the method generates warping due to the thermal expansion coefficient difference between the prepared fan-out type wafer level chip packaging structure and the anisotropic material at different process temperatures and the like can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a fan-out wafer level chip package structure according to an embodiment of the present invention;
FIG. 2 is a process flow diagram of a fan-out wafer level chip packaging method according to an embodiment of the present invention;
fig. 3 to 10 are schematic structural diagrams of steps of a fan-out wafer level chip packaging method according to an embodiment of the present invention.
Description of reference numerals:
1-a conductive layer; 2-chip; 3-a substrate; 4-an insulating layer; 5-a package body; 6-conductive post; 7-a rewiring layer; 8-solder balls.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present invention.
Example 1
The present embodiment provides a fan-out wafer level chip package structure, as shown in fig. 1, including: the chip packaging structure comprises a conductive layer 1, wherein a groove for arranging a chip 2 is formed in the conductive layer 1; the conductive layer 1 is arranged on the substrate 3; an insulating layer 4 disposed between the conductive layer 1 and the substrate 3 for filling a gap between the conductive layer 1 and the substrate 3; a package 5 disposed on the upper surface of the conductive layer 1; the chip 2 is packaged in the packaging body 5, and a bonding pad of the chip 2 is exposed out of the packaging body 5; a conductive post 6 disposed in the package 5, one end of which is coupled to the conductive layer 1 and the other end of which is exposed outside the package 5; the conductive post 6 is connected to ground. In a specific embodiment, the depth of the groove is less than the thickness of the chip 2, the conductive layer 1 is an aluminum, copper, aluminum alloy or copper alloy layer, and preferably, the thickness of the conductive layer 1 is 2-10 um. The insulating layer 4 is a photosensitive material layer, and of course, may also be a non-photosensitive material layer, and preferably, the thickness of the insulating layer 4 is 2-20 um. In a specific embodiment, the material of the substrate 3 is silicon, silicon carbide, thermally conductive ceramic, or metal, which has a good thermal conductivity, and specifically, the expansion coefficient of the substrate 3 is close to that of the package 5.
In this embodiment, the pad of the chip 2 is exposed outside the package 5, which means that a plane where the pad of the chip 2 is located, that is, a device surface of the chip 2 and an upper surface of the package 5 are located on the same plane, or the device surface of the chip 2 is located in the package 5, and the package 5 is provided with a through hole at the pad of the chip 2, so that the pad of the chip 2 is exposed outside the package 5 through the through hole. One end of the conductive pillar 6 is coupled to the conductive layer 1, that is, one end of the conductive pillar 6 is in contact with the conductive layer 1, and the other end of the conductive pillar 6 is exposed outside the package 5, that is, the other end of the conductive pillar 6 and the upper surface of the package 5 are located on the same plane.
Through setting up chip 2 in the recess on conducting layer 1 to this conducting layer 1 is connected with the ground wire through leading electrical pillar 6, thereby forms the inside electromagnetic shield structure that is in fan-out type wafer level chip packaging structure, can reduce the possibility that chip 2 receives the electromagnetic wave interference of packaging structure internal part device and external device, and the preparation degree of difficulty is less, and manufacturing cost is lower, has solved and has used the electromagnetic shield frame as electromagnetic shield structure among the prior art, and the preparation degree of difficulty is great, the higher problem of manufacturing cost. Meanwhile, the conductive layer 1 extends inside the whole packaging structure, and the conductive layer 1 has good thermal conductivity, so that the conductive layer can be used as a heat dissipation structure, and the heat dissipation performance of the fan-out wafer level chip packaging structure is improved.
In addition, the substrate 3 as a part of the package structure can play a role of supporting the whole package structure, thereby improving the stability of the fan-out wafer level chip package structure. Meanwhile, since the substrate 3 has good thermal conductivity, it can be used as a heat sink for the chip 2 inside the package structure, thereby shortening the heat dissipation path of the chip 2, enlarging the heat dissipation area, and further improving the heat dissipation efficiency of the package structure.
In an alternative embodiment, there are one or more grooves, and the chips 2 are arranged in one-to-one correspondence with the grooves. In the present embodiment, one or more conductive pillars 6 are disposed around each chip 2. In a specific embodiment, the pitch of the conductive pillars 6 is smaller than the wavelength of the electromagnetic wave, so that the possibility that the chip 2 is interfered by the electromagnetic wave of the device inside the package structure and the device outside the package structure can be effectively reduced. Through setting up chip 2 and recess one-to-one, regard the recess as the setpoint that sets up chip 2, can improve this fan-out type wafer level chip package structure's positioning accuracy, simultaneously, the recess can also restrict the chip 2 at the biggest displacement of the in-process that sets up packaging body 5, improves this fan-out type wafer level chip package structure's preparation precision.
In an alternative embodiment, the chip 2 is arranged at the bottom of the recess by means of an adhesive. In a specific embodiment, the adhesive may be a liquid adhesive, a semi-solid adhesive or a solid adhesive film, and specifically, when the adhesive is a liquid adhesive, the liquid adhesive is coated on the bottom of the groove, and then is baked and cured, the viscosity degree of the liquid adhesive is controlled, and then the chip 2 is pressed and attached to the cured liquid adhesive, so as to complete the setting of the chip 2; when the adhesive is semisolid adhesive, the adhesive can be directly coated in a dispensing manner except that part of the adhesive needs to be baked and cured to enable the adhesive to have proper viscosity, and then the chip 2 is stuck on the semisolid adhesive to complete the setting of the chip 2; when the adhesive is a solid adhesive film, the solid adhesive film is attached to the bottom of the groove by using a film attaching machine, curing is not needed, and the chip 2 is directly attached to the solid adhesive film to complete the setting of the chip 2. Preferably, the adhesive is conductive adhesive, and is converted into a conductor after being cured to be interconnected with the conductive layer 1, so that the electromagnetic shielding effect can be achieved, and the electromagnetic shielding performance of the fan-out wafer level chip package is further improved.
In an optional embodiment, the fan-out wafer level chip package structure further includes: and a redistribution layer 7 disposed on the package 5, the pads of the chip 2, and the conductive pillars 6, and coupled to the chip 2 and the conductive pillars 6. In the present embodiment, the conductive post 6 is connected to the ground line through the redistribution layer. In a specific embodiment, the material of the redistribution layer 7 may be one of aluminum, gold, chromium, cobalt, nickel, copper, molybdenum, titanium, tantalum, or tungsten, or an alloy of the above metals. By arranging one or more layers of rewiring layers 7 on the device surface of the chip 2, the input/output ports of the chip 2 can be rearranged and arranged in a new area with more loose pitch occupation, so that the layout flexibility of the wafer level fan-out type packaging structure is improved, and the application limitation caused by the arrangement of the input/output ports is reduced.
Example 2
The embodiment provides a fan-out wafer level chip packaging method, as shown in fig. 2, including the following steps:
step S1: a substrate is provided, and an insulating layer is disposed on the upper surface of the substrate. As shown in fig. 3, in the present embodiment, the insulating layer 4 may be disposed by spraying or spin coating. In a specific embodiment, the substrate 3 is made of silicon, silicon carbide, thermally conductive ceramic, or metal with good thermal conductivity, and the insulating layer 4 is made of photosensitive material layer made of photosensitive polyimide or other photosensitive resin, or of course, may be made of non-photosensitive material layer, and preferably, the thickness of the insulating layer 4 is 2-20 um.
Step S2: a groove is formed on the insulating layer. As shown in fig. 4, in a specific embodiment, when the insulating layer 4 is a photosensitive material layer, a groove is formed by photolithography and development, and the groove is baked and cleaned; when the insulating layer 4 is a non-photosensitive material layer, a photoresist layer is formed on the insulating layer 4, a groove is formed by adopting a photoetching and wet etching mode, and the groove is baked and cleaned. In the embodiment, the groove penetrates through the insulating layer 4, and the bottom of the groove is the upper surface of the substrate 3, so that the thickness of a product prepared by adopting the fan-out wafer level chip packaging method can be reduced.
Step S3: and arranging a conductive layer on the upper surface of the insulating layer, the bottom of the groove and the side wall of the groove. As shown in fig. 5, in a specific embodiment, the conductive layer 1 may be an aluminum, copper, aluminum alloy or copper alloy layer, specifically, when the conductive layer 1 is an aluminum or aluminum alloy layer, the conductive layer 1 may be disposed by physical deposition or the like; when the conductive layer 1 is a copper or copper alloy layer, a bonding film may be first disposed on the upper surface of the insulating layer 4, the bottom of the groove, and the sidewall of the groove, and then the conductive layer 1 is disposed by physical deposition, and specifically, the bonding film may be a titanium film or a tantalum film. Preferably, the thickness of the conductive layer 1 is 2-10 um.
Step S4: the chip is attached to the conducting layer at the bottom of the groove, and the device surface of the chip 2 is far away from the conducting layer. As shown in fig. 6, in the present embodiment, the chip 2 is attached to the conductive layer 1 at the bottom of the groove by an adhesive. In a specific embodiment, the adhesive may be a liquid adhesive, a semi-solid adhesive or a solid adhesive film, and specifically, when the adhesive is a liquid adhesive, the liquid adhesive is coated on the bottom of the groove, and then is baked and cured, the viscosity degree of the liquid adhesive is controlled, and then the chip 2 is pressed and attached to the cured liquid adhesive, so as to complete the setting of the chip 2; when the adhesive is semisolid adhesive, the adhesive can be directly coated in a dispensing manner except that part of the adhesive needs to be baked and cured to enable the adhesive to have proper viscosity, and then the chip 2 is stuck on the semisolid adhesive to complete the setting of the chip 2; when the adhesive is a solid adhesive film, the solid adhesive film is attached to the bottom of the groove by using a film attaching machine, curing is not needed, and the chip 2 is directly attached to the solid adhesive film to complete the setting of the chip 2.
In this embodiment, the adhesive is preferably a thermally curable adhesive, so that the chip 2 can be secured to the mounted position, the chip 2 is prevented from being displaced in the subsequent process, and the precision of the product prepared by the fan-out wafer level chip packaging method is improved. Preferably, the adhesive is conductive adhesive, and is converted into a conductor after being cured to be interconnected with the conductive layer 1, so that the electromagnetic shielding effect can be achieved, and the electromagnetic shielding performance of the fan-out wafer level chip packaging structure prepared by the method is further improved.
Step S5: and arranging a packaging body on the conductive layer to encapsulate the chip. As shown in fig. 7, in the present embodiment, the bonding pads of the chip 2 are exposed outside the package body 5. In the embodiment, the package 5 is formed by injecting resin on the upper surface of the conductive layer 1 and over the chip 2 and molding. In this embodiment, the pad of the chip 2 is exposed outside the package 5, which means that a plane where the pad of the chip 2 is located, that is, a device surface of the chip 2 and an upper surface of the package 5 are located on the same plane, or the device surface of the chip 2 is located in the package 5, and the package 5 is provided with a through hole at the pad of the chip 2, so that the pad of the chip 2 is exposed outside the package 5 through the through hole. In a specific embodiment, the pads of the chip 2 can be exposed outside the package 5 by grinding the upper surface of the package 5; or a through hole is formed at the position of the bonding pad of the chip 2 by penetrating through the packaging body 5 in a laser drilling mode and the like, so that the bonding pad of the chip 2 is exposed out of the packaging body 5; or, a method of combining the grinding of the package 5 with the laser drilling is adopted, that is, the package 5 is firstly ground to expose the bonding pad of the chip 2 with a larger thickness out of the package 5, and then a laser drilling method is adopted to form a through hole at the bonding pad position of the chip 2 with a smaller thickness, so that the bonding pad of the chip 2 is exposed out of the package 5.
Step S6: and forming conductive columns in the packaging body around the chip. As shown in fig. 8 and 9, in the present embodiment, one end of the conductive pillar 6 is coupled to the conductive layer 1, and the other end is exposed outside the package body 5. In a specific embodiment, the conductive via penetrating the package 5 is formed by drilling a hole in the package 5 around the chip 2 to expose the conductive layer 1, and the conductive post 6 is formed by filling a conductive material in the conductive via. In a specific embodiment, the conductive post 6 may be formed by implanting a solder ball in the conductive via for multiple times, implanting a copper rod wrapped by a tin film in the conductive via, and electroplating copper, or by filling a conductive adhesive in the conductive via and then curing.
Step S7: and connecting the conductive column with the ground wire.
In this embodiment, after the steps S1 to S7 are completed, the lower surface of the substrate 3 may be ground and thinned as required by the actual application scenario, so as to reduce the thickness of the fan-out wafer level chip package structure prepared by the above method.
By arranging the conductive layer 1 on the upper surface of the insulating layer 4, the bottom of the groove and the side wall of the groove, the limitation on temperature in the preparation process of the conductive layer 1 can be reduced, and the selection flexibility of the setting method of the conductive layer 1 is improved, so that the preparation requirements on different thicknesses and different resistance values of the conductive layer 1 can be met. In addition, all steps of the fan-out type wafer level chip packaging method are completed on the substrate 3, so that the possibility that the fan-out type wafer level chip packaging structure prepared by the method generates warping due to the thermal expansion coefficient difference between the prepared fan-out type wafer level chip packaging structure and the anisotropic material at different process temperatures and the like can be reduced.
In an alternative embodiment, as shown in fig. 10, there are one or more grooves, and the chips 2 are arranged in one-to-one correspondence with the grooves; one or more conductive posts 6 are disposed around each chip 2. In a specific embodiment, the pitch of the conductive pillars 6 is smaller than the wavelength of the electromagnetic wave, so that the possibility that the chip 2 is interfered by the electromagnetic wave of the device inside the package structure and the device outside the package structure can be effectively reduced. Through setting up chip 2 and recess one-to-one, therefore, can regard as the setpoint that sets up chip 2 with the recess, improve this fan-out type wafer level chip package structure's positioning accuracy, simultaneously, the recess can also restrict the chip 2 at the biggest displacement of the in-process that sets up packaging body 5, further improves this fan-out type wafer level chip package structure's positioning accuracy.
In an alternative embodiment, as shown in fig. 9, the fan-out wafer level chip packaging method further includes the following steps: a redistribution layer 7 is provided on package 5, pads of chip 2, and conductive pillars 6, and solder balls 8 are provided on redistribution layer 7, solder balls 8 being coupled to chip 2 and conductive pillars 6 through redistribution layer 7. In a specific embodiment, when the pad of the chip 2 is exposed outside the package 5 by a via, an adhesion layer such as a tantalum layer, a titanium layer, a tantalum nitride layer, or a titanium nitride layer may be formed in the via by sputtering, the via may be filled by electroplating copper, and then the redistribution layer 7 may be disposed. In the present embodiment, the conductive post 6 is connected to the ground line via the redistribution layer 7 and the solder ball 8. In a specific embodiment, the material of the redistribution layer 7 may be one of aluminum, gold, chromium, cobalt, nickel, copper, molybdenum, titanium, tantalum, or tungsten, or an alloy of the above metals. By arranging one or more layers of rewiring layers 7 on the device surface of the chip 2, the input/output ports of the chip 2 can be rearranged and arranged in a new area with more loose pitch occupation, so that the layout flexibility of the wafer level fan-out type packaging structure is improved, and the application limitation caused by the arrangement of the input/output ports is reduced.
In an embodiment, the fan-out wafer level chip package structure prepared by all or part of the above methods may be singulated to prepare a single packaged device.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are intended to be within the scope of the invention.

Claims (9)

1. A fan-out wafer level chip package structure, comprising:
the chip packaging structure comprises a conductive layer (1), wherein a groove for arranging a chip (2) is formed in the conductive layer (1); the conducting layer (1) is arranged on the substrate (3); the depth of the groove is smaller than the thickness of the chip (2);
an insulating layer (4) disposed between the conductive layer (1) and the substrate (3) for filling a gap between the conductive layer (1) and the substrate (3);
a package (5) disposed on an upper surface of the conductive layer (1); the chip (2) is packaged in the packaging body (5), and a bonding pad of the chip (2) is exposed out of the packaging body (5);
the conductive column (6) is arranged in the packaging body (5), one end of the conductive column is coupled with the conductive layer (1), and the other end of the conductive column is exposed out of the packaging body (5); the conductive column (6) is connected with the ground wire; each chip (2) is provided with a plurality of conducting posts (6) all around, and the interval that is adjacent conducting posts (6) is less than the wavelength of electromagnetic wave.
2. The fan-out wafer level chip package structure of claim 1, wherein the number of the grooves is one or more, and the chips (2) are arranged in one-to-one correspondence with the grooves.
3. The fan-out wafer level chip package structure of claim 1 or 2, wherein the chip (2) is disposed at the bottom of the groove by an adhesive.
4. The fan-out wafer level chip package structure of claim 1 or 2, further comprising:
and the redistribution layer (7) is arranged on the packaging body (5), the bonding pad of the chip (2) and the conductive column (6) and is coupled with the chip (2) and the conductive column (6).
5. A fan-out wafer level chip packaging method is characterized by comprising the following steps:
providing a substrate (3), and arranging an insulating layer (4) on the upper surface of the substrate (3);
forming a groove on the insulating layer (4);
arranging a conductive layer (1) on the upper surface of the insulating layer (4), the bottom of the groove and the side wall of the groove;
a chip (2) is attached to the conducting layer (1) at the bottom of the groove, and the device surface of the chip (2) is far away from the conducting layer (1); the depth of the groove is smaller than the thickness of the chip (2);
arranging a packaging body (5) on the conductive layer (1) to encapsulate the chip (2), wherein a bonding pad of the chip (2) is exposed out of the packaging body (5);
forming a conductive column (6) in the package body (5) around the chip (2), wherein one end of the conductive column (6) is coupled with the conductive layer (1), and the other end of the conductive column is exposed out of the package body (5); a plurality of conductive columns (6) are arranged around each chip (2), and the distance between every two adjacent conductive columns (6) is smaller than the wavelength of electromagnetic waves;
and connecting the conductive column (6) with the ground wire.
6. The fan-out wafer level chip packaging method according to claim 5, wherein the groove penetrates through the insulating layer (4), and the bottom of the groove is an upper surface of the substrate (3).
7. The fan-out wafer level chip packaging method according to claim 6, wherein the number of the grooves is one or more, and the chips (2) are arranged in one-to-one correspondence with the grooves.
8. The fan-out wafer level chip packaging method according to claim 5, wherein the conductive layer (1) is an aluminum, copper, aluminum alloy or copper alloy layer.
9. The fan-out wafer level chip packaging method of any one of claims 5-8, further comprising the steps of:
and arranging a redistribution layer (7) on the packaging body (5), the bonding pad of the chip (2) and the conductive column (6), arranging a solder ball (8) on the redistribution layer (7), and coupling the solder ball (8) with the chip (2) and the conductive column (6) through the redistribution layer (7).
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Application publication date: 20180420

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