CN107923856A - The non-vision dividing instrument of real time scan electron microscope based on scope - Google Patents

Abstract

Present invention is disclosed a kind of technology for being used to identify the non-vision defect such as the non-vision defect SNV of SEM, the technology includes：Produce the image of the layer of chip；At least one attribute of described image is assessed using grader；And the non-vision defect on the layer of the identification chip.Controller can be configured to be identified the non-vision defect using the grader.This controller can examine instrument communications again with the defects of such as scanning electron microscope SEM.

Description

The non-vision dividing instrument of real time scan electron microscope based on scope

The cross reference of related application

Application case 4069/CHE/2015 India of India was applied for and transferred to present application requirement on 5th in August in 2015 Temporary patent application case and in the application on the 23rd of September in 2015 and No. 62/222,647 temporary patent application of assigned U application case The priority of case, the disclosure of the application case are herein incorporated by reference accordingly.

Technical field

The present invention relates to the classification to defect, and more specifically, it is related to the classification to non-vision defect.

Background technology

Chip detection system contributes to semiconductor maker by detecting the defects of occurring during manufacturing process to increase And maintain integrated circuit (IC) chip yield.One purpose of detecting system is whether monitoring manufacturing process is up to specification.Such as Fruit manufacturing process is outside the scope of given profile, then the source of detecting system indication problem and/or problem, then semiconductor system Described problem can be solved by making business.

The development of semiconductor processing industry said to yield management and specifically metering and detecting system demand increasingly Greatly.Critical dimension increasingly reduces and wafer size increasingly increases.Economic factor drives the industry to reduce and is used for realization high finished product Rate, the time of high value production.Therefore, minimize and determine total time partly to lead from detection yield problem to solution described problem The investment repayment of body manufacturer.

Prior art for being classified to defect and (including manual classification and the automatic classification based on layer) is related to Excessive time and effort.As device becomes more complicated, carrying out manual classification to defect in semiconductor manufacturing facilities needs Will increasingly increased time and effort.Even after taking a significant amount of time and being classified, human error, defect classification are attributed to May be still to be inaccuracy and inconsistent.The current techniques classified automatically to defect in field need many realities of defect Example and also need to the human resources for training grader sometimes.In addition, train classification for each layer of each defect type Device can be cumbersome, this is because the total number of grader to be trained will be multiplied by the number of layer for the number of defect type.

Manual classification is related to：With each defect image of multiple visual angle manual observations, with known reference defect image set into Row defect recognition, and for each defect sites manual allocation classification code.Carrying out manual classification to defect needs the plenty of time Complete.This is extremely expensive again.In addition, inaccuracy can be introduced in the result using artificial judgement during classification and differed Cause property.

Classification automatically based on layer includes the self-defined grader for each layer of foundation, existing for its separation all Critical defective type.Grader can manually or automatically be established.Automatic classification based on layer is implemented to self-defined point of layer specific The foundation of class device.The grader of training whole layer needs vast resources, as training data, human resources and time.For example, training Each layer of grader needs training data.Training data should have lacking enough for each critical defective that need to be classified by grader Fall into example.Some graders used in the field, which establish scheme, needs manual classification device to establish.Together with being related to the plenty of time Investment, is attributed to inaccuracy when judging to be used to establish the best attributes collection of the grader, this, which also brings, is set up classifying The inconsistency of the performance of device.Due to for the layer at specific site and also across the identical defect type in multiple client sites Huge repetition during grader is established, the plenty of time is spent in foundation, training and safeguards on grader.

Therefore, it is necessary to a kind of time reduced needed for classification wafer defect and the system and technology of effort.

The content of the invention

In the first embodiment, there is provided a kind of system.The system comprises：Defect examines instrument again；And controller, it is through matching somebody with somebody Put to examine instrument communications again with the defect.The defect examines instrument again has the objective table for being configured to holding chip.It is described Controller is configured to identify the non-vision defect on the layer of the chip using grader.The defect examines instrument again Scanning electron microscope (SEM).The non-vision defect can be the non-vision defects of SEM (SNV).

The controller may include：Processor, it is configured to examine instrument communications again with the defect；Storage device, its With the processor electronic communication containing the grader；And communication port, its with the processor electronic communication with institute State defect and examine instrument communications again.

The controller can be filtered in pattern defect, Intensity attribute or energy properties extremely by using the grader Lack one and identify non-vision defect.

In a second embodiment, there is provided a kind of method.The described method includes：Instrument is examined again using defect to produce on chip The image of layer；At least one attribute of described image is assessed using grader using processor；And use processor profit The non-vision defect on the layer of the chip is identified with the grader.

The method can further comprise：The upper limit and lower limit of non-vision defect, wherein institute are defined using the processor The non-vision defect of identification is between the upper limit and the lower limit.

The grader can be configured to filter pattern defect, Intensity attribute and/or energy properties.

The grader can be configured to be used on each layer of the chip.

Scanning electron microscope (SEM) can be used in described produce.The non-vision defect can be the non-vision defects of SEM (SNV)。

Compared with being performed in real time together with the generation and identify.

Brief description of the drawings

In order to which the property and target of the present invention is more fully understood, should with reference to attached drawing with reference to described in detail below, wherein：

Fig. 1 is flow chart according to an embodiment of the invention；

Fig. 2 is the chart of the exemplary upper limit that display scan electron microscope non-vision (SNV) is spread and lower limit；

Fig. 3 is the schematic diagram of exemplary SNV graders；And

The defects of Fig. 4 is according to the present invention examines the embodiment of instrument again.

Embodiment

Although advocated subject matter will be described according to specific embodiment, other embodiments (are included and not provided herein The all advantages of middle elaboration and the embodiment of feature) it is also within the scope of the invention.The situation of the scope of the present invention is not being departed from Under, various structures, logic, process steps and electronics can be carried out and changed.Therefore, the scope of the present invention is only with reference to appended claims Book defines.

Scanning electron microscope (SEM) non-vision (being known as " SNV ") is defined as defective but does not contain any real definition The defects of inspection site again.The defects of real definition can be with the destruction on the chip with reference to compared with.For example, real definition lacks It can be particle, scratch or gap to fall into.Therefore, for SNV by with similar property compared with its reference point, this can be difficult to SNV Manual identification.As disclosed herein, it can calculate and lack after reference picture (that is, defect-reference picture) is subtracted from defect image Fall into attribute.This causes the common attribute value of the SNV of cross-layer, and causes to establish the SNV to lattice gone out on (bin out) multiple layers Single grader or real-time SNV (RT-SNV) grader.Lattice refers to several general successive value packets are a into small number One or more methods of subgroup.Grader can be directed to specific purpose (for example, defect classification and detection) by identifying that SNV's is same Attribute group and " lattice goes out " SNV.

Even if there be no the physics residue or visual defects that can easily watch, non-vision defect (such as SNV) can still draw The electric fault of lifting device.The example of non-vision defect includes：Between the chip of resistance, capacitance or sequential or chip chamber changes；Should Dislocation caused by power；Local-crystalized defect；Or local engagement defect.Non-vision defective effect yield rate, this makes non-vision defect It is of interest for semiconductor maker, and identify non-vision defect tool challenge.

Some defect types (such as SNV or particle) are common and consistent across multiple layers of one or more chips.This is Cause to establish the grader foundation being converted to based on defect from the grader based on layer.Classification based on defect Device foundation is related to implementation lattice and goes out the single grader across multiple layers of common defects type of one or more chips.Common defects Type has similar defect attribute value scope across multiple layers.

SNV can be found when scheming the defects of inspection comes from one-hundred-percent inspection device again.Verifier can include automatic, semi-automatic and manual Wafer inspection instrument and process.Semiconductor maker may not want to miss any real defect, this cause detection scanning have compared with Low threshold.Lower threshold causes to judge (false positive) and other public hazards by accident again.After a test by these erroneous judgement or its It is difficult task that its public hazards is separated with real defect, this is because the layer with high SNV percentages will need the plenty of time and Manpower is again examined.The embodiment of the present invention is related to the range of attributes of the SNV on multiple layers of one or more chips, to establish one Grader and SNV is separated with real defect across the whole nodes found in whole layers and whole site.

As disclosed herein, the range of attributes of the SNV on multiple layers can be used to：1) physics across the SNV of significant number of layers is understood Property, this will realize that SNV and the program of other real defects separate；And 2) understand attribute and range of attributes for across significant number of layers It is identical for SNV so that this generic attribute and range of attributes to can be used programmatically to isolate SNV.Presently disclosed system And method is also produced using the predicable scope of the SNV on whole layers and goes out SNV using grader with lattice.It is presently disclosed System and method can also be directed to different instances (such as chain test, find stream etc.) produce and using single grader with lattice go out across The SNV of whole layers.In addition, the present invention can carry out cutting for defining classification device across multiple layers using common (that is, the shared) scope of attribute Stop.

RT-SNV graders can reduce cost and increase treating capacity at semiconductor maker.In addition, defect is faster divided Class can help to semiconductor maker and faster solve its yield problem, this is reduced to the time for producing result.These advantages are led Induced semiconductor manufacturer saves a large amount of capital.

Fig. 1 is flow chart according to an embodiment of the invention.The step of method can be performed as described further herein It is each of rapid.The method can also include can be by image acquisition subsystem described herein and/or computer subsystem Or any other step that system performs.The step, one or more described calculating are performed by one or more computer systems Machine system can be configured according to any one of embodiment described herein.In addition, it can be implemented by system described herein Any one of example performs method as described above.

As seen in Figure 1, at 100, the image of the layer on chip is produced.Image capture device can be used (such as to scan Electron microscope (SEM)) produce or catch image.Image may include one or more figures being programmatically stitched together Picture.Multiple views of the image containing chip, such as the view of the light generation using various wavelength.Image can be digitized into and by Store in scratchpad memory (RAM) or permanent memory (such as hard disk drive).Image can be stored in can be by one or more System is opened up in database via the plan that internet or internal network access.At 101, image is assessed at least using grader One attribute.For example, image can be retrieved by classification processor to be assessed.Classification processor can from scratchpad memory or forever Long memory requests image.In one embodiment, classification processor can open up database request image from plan.Classification processor can Image is assessed using grader.Thus, at 102, using grader come identify the non-vision defect on the layer of chip (such as SNV)。

It can be based on across multiple layers and/or multiple chips (and across multiple sites, using supporting (assorted) equipment) in SEM The defects of being extracted on image attribute is examined again to establish or produce grader.This, which can be used, examines or measures algorithm performs.Can by institute The SEM of collection examines image manual classification into the defects of different type and SNV again.In certain embodiments, can from previous test and Known source imports collected SEM and examines image again.

Examined again using defect and software of classifying (such as Impact XP from Ke Lei company (KLA-Tencor)) determines The attribute-value ranges of SNV.Software is examined and classified to this defect again can include automatic defect classification.In most of SNV, (exclusion peels off Point) collectively reside in the upper limit and lower limit of the boundary generation in it for the SNV distributions of particular community.For example, with reference in Fig. 2 The upper limit and lower limit.In the range of the property value of most of SNV is spread around the ideal value of SNV.For example, for SNV, belong to Property 1=1, attribute 2=0, attribute 3=0 etc..

Similar data are collected with definite or further analysis to defining and classifying in each heavy inspection batch for multiple layers Attribute useful SNV.Multiple attribute collection SNV range datas can be directed to (comprising the upper limit and lower limit).Can across different layers and/or not Different image-forming conditions are used with chip.

The range of attributes value of SNV is programmatically analyzed for the coextensive of the layer across one or more chips.Because belong to Property can show common value scopes of the SNV across multiple layers, so the predicable scope of SNV can be used for implement single grader with across Multiple layers of lattice go out SNV.These coextensives are by for defining the attribute boundary of RT-SNV graders.Across multiple chips confirm because The performance of this RT-SNV grader formed.

More attribute can be used use grader from SNV lattices filter different type the defects of.These are included with next A little or all filterings.Pattern attribute filters out pattern defect, such as particle, scratch.Intensity attribute separates high material contrast or height GL difference defects, such as residue, scum silica frost.Energy properties filtering high energy and high-energy-density defect, such as gap or big defect. Similarly, other types of attribute can be used to separate with SNV the defects of different type.

Extracted range of attributes can be marked and drawn.The classification of automatic defect in real time (RT-ADC) attribute mentioned below, SNV Scope is similar for various layers.

Table 1

The border of the predicable scope of SNV on whole layers can be used as the cut off of the respective attributes node of grader. After this may be any in any client site without that should be ready to be deployed in the conventional training of grader and grader In any layer of node.However, in certain embodiments, cut off can need adjusted and remote predicable scope to compensate spy Determine instrument or purposes.

It can be used with properties node by grader SNV to be separated with real defect.Attribute 2, attribute 3, attribute 6 and Attribute 5 separates pattern real defect (such as particle and scratch) with SNV.Attribute 5 can for example be related to energy measurement.Attribute 2 can example Such as compare peak height.Attribute 3 and attribute 6 can be respectively positive measured value and negative measured value.Attribute 7 is true by high material contrast Defect (such as residue) is separated with SNV.Attribute 8 separates high density real defect (such as gap) with SNV.Attribute 4 can be covered aobvious Work property and exclusive individual defect (as protuberance, little particle, small concave point and opening) can be separated with SNV.Attribute 1 will be with background not class As any other defect separated with SNV.

For example, exemplary SNV graders are directed to, referring to Fig. 3.

After grader is ready to, it can the deployed SNV to identify on the layer of other chips.

As used herein, term " chip " generally refers to substrate made of semiconductors or non-semiconductor materials.This The example of semiconductor or non-semiconducting material is including but not limited to monocrystalline silicon, gallium nitride, GaAs, indium phosphide, sapphire and glass Glass.It usually can find and/or handle in semiconductor manufacturing facilities such substrate.

Chip can include one or more layers formed on substrate.For example, such layer can be including but not limited to photoresist Agent, dielectric substance, conductive material and semiconductive material.Many different types of such layers known in the art, and such as this Term chip used herein wishes to cover the chip of such layer comprising all types.

One or more layers formed on chip can patterned or unpatterned.For example, chip can include it is multiple naked Piece, it, which each has, repeats patterned feature or periodic structure.The formation and processing of such material layer can finally cause Intact device.Many different types of devices can be formed on chip, and term " chip " wishes to cover as used in this article The chip of any kind of device known in the art is manufactured thereon.

Fig. 4 is the embodiment that defect examines instrument 200 again.It can be SEM, using the another of electron beam that defect examines instrument 200 again Defect examines instrument again, or is configured to examine the miscellaneous equipment of chip.

Defect examines instrument 200 and includes the objective table 204 for being configured to holding chip 203 again.Objective table 204 can be configured with Move or rotate on one, two or three axis.

As seen in Figure 4, chip 203 includes multiple layers, includes layer 209 and 210.Layer 210 is formed at after layer 209.Though Right layer 210 is illustrated in Figure 4 to be imaged, but layer 209 can be imaged before forming layer 210.Than three layers illustrated in fig. 4 More or fewer layers are feasible.

Defect examines the image generating system of image of the instrument 200 also comprising the surface for being configured to produce chip 203 again 201.Image can be directed to the certain layer of chip 203.In this example, image generating system 201 produces electron beam 202 to produce crystalline substance The image of piece 203.Other image generating systems 201 are feasible, such as use broadband plasma body or the image of laser scanning Generation system.

In particular instances, it is that the part of scanning electron microscope (SEM) or scanning electron are shown that defect examines instrument 200 again Micro mirror (SEM).The image of chip 203 is produced by using the scanning chip 203 of electron beam 202 is focused on.Electronics be used for produce containing On chip 203 surface topography and composition information signal.Electron beam 202 can be scanned with raster scan pattern, and can group The position of electron beam 202 is closed with signal after testing to produce image.

Defect examines instrument 200 and communicates with controller 205 again.For example, controller 205 can be with image generating system 201 or scarce Fall into the other assembly communications for examining instrument 200 again.Controller 205 can include processor 206, be deposited with processor 206 electronic communication Storage device 207, and the communication port 208 with 206 electronic communication of processor.It will be appreciated that controller 205 actually can by hardware, Any combinations of software and firmware are implemented.In addition, its function can be performed by a unit or is allocated in not as described in this article With in component, each of described component can be implemented by any combinations of hardware, software and firmware again.For implementing herein Described in various methods and function controller 205 program code or instruction can be stored in the controller 105, control In the controller readable memory medium (such as memory) of the outside of device 205 or its combination.

Grader also can be used to identify the non-vision defect on the layer of chip, such as SNV in controller 205.For example, control The step of device 205 can perform Fig. 1.Controller 205 can also carry out other steps or technology disclosed herein.

Controller 205 can in any suitable manner (for example, via one or more transmission medias, its can include " wired " and/ Or " wireless " transmission media) it is coupled to the detector that defect examines instrument 200 again so that controller 205 can be received by detector (example Such as the detector in image generating system 201) produce output.Controller 205 can be configured to be come using the output of detector Perform several functionalities.For example, the defects of controller 205 can be configured with the output using detector to detect on chip 203.Can By controller 205 by the way that a certain defects detection algorithm and/or method are applied to the output by detector generation and perform detection The defects of on chip 203.Defects detection algorithm and/or method can include disclosed herein or known in the art any Fit algorithm and/or method.For example, controller 205 may compare output and the threshold value of detector.Appointing with the value beyond threshold value What output can be identified as possible defect (such as the non-vision defects of SNV or other), and the value with less than threshold value is any defeated Going out to be not recognized as may defect.In another example, controller 205 can be configured is deposited so that the output of detector is sent to Storage device 207 or another storage media, and defects detection is not performed to output.Controller 205 can as described in this article as into one Step configuration.

Controller 205, other systems or other subsystems described herein can take various forms, include individual calculus Machine system, image computer, mainframe computer system, work station, network appliance, Internet appliance or other devices.In general, Term " controller " can be broadly defined as covering any device with one or more processors, one or more described processors are held Instruction of the row from memory medium.Subsystem or system can also include any suitable processor known in the art, example Such as parallel processor.In addition, subsystem or system can include the platform with high speed processing and software, its as standalone tool or Networking tools.

If system includes more than one subsystem, then different sub-systems can be coupled to each other so that can be in the subsystem Image, data, information, instruction etc. are sent between system.For example, one subsystem can (it can be wrapped by any suitable transmission media Containing any suitable wired and/or wireless medium known in the art) it is coupled to extra subsystem.Such subsystem More than both or both can also effectively it be coupled by Sharing computer readable memory medium (not showing).

Additional examples of composition is related to a kind of non-transitory computer-readable media of storage program instruction, and described program instruction can Perform on the controller and be used to identify the computer-implemented side such as non-vision defect (such as SNV) disclosed herein to perform Method.Specifically say, as shown in Figure 4, storage device 207 or other storage medias can contain comprising can be held on controller 205 The non-transitory computer-readable media of capable programmed instruction.Computer implemented method can include any method described herein Any step.

The programmed instruction of the method for embodiment method as described in this article can be stored on computer-readable media, such as In storage device 207 or other storage medias.Computer-readable media can be storage media, such as disk or CD, tape, Or any other suitable non-transitory computer-readable media known in the art.

Programmed instruction can be implemented any one of in a variety of ways, the mode include technology based on program, with Technology and/or Object-oriented Technique based on component etc..For example, as required, can be used ActiveX control, C++ objects, JavaBeans, Microsoft Foundation classification (" MFC "), SSE (streaming SIMD extensions) or other techniques or methods opinions are carried out implementation procedure and are referred to Order.

Controller 205 can be configured according to any one of embodiment described herein.The other configurations of controller 205 or Function is feasible, such as the configuration described in the 14/991st, No. 901 US application case or function, the case disclosure Full text be herein incorporated by reference.

Although being disclosed as the part of defect weight check system, controller described herein can be configured to be with examining System is used together.In another embodiment, controller described herein can be configured to be used together with metering system.Cause This, as embodiments disclosed herein description can be directed to the system with the different imaging capabilities for being more or less suitable for different application And with some configurations of the classification of several means customization.

Embodiments disclosed herein also can be configured the inspection for other samples (such as key light cover), defect is examined again and Metering.For example, the purpose that can be measured for mask inspection, wafer inspection and chip configures embodiment described herein.It is specific Say that embodiment described herein can be installed on computer node or computer cluster, the computer node or calculating in ground Machine cluster is that output obtains subsystem (such as broadband plasma body verifier, electron beam verifier or defect examine instrument, mask again Verifier, virtual verifier etc.) component or be coupled to it is described output obtain subsystem.In this way, reality described herein Output available for a variety of applications can be produced by applying example, and the application is examined including but not limited to wafer inspection, mask inspection, electron beam Test and examine again, measure.Controller can be changed based on the sample of reality output will be produced for it as described above.

Embodiments disclosed herein is better than manual classification.RT-SNV aids in the manual classification to defect.It uses RT- ADC attributes carry out automatic fitration SNV.It reduces defect classification effort and time.It also reduces people present in manual classification method For error.

Embodiments disclosed herein is also advantageous over the automatic classification based on layer.Can be across whole layer uses with general defect Based on grader, and the grader based on layer only works by indivedual layers.RT-SNV graders are saved in each layer On establish different SNV graders the time it takes.The grader based on layer of training data is needed with each of which layer Compare, RT-SNV graders can need less training data.RT-SNV graders are ready to use, provide consistent results, and nothing Any training is needed, and the grader based on layer is for example when running into the new lot with different defect types or process variations Need to reset.

Although the present invention is described on one or more specific embodiments, so it will be appreciated that, not departing from the scope of the present invention In the case of, other embodiments of the invention can be carried out.Therefore, the present invention be considered as being limited solely by the appended claims and its Reasonable dismissal.

Claims (14)

1. a kind of system, it includes：

Defect examines instrument again, wherein the defect, which examines instrument, has the objective table for being configured to holding chip again；And

Controller, it is configured to examine instrument communications again with the defect, wherein the controller is configured to use grader To identify the non-vision defect on the layer of the chip.

2. system according to claim 1, wherein the controller includes：Processor, it is configured to and the defect Instrument communications are examined again；Storage device, itself and the processor electronic communication containing the grader；And communication port, its with The processor electronic communication with the defect to examine instrument communications again.

3. system according to claim 1, wherein the controller by using the grader come filter pattern defect, At least one of Intensity attribute or energy properties and identify non-vision defect.

4. system according to claim 1, wherein it is scanning electron microscope SEM that the defect, which examines instrument, again.

5. system according to claim 1, wherein the non-vision defect is the non-vision defect SNV of SEM.

6. a kind of method, it includes：

Examine the image for the layer that instrument is produced on chip again using defect；

At least one attribute of described image is assessed using grader using processor；And

The non-vision defect on the layer of the chip is identified using the grader using the processor.

7. according to the method described in claim 6, its upper limit for further comprising defining non-vision defect using the processor And lower limit, wherein the non-vision defect identified is between the upper limit and the lower limit.

8. according to the method described in claim 6, wherein described grader is configured to filtering pattern defect.

9. according to the method described in claim 6, wherein described grader is configured to intensity filter attribute.

10. according to the method described in claim 6, wherein described grader is configured to filter energy attribute.

11. make according to the method described in claim 6, wherein described grader is configured on each layer of the chip With.

12. according to the method described in claim 6, wherein described generation uses scanning electron microscope SEM.

13. according to the method described in claim 6, wherein described non-vision defect is the non-vision defect SNV of SEM.

14. according to the method described in claim 6, compared with can wherein being performed in real time together with the generation and identify.