CN107918442B - Frequency adjusting device and method for adjusting frequency - Google Patents
Frequency adjusting device and method for adjusting frequency Download PDFInfo
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- CN107918442B CN107918442B CN201610882896.XA CN201610882896A CN107918442B CN 107918442 B CN107918442 B CN 107918442B CN 201610882896 A CN201610882896 A CN 201610882896A CN 107918442 B CN107918442 B CN 107918442B
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Abstract
The invention provides a frequency adjusting device, which comprises a voltage drop detector and a frequency eliminator. The voltage drop detector compares the supply voltage with a threshold voltage to output a comparison result. When the supply voltage is larger than the lower limit voltage, the frequency divider outputs the basic clock signal divided by a first value to be used as the result clock signal. When the supply voltage is less than the lower limit voltage, the frequency divider divides the basic clock signal by a second value to obtain the result clock signal.
Description
Technical Field
The present invention relates to a semiconductor chip, and more particularly, to a semiconductor circuit capable of adjusting a frequency.
Background
Complex digital circuitry can be implemented within the semiconductor chip. In general, digital circuit systems require a clock signal to perform synchronous operations. With the increasing demand of the industry for the product function, the clock of the digital circuit needs to be continuously increased. This requirement is also evident in the part of the central processing unit. However, to achieve high speed clock, the supply voltage for the digital circuitry must be relatively stable. If the supply voltage to the digital circuitry is not stable, delays and errors in the digital circuitry are likely to result. However, the external environment may cause unstable supply voltage, such as noise generated by the circuit board itself connected to the chip, which may cause temporary voltage disturbance or drop of the voltage supplied to the digital circuitry. Therefore, there is a need for a chip designer to design a device that can quickly respond to voltage disturbances or drops, and allow stable operation of digital circuitry without errors.
Disclosure of Invention
An objective of the present invention is to provide a frequency adjustment apparatus, which can quickly reduce the frequency of a basic clock signal when a supply voltage suddenly drops or is unstable, so as to maintain the normal operation of a rear digital circuit.
Another objective of the present invention is to provide a frequency adjustment apparatus, which can suppress glitches or noise when down-converting a basic clock signal.
Another objective of the present invention is to provide a frequency adjustment apparatus, which can flexibly adjust the lower limit voltage of the droop detector according to the critical path of the rear digital circuit.
According to an embodiment of the present invention, a frequency adjustment apparatus is provided. The frequency adjusting device comprises a voltage drop detector and a frequency divider. The voltage drop detector receives a supply voltage. The voltage drop detector compares the supply voltage with a threshold voltage to output a comparison result. The frequency divider receives a basic clock signal. The frequency divider outputs a result clock signal according to the comparison result. When the supply voltage is larger than the lower limit voltage, the frequency divider outputs the basic clock signal divided by a first value to be used as the result clock signal. When the supply voltage is less than the lower limit voltage, the frequency divider divides the basic clock signal by a second value to obtain the result clock signal.
According to another embodiment of the present invention, a frequency adjustment apparatus is provided. The frequency adjusting device comprises a sample digital circuit module, a delay test unit, a delay state determiner and a frequency divider. The sample digital circuit module receives a switching signal to output a sample digital circuit module output signal. The delay test unit comprises a delay unit and an exclusive OR unit. The delay unit receives the sample digital circuit block output signal and delays the sample digital circuit block output signal by at least one cycle. The XOR operation unit receives the output signal of the sample digital circuit module and the delayed output signal of the sample digital circuit module to perform XOR operation and output a first operation result. The delay state determiner receives the first operation result and outputs a frequency division indicating signal. The frequency divider receives the frequency dividing indication signal to determine a frequency dividing value. The frequency divider divides a basic clock signal by the divided frequency value to output a resultant clock signal.
According to another embodiment of the present invention, a frequency divider is provided. The frequency divider includes a mask clock generator and a frequency dividing unit. The mask clock generator receives a basic clock signal and a down-conversion indication signal. The down-conversion indication signal comprises a down-conversion start pulse and a down-conversion end pulse. The mask clock generator outputs a mask clock. The mask clock suppresses potential switching during the down start pulse and the down end pulse. The frequency dividing unit comprises a plurality of D-type flip-flops. The D-type flip-flops take the mask clock as a trigger input, and the frequency dividing unit outputs a result clock signal.
In accordance with another embodiment of the present invention, a method for suppressing noise during switching frequencies is provided. The method comprises the following steps. First, a supply voltage and a threshold voltage are compared to output a comparison result. Then, the comparison result is delayed by at least one period of the basic clock signal to generate a first comparison result delay signal. Then, the first comparison result delay signal is delayed by at least one period of the basic clock signal to generate a second comparison result delay signal. Then, the comparison result and the second comparison result delay signal are processed with an XOR operation to generate a down-conversion indication signal. The down-conversion indication signal comprises a down-conversion start pulse and a down-conversion end pulse. Then, an XOR operation is performed on the down indication signal and the base clock signal to generate a mask clock. The mask clock suppresses the potential switching of the base clock signal during the down start pulse and the down end pulse. Then, the mask clock is down-converted according to the down-conversion indication signal.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1A shows a state of temporary instability of the supply voltage;
FIG. 1B shows a schematic diagram of down-conversion over a period of time for a change in supply voltage;
FIG. 2A illustrates an embodiment of a frequency adjustment apparatus;
FIG. 2B shows another embodiment of a frequency adjustment apparatus;
FIG. 3 shows an embodiment of a frequency divider;
FIG. 4 is a waveform diagram of a down conversion indicator;
FIG. 5 shows an embodiment of a divide signal generator;
FIG. 6 is a waveform diagram of a related signal for generating a down-conversion indicating signal;
FIG. 7 illustrates one embodiment of a frequency adjustment apparatus; and
fig. 8 shows a flow chart of a method of suppressing noise during switching of frequencies.
The element numbers in the figures are illustrated as follows:
101 pressure drop detector
102 supply voltage
103 comparison result
104 frequency divider
105 basic clock signal
106 result clock signal
107 frequency-dividing signal generator
108 down-conversion indication signal
301 mask clock generator
302 frequency division unit
303 mask clock
304 trigger
305 flip-flop
306 nand gate
307 nand operation result
401 Down start pulse
402 Down end pulse
501 first D type flip-flop
502 second D-type flip-flop
503 exclusive or gate
504 first comparison result delay signal
505 second comparison result delay signal
601 first sample digital circuit module
602 second sample digital circuit module
603 third sample digital circuit module
604 first delay unit
605 first exclusive OR operation unit
606 delay state decider
607 frequency divider
608 switching signal
609 first sample digital circuit module output signal
610 first operation result
611 frequency division indication signal
613 second sample digital circuit module output signal
614 third sample digital circuit block output signal
615 delay unit
616 XOR operation unit
617 delay unit
618 XOR operation unit
619 second operation result
620 third operation result
621 first delay test unit
622 second delay test unit
623 third delay test Unit
624 digital circuit
Steps S801, S802, S803, S804, S805, S806
Detailed Description
Fig. 1A shows a state where the supply voltage is temporarily unstable. The supply voltage VDD supplied to a digital circuit may cause temporary voltage instability or voltage drop for various reasons. For example, in FIG. 1A, during a time intermediate between time t1 and time t2, the supply voltage VDD may drop and become unstable. FIG. 1B shows a schematic diagram of down-conversion over a certain period of time for a change in supply voltage. Referring to fig. 1B, in an embodiment, a clock of the digital circuit may be down-converted by a frequency adjusting device in a period between time t1 and time t 2. Therefore, the digital circuit can be ensured to operate normally without generating errors due to sudden voltage drop. In addition, another object of the present invention is to reduce the frequency of the clock in a very short time when the unstable supply voltage is detected.
Referring to fig. 2A, a frequency adjustment apparatus 100 according to an embodiment of the invention includes a voltage drop detector 101 and a frequency divider 104. The voltage drop detector 101(voltage drop detector) receives a supply voltage 102. The voltage drop detector 101 compares the supply voltage 102 with a threshold voltage (threshold voltage) to output a comparison result 103. The frequency divider 104 receives a base clock signal 105. The frequency divider 104 outputs a result clock signal 106 according to the comparison result 103. Wherein, when the supply voltage 102 is greater than the lower limit voltage, the frequency divider 104 outputs a basic clock signal 105 as the resultant clock signal 106. When the supply voltage 102 is less than the lower limit voltage, the frequency divider 104 divides the frequency of the base clock signal 105 into the resulting clock signal 106. The voltage drop detector 101 may be a comparator. The low-limit voltage can be selected by several groups of voltages. The resulting clock signal may be used by subsequent digital circuitry 624. The digital circuit 624 may be a Central Processing Unit (CPU).
In some embodiments, referring to fig. 2B and fig. 6, the frequency adjustment apparatus 100 further includes a frequency divider 107. The frequency-dividing signal generator 107 generates a frequency-dividing indication signal 108 according to the comparison result 103. The down indication signal 108 comprises a down start pulse 401 and a down end pulse 402.
Referring to fig. 2A, 2B, 5 and 6, the frequency-divided signal generator 107 receives the comparison result 103(SEL) from the voltage-drop detector 101. When the comparison result 103 is low, it indicates that the supply voltage 102 is normal. When the comparison result 103 is high, it indicates that the supply voltage 102 is lower than the lower limit voltage. At this time, the basic clock signal 105 needs to be immediately down-converted to ensure that the following digital circuits will not malfunction.
In some embodiments, referring to fig. 2A, fig. 2B and fig. 5, the frequency-dividing signal generator 107 includes a first D-type flip-flop 501, a second D-type flip-flop 502 and an exclusive-or gate (XORgate) 503. The first D-flip flop 501 receives the comparison result 103. The output of the first D-flip flop 501 is connected to the input of the second D-flip flop 502. The XOR gate 503 receives the comparison result 103 and the output of the second D-flip flop 502 to perform an XOR operation and output the down indication signal 108.
Referring to fig. 5 and 6, the first D-flip flop 501 delays the comparison result 103 for a first time to generate a first comparison result delayed signal 504(SEL _ D). Next, the second D-flip flop delays the first comparison result delayed signal 504 a second time to generate a second comparison result delayed signal 505(SEL _ DD). The second comparison result delay signal 505 is delayed by one cycle of the base clock relative to the first comparison result delay signal 504. Next, the XOR gate 503 receives the comparison result 103 and the second comparison result delay signal 505 to perform an exclusive or (XOR) operation to generate the down indicating signal 108. The down indication signal 108 comprises a down start pulse 401 and a down end pulse 402.
In some embodiments, referring to fig. 2A, fig. 2B and fig. 3, the frequency divider 104 includes a mask clock (mask clock) generator 301 and a frequency divider unit 302. The masking clock generator 301 receives a base clock signal 105 and a down-conversion indication signal 108. Referring to fig. 6, the down-conversion indication signal 108 includes a down-conversion start pulse 401 and a down-conversion end pulse 402. The mask clock generator 301 outputs a mask clock 303. The mask clock 303 suppresses potential switching during the down start pulse 401 and the down end pulse 402. The frequency dividing unit 302 includes a plurality of D-type flip- flops 304 and 305, the D-type flip-flops have the mask clock 303 as a trigger input, and the frequency dividing unit 303 outputs a result clock signal 106.
In some embodiments, the D-flip flops include a first D-flip flop 304 and a second D-flip flop 305. The first D-flip flop 304 is triggered by the negative edge with the masked clock 303. The second D-flip flop 305 is triggered by the negative edge with the masked clock 303. The output of the first D-flip flop 304 is connected to the input of the second D-flip flop 305. In some embodiments, the frequency divider 104 further comprises a nand gate 306. The NAND gate 306 receives the output of the first D-flip flop 304 and the output of the second D-flip flop 305, performs a NAND operation, and outputs a NAND operation result 307. The NAND operation result 307 is input to the first D-flip flop 304.
Referring to fig. 3 and 4, the mask clock generator 301 may be a nand gate. The down indicating signal 108 is inverted and then input to the NAND gate (NAND gate), and the basic clock signal 105 is input to the NAND gate. The nand gate outputs the mask clock 303 after performing a nand operation. The masking clock 303 is at a low level during the down start pulse 401 and the down end pulse 402 due to the nand operation. That is, the masking clock 303 suppresses the potential switching of the base clock signal 105 during the down start pulse 401 and the down end pulse 402. Next, the masked clock 303 is divided to generate the result clock signal 106. Since the masking clock 303 suppresses the potential switching of the base clock signal 105 during the down start pulse 401 and the down end pulse 402, glitches and noises at the beginning and end of frequency division can be avoided in the subsequent frequency division process. Meanwhile, only one period of the basic clock signal is spent from the detection of the abnormal supply voltage to the start of the frequency reduction, and the response is very quick.
Referring to fig. 4 and 7, in some embodiments, the frequency of the resultant clock signal 106 before the start of the down start pulse 401 is 1/2 of the base clock signal 105. After the down start pulse 401, the frequency of the result clock signal 106 is 1/3 of the base clock signal 105. Referring to fig. 7, the base clock signal 105 has been down-converted to the 1/2 frequency of the base clock signal 105 before entering the sample-and-digital circuit block 601. Divider 607 has two options, one to divide the frequency of base clock signal 105 by 2 and the other to divide base clock frequency 105 by 3. Therefore, under normal conditions, the frequency divider 607 divides the base clock signal 105 by 2 and outputs the result clock signal 106. Between the down start pulse 401 and the down end pulse 402, the frequency divider 607 divides the base clock signal 105 by 3 and outputs the result clock 106.
Referring to fig. 7, a frequency adjustment apparatus 600 according to another embodiment of the present invention includes a sample digital circuit module 601, a delay test unit 621, a delay status determiner 606 and a frequency divider 607. The sample digital circuit block 601 receives a switching signal 608 to output a sample digital circuit block output signal 609. The delay test unit 621 includes a delay unit 604 and an exclusive-or unit 605. The delay unit 604 receives the sample digital circuit block output signal 609 and delays the sample digital circuit block output signal 609 by at least one cycle. The xor operation unit 605 receives the sample digital circuit block output signal 609 and the delayed sample digital circuit block output signal 609 to perform an xor operation and output a first operation result 610.
If the output of the xor operation unit 605 indicates that the sample-digital circuit block output signal 609 and the high potential of the sample-digital circuit block output signal 609 after the delay overlap, it indicates that the delay of the sample-digital circuit block output signal 609 is not serious, and therefore down-conversion may not be required. If the output of the xor operation unit 605 indicates that there is no overlapping portion of the sample digital circuit block output signal 609 and the sample digital circuit block output signal 609 after the delay, it indicates that the delay of the sample digital circuit block output signal 609 is serious, and this situation may require down-conversion.
The delay state determiner 606 receives the operation result 610 and outputs a frequency division indication signal 611. The frequency divider 607 receives the frequency division indication signal 611 to determine a frequency division value. The frequency divider 607 divides a basic clock signal 105 by the divided frequency value to output a resultant clock signal 106.
In some embodiments, the sample digital circuit block 601 is a first sample digital circuit block 601, and the frequency adjustment apparatus 600 further includes a second sample digital circuit block 602 and a third sample digital circuit block 603. The output of the first sample digital circuit block 601 is connected to the input of the second sample digital circuit block 602, and the output of the second sample digital circuit block 602 is connected to the input of the third sample digital circuit block 603. The first sample digital circuit block 601 may be a critical path (critical path) that replicates a segment of the digital circuit 624. Similarly, the second sample digital circuit block 602 may also be a critical path in the replica digital circuit 624. The third sample digital circuit block 603 may also be a block that replicates a critical path in a section of digital circuit 624.
In some embodiments, the delay test unit 621 is a first delay test unit 621. The frequency adjustment apparatus 600 further includes a second delay test unit 622 and a third delay test unit 623. The output of the second sample digital circuit block 602 is connected to the second delay test unit 622. The output of the third sample digital circuit block 603 is connected to a third delay test unit 623. The second sample digital circuit block 602 outputs a second sample digital circuit block output signal 613. The third sample digital circuit block 603 outputs a third sample digital circuit block output signal 614.
In some embodiments, the second delay test unit 622 includes a delay unit 615 and an exclusive-or unit 616. The delay unit 615 receives the second sample digital circuit block output signal 613 and delays the second sample digital circuit block output signal 613 by at least one cycle. The XOR operation unit 616 receives the second SAM output signal 613 and the delayed second SAM output signal 613 to perform an XOR operation and output a second operation result 619.
In some embodiments, the third delay test unit 623 includes a delay unit 617 and an XOR operation unit 618. The delay unit 617 receives the third sample digital circuit block output signal 614 and delays the third sample digital circuit block output signal 614 by at least one cycle. The xor operation unit 618 receives the third sample-and-digital-circuit-module output signal 614 and the delayed third sample-and-digital-circuit-module output signal 614 for xor operation and outputting a third operation result 620. In some embodiments, the delay status determiner 606 is a multiplexer. The multiplexer further receives the second operation result 619 and the third operation result 620 to output the frequency-dividing indication signal 611. The operations of the second delay test unit 622 and the third delay test unit 623 are the same as the first delay test unit 621, and are not described herein again.
The first operation result 610, the second operation result 619, and the third operation result 620 can be used to select different low-limit voltages for the droop detector 101. If the critical path is long and the voltage drop may be more finely controlled, a third operation 620 may be used to select a higher threshold voltage. If the critical path is short, the voltage drop may not need to be controlled very finely, and a lower threshold voltage may be selected using the first operation result 610. It is known to those skilled in the art that the delay test unit and the delay unit xor operation unit can be implemented by digital circuits, and the implementation details thereof are not described herein.
Referring to fig. 2 and 7, a frequency adjustment apparatus 100 according to another embodiment of the present invention includes a voltage drop detector 101 and a frequency divider 104. The voltage drop detector 101 receives a supply voltage 102. The voltage drop detector 101 compares the supply voltage 102 with a threshold voltage to output a comparison result 103. The frequency divider 104 receives a base clock signal 105. The frequency divider 104 outputs a result clock signal 106 according to the comparison result 103. When the supply voltage 102 is greater than the lower limit voltage, the frequency divider 104 divides the basic clock signal 105 by a first value to obtain the resultant clock signal 106. When the supply voltage 102 is less than the lower limit voltage, the frequency divider 104 divides the frequency of the base clock signal 105 by a second value to obtain the result clock signal 106. In some embodiments, the first value is 2 and the second value is 3. In some embodiments the first value is bit 1 and the second value is 2. When the first value is 1, the base clock signal 105 can be directly output as the result clock signal 106 without frequency division.
Referring to fig. 6 and 8, a method for suppressing noise during a switching frequency according to an embodiment of the present invention is provided, which includes the following steps. First, a supply voltage 102 and a low-limit voltage 102 are compared to output a comparison result 103 (step S801). Next, the comparison result 103 is delayed to generate a first comparison result delayed signal 504 (step S802). Then, the first comparison result delay signal 504 is delayed by at least one period of the basic clock signal 105 to generate a second comparison result delay signal 505 (step S803). Then, an exclusive-or operation is performed on the comparison result 103 and the second comparison result delay signal 505 to generate a down-conversion indication signal 108 (step S804). The down indication signal 108 comprises a down start pulse 401 and a down end pulse 402. Then, an exclusive or operation is performed on the inverted signal of the down indicating signal 108 and the base clock signal 105 to generate a mask clock 303 (step S805). The mask clock 303 suppresses the potential switching of the base clock signal 105 during the down start pulse 401 and the down end pulse 402. Then, the masking clock 303 is down-clocked according to the down-clocking indication signal 108 (step S806). Wherein the steps may not be in a fixed order. Some steps can be interchanged in sequence as long as the same effect is achieved.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A frequency adjustment apparatus, comprising:
a voltage drop detector, receiving a supply voltage, comparing the supply voltage with a lower limit voltage to output a comparison result;
a frequency divider, receiving a basic clock signal, the frequency divider outputting a result clock signal according to the comparison result; and
a frequency-dividing signal generator, which generates a frequency-dividing indication signal according to the comparison result, the frequency-dividing indication signal includes a frequency-dividing start pulse and a frequency-dividing end pulse,
wherein, when the supply voltage is greater than the lower limit voltage, the frequency divider outputs the basic clock signal divided by a first value as the result clock signal, when the supply voltage is less than the lower limit voltage, the frequency divider divides the basic clock signal by a second value as the result clock signal,
the frequency-dividing signal generator comprises a first D-type trigger, a second D-type trigger and an XOR gate, wherein the first D-type trigger receives the comparison result, the output of the first D-type trigger is connected with the input of the second D-type trigger, and the XOR gate receives the comparison result and the output of the second D-type trigger to perform XOR operation and output the frequency-dividing indication signal.
2. The frequency adjustment device of claim 1, wherein the frequency divider comprises:
a mask clock generator, receiving the basic clock signal and a frequency-down indication signal, the frequency-down indication signal including a frequency-down start pulse and a frequency-down end pulse, the mask clock generator outputting a mask clock, the mask clock inhibiting potential switching during the frequency-down start pulse and the frequency-down end pulse; and
and the frequency dividing unit comprises a plurality of D-type flip-flops, the D-type flip-flops take the mask clock as trigger input, and the frequency dividing unit outputs the result clock signal.
3. The apparatus of claim 1, wherein the first value is 2 and the second value is 3.
4. A method of suppressing noise during a switching frequency, comprising:
comparing a supply voltage with a threshold voltage to output a comparison result;
delaying the comparison result to generate a first comparison result delayed signal;
delaying the first comparison result delayed signal by at least one period of the basic clock signal to generate a second comparison result delayed signal;
performing an exclusive-or operation on the comparison result and the second comparison result delay signal to generate a frequency-down indication signal, wherein the frequency-down indication signal comprises a frequency-down start pulse and a frequency-down end pulse;
performing an exclusive-or operation on the down-conversion indication signal and the basic clock signal to generate a mask clock, wherein the mask clock suppresses the potential switching of the basic clock signal during the down-conversion start pulse and the down-conversion end pulse; and
the mask clock is down-converted according to the down-conversion indication signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138750A (en) * | 2011-12-05 | 2013-06-05 | 创意电子股份有限公司 | Clock pulse data recovery circuit |
| CN103176029A (en) * | 2011-12-26 | 2013-06-26 | 索尼公司 | Voltage amplitude detection circuit, information storage device, communication device, and voltage amplitude detection method |
| CN103176587A (en) * | 2011-12-23 | 2013-06-26 | 金宝电子工业股份有限公司 | Solar power management module, method and electronic computer |
| CN103731142A (en) * | 2012-10-15 | 2014-04-16 | 成一电子股份有限公司 | Multi-mode frequency divider |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138750A (en) * | 2011-12-05 | 2013-06-05 | 创意电子股份有限公司 | Clock pulse data recovery circuit |
| CN103176587A (en) * | 2011-12-23 | 2013-06-26 | 金宝电子工业股份有限公司 | Solar power management module, method and electronic computer |
| CN103176029A (en) * | 2011-12-26 | 2013-06-26 | 索尼公司 | Voltage amplitude detection circuit, information storage device, communication device, and voltage amplitude detection method |
| CN103731142A (en) * | 2012-10-15 | 2014-04-16 | 成一电子股份有限公司 | Multi-mode frequency divider |
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