CN107908578A - The general DMA transfer method driven based on PXIe buses and VISA - Google Patents
The general DMA transfer method driven based on PXIe buses and VISA Download PDFInfo
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- CN107908578A CN107908578A CN201711321310.3A CN201711321310A CN107908578A CN 107908578 A CN107908578 A CN 107908578A CN 201711321310 A CN201711321310 A CN 201711321310A CN 107908578 A CN107908578 A CN 107908578A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/28—DMA
- G06F2213/2806—Space or buffer allocation for DMA transfers
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Abstract
The invention discloses the general DMA transfer method based on PXIe buses and VISA drivings, including it is provided with the PXIe cabinets of PXIe buses and PXI e interface, the PCI9054 bridge pieces being connected with PXI e interface, the FPGA boards being connected with PCI9054 bridge pieces and the RS422 sending and receiving modules being connected with FPGA boards；General VISA driving DMA transfer methods based on PXIe buses, specifically include following steps：Software is installed；Connect equipment；Installation driving；Test DMA communications.The present invention only needs to change load document, can just be directed to the DMA data transfer of respective platform；Not only PXIe bus transfer datas that are easy but also time saving and energy saving, but also can realizing high speed had been developed, have met performance requirement；It is simple and convenient, and effectively realize modularization, while solve to solve DMA exploitation hardly possiblies, it is impossible to the problem of realizing high speed performance.
Description
Technical field
The present invention relates to technical field of communication field, is the general DMA based on PXIe buses and VISA drivings specifically
Transmission method.
Background technology
VISA software-drivens are the current popular driving developing instruments of NI companies exploitation.Can be quick by VISA
Ready-made driving is generated, is had for various equipment and bus development function basic function interface VISA storehouses.
In test fields of measurement, it is often necessary to transmit mass data, it is a kind of big to carry out high speed transmission data using DMA technology
Trend.Also have on the market and develop DMA transfer using technologies such as DDK, WDM, although this kind of method can be realized, need more
The problems such as time, introduction require height, and the construction cycle is long, highly significant.
The content of the invention
It is an object of the invention to provide the general DMA transfer method based on PXIe buses and VISA drivings, it is only necessary to repaiies
Change load document, can just be directed to the DMA data transfer of respective platform；Not only developed easy but also time saving and energy saving, and but also can realize high speed
PXIe bus transfer datas, meet performance requirement；It is simple and convenient, and effectively realize modularization, while solve solution DMA and open
Raise difficult questions, it is impossible to the problem of realizing high speed performance.
The present invention is achieved through the following technical solutions：The general DMA transfer method driven based on PXIe buses and VISA, institute
State general DMA transfer method to realize based on DMA transfer system, the DMA transfer system includes being provided with PXIe buses and PXIe
The PXIe cabinets of interface, the PCI9054 bridge pieces being connected with PXI e interface, the FPGA boards being connected with PCI9054 bridge pieces and with
The RS422 transceiver modules of FPGA boards connection.
General VISA driving DMA transfer methods based on PXIe buses, specifically include following steps：
Step S1：Software is installed；Specifically refer to that CVI2009 and NI MAX are installed on PXI cabinets, build software loop
Border；
Step S2：Connect equipment；FPGA boards are connected with PXI e interface；
Step S3：Installation driving；Pass through NI MAX load drivers；
Step S4：Test DMA communications；
Further, in order to preferably realize the present invention, the step S3 specifically includes following steps：
Step S31：NI VISA Driver Wizard are opened, select equipment, into next step；
Step S32：Device parameter is filled in, indicates that the driving uses interruption；
Step S33：Configure Bar0 spaces, configuration status status register；It is 0x00000900 to set 0x68 addresses, initially
Change and interrupt.
Further, in order to preferably realize the present invention, the step S4 specifically includes following steps：
Step S41：Loading configuration file；
Step S42：Open hardware FPGA resource；
Step S43：Register interrupt resources；
Step S44：DMA is initialized, configures memory headroom；Configuration memory headroom is not met, then is exited the program；Configure memory
Space, which meets, then to carry out in next step；
Step S45：DMA read operations and DMA write operation；
Step S46：DMA performance tests.
Further, in order to preferably realize the present invention, the step S41 specifically includes following steps：
Step S411：Load form configuration file；
Step S421：By CVI system functions, table content is read.
Further, in order to preferably realize the present invention, the step S42 specifically includes following steps：
Step S421：The explorer of acquiescence is opened, obtains the reply handle of resource management；
Step S422：Obtain resource descriptor and use function；
Step S423：Open equipment and use function；Find the resource handle for carrying out hardware operation；By the handle, indicate
The Bar spaces to be operated, complete the read-write operation to hardware register.
Further, in order to preferably realize the present invention, the step S43 specifically includes following steps：
Step S431：Register interrupt resources；
Step S432：PXI is registered with the event interrupted；
Step S433：Interrupt register state is read, enables and interrupts.
Further, in order to preferably realize the present invention, the step S44 specifically includes following steps：
Step S441：Obtain introversive handle；
Step S442：The resource of storage allocation handle；
Step S443：The physical start address of DMA transfer PCI is set；
Step S444：The address of DMA transfer Local Bus is set；
Step S445：DMA transfer FPGA is set to put data first address；
Step S446：DMA transfer bit wide and preparation are set.
Further, in order to preferably realize the present invention, the DMA read operations in the step S45 specifically include following step
Suddenly：
Step SD451：DMA directions are set to read；
Step SD452：DMA is set to prepare the length read；Memory headroom of the length no more than opening space application
Size；
Step SD453：DMA is set to enable and transmit；
Step SD454：Start DMA to read；
Step SD455：DMA is detected to complete；Read PXIe bus datas.
Further, in order to preferably realize the present invention, the DMA write operation in the step S45 specifically includes following step
Suddenly：
Step SX451：DMA directions are set to write；
Step SX452：Reading DMA data；
Step SX453：DMA is set to prepare the length read；
Step SX454：DMA is set to enable and transmit；
Step SX455：Start DMA to read；
Step SX456：DMA is detected to complete；Reading DMA data.
Compared with prior art, the present invention haing the following advantages and beneficial effect：
(1) present invention only needs to change load document, can just be directed to the DMA data transfer of respective platform；
(2) present invention had not only developed PXIe bus transfer datas that are easy but also time saving and energy saving, but also can realizing high speed, met performance
Demand；
(3) present invention is simple and convenient by being driven based on PXIe bus VISA technological development DMA, and effectively realizes
Modularization, while solve to solve DMA exploitation hardly possiblies, it is impossible to the problem of realizing high speed performance.
Brief description of the drawings
Fig. 1 is the system connection diagram of the present invention；
Fig. 2 is workflow schematic diagram of the present invention；
Fig. 3 is DMA test method work flow diagrams in the present invention；
Fig. 4 is DMA write operation flow diagram in the present invention；
Fig. 5 flows operating process schematic diagram for DMA in the present invention；
Fig. 6 is the system level graph of a relation of the present invention.
Embodiment
The embodiment of the present invention is described below in detail, in the present invention, unless otherwise clearly defined and limited, term
The term such as " installation ", " connected ", " connection ", " fixation " should be interpreted broadly, for example, it may be being fixedly connected or can
Dismantling connection, or be integrally connected；Can mechanically connect or be electrically connected；It can be directly connected, can also pass through
Intermediary is indirectly connected, and can be the connection inside two elements.For the ordinary skill in the art, Ke Yigen
Understand the concrete meaning of above-mentioned term in the present invention according to concrete condition.
The present invention is described in further detail with reference to embodiment, but the implementation of the present invention is not limited to this.
Embodiment 1：
The present invention is achieved through the following technical solutions, and as shown in figs 1 to 6, is driven based on PXIe buses and VISA general
DMA transfer method, the general DMA transfer method realize that the DMA transfer system includes being provided with based on DMA transfer system
The PXIe cabinets of PXIe buses and PXI e interface, the PCI9054 bridge pieces that are connected with PXI e interface, be connected with PCI9054 bridge pieces
FPGA boards and the RS422 transceiver modules being connected with FPGA boards.
The present invention only needs to change load document, can just be directed to the DMA data transfer of respective platform；Not only developed easy but also saved
Shi Shengli, and can realize the PXIe bus transfer datas of high speed, meet performance requirement；It is simple and convenient, and effectively realize mould
Block, while solve to solve DMA exploitation hardly possiblies, it is impossible to the problem of realizing high speed performance.
The other parts of the present embodiment are same as the previously described embodiments, and so it will not be repeated.
Embodiment 2：
The present embodiment does further optimization on the basis of above-described embodiment, as Figure 1-Figure 5, based on PXIe buses
General VISA drives DMA transfer method, specifically includes following steps：
Step S1：Software is installed；Specifically refer to that CVI2009 and NI MAX are installed on PXI cabinets, build software loop
Border.
Step S2：Connect equipment；FPGA boards are connected with PXI e interface.
Step S3：Installation driving；Pass through NI MAX load drivers.
Step S4：Test DMA communications.
It should be noted that pass through above-mentioned improvement, it is only necessary to change load document, can just be directed to the DMA numbers of respective platform
According to transmission；Not only PXIe bus transfer datas that are easy but also time saving and energy saving, but also can realizing high speed had been developed, have met performance requirement；Simply
It is convenient, and effectively realize modularization, while solve to solve DMA exploitation hardly possiblies, it is impossible to the problem of realizing high speed performance.
The other parts of the present embodiment are same as the previously described embodiments, and so it will not be repeated.
Embodiment 3：
The present embodiment does further optimization on the basis of above-described embodiment, as Figure 1-Figure 5, based on PXIe buses
General VISA drives DMA transfer method, specifically includes following steps：
Step S1：Software is installed；Specifically refer to that CVI2009 and NI MAX are installed on PXI cabinets, build software loop
Border.
Step S2：Connect equipment；FPGA boards are connected with PXI e interface.
Step S3：Installation driving；Pass through NI MAX load drivers；Specifically include following steps：
Step S31：NI VISA Driver Wizard are opened, select equipment, into next step.
Step S32：Device parameter is filled in, indicates that the driving uses interruption.
Step S33：Configure Bar0 spaces, configuration status status register；It is 0x00000900 to set 0x68 addresses, initially
Change and interrupt.
Step S4：Test DMA communications；Specifically include following steps：
Step S41：Loading configuration file；Specifically include following steps：
Step S411：Load form configuration file；
Step S421：By CVI system functions, table content is read.
Step S42：Open hardware FPGA resource；Specifically include following steps：
Step S421：The explorer of acquiescence is opened, obtains the reply handle of resource management.
Step S422：Obtain resource descriptor and use function.
Step S423：Open equipment and use function；Find the resource handle for carrying out hardware operation；By the handle, indicate
The Bar spaces to be operated, complete the read-write operation to hardware register.
Step S43：Register interrupt resources；Specifically include following steps：
Step S431：Register interrupt resources.
Step S432：PXI is registered with the event interrupted.
Step S433：Interrupt register state is read, enables and interrupts.
Step S44：DMA is initialized, configures memory headroom；Configuration memory headroom is not met, then is exited the program；Configure memory
Space, which meets, then to carry out in next step；Specifically include following steps：
Step S441：Obtain introversive handle；
Step S442：The resource of storage allocation handle；
Step S443：The physical start address of DMA transfer PCI is set；
Step S444：The address of DMA transfer Local Bus is set；
Step S445：DMA transfer FPGA is set to put data first address；
Step S446：DMA transfer bit wide and preparation are set.
Step S45：DMA read operations and DMA write operation；
The DMA read operations specifically include following steps：
Step SD451：DMA directions are set to read；
Step SD452：DMA is set to prepare the length read；Memory headroom of the length no more than opening space application
Size；
Step SD453：DMA is set to enable and transmit；
Step SD454：Start DMA to read；
Step SD455：DMA is detected to complete；Read PXIe bus datas.
The DMA write operation specifically includes following steps：
Step SX451：DMA directions are set to write；
Step SX452：Reading DMA data；
Step SX453：DMA is set to prepare the length read；
Step SX454：DMA is set to enable and transmit；
Step SX455：Start DMA to read；
Step SX456：DMA is detected to complete；Reading DMA data.
Step S46：DMA performance tests；Specifically refer to：When testing DMA performances, step S41- steps are directly pressed first
S44 is operated, then by thread and mutual exclusion lock, to distinguish DMA read operations and the DMA write operation in invocation step S45, i.e.,
Read and write by DMA, send and receive RS422 data to realize the test to data performance.
The other parts of the present embodiment are same as the previously described embodiments, and so it will not be repeated.
Embodiment 4：
The present embodiment does further optimization on the basis of above-described embodiment, as Figure 1-Figure 5, based on PXIe buses
General VISA drives DMA transfer method, specifically includes following steps：
Step S1：Software is installed；Specifically refer to：CVI2009 and NI MAX are installed on PXI cabinets, build software loop
Border.
Step S2：Connect equipment；FPGA boards are connected with PXI e interface.Pass through the 4Mpbs's of 16 passage of function module
RS422 buses are used to test.The receiving terminal of RS422 is shorted to the transmitting terminal of RS422.
Step S3：Installation driving；Pass through NI MAX load drivers.Specifically include following steps：
Step S31：NI VISA Driver Wizard are opened, select equipment, into next step.
Step S32：Device parameter is filled in, inserts PID, chooses " this device generates interrupt " choosings
, indicate that the driving uses interruption.
Step S33：Configure Bar0 spaces, configuration status status register；It is 0x00000900 to set 0x68 addresses, initially
Change and interrupt.
Step S4：Test DMA communications；Open and start test software, complete DMA initial configurations, then read and write using DMA
Data are sent, and are received by receiving channel, the data that sendaisle is sent.Verification DMA can normally read and write, and speed
Test.Specifically include following steps：
Step S41：Loading configuration file；Specifically include following steps.
Step S411：Load form configuration file；, as shown in Table 1.
Step S421：By CVI system functions, table content is read.
Step S42：Open hardware FPGA resource；Specifically include following steps.
Step S421：The explorer of acquiescence is opened, obtains the reply handle of resource management.
Step S422：Obtain resource descriptor and use function.
Step S423：Open equipment and use function；Find the resource handle for carrying out hardware operation；By the handle, indicate
The Bar spaces to be operated, complete the read-write operation to hardware register.
Step S43：Register interrupt resources.Specifically include following steps：
Step S431：Register interrupt resources.
Step S432：PXI is registered with the event interrupted.
Step S433：Interrupt register state is read, enables and interrupts.
Step S44：DMA is initialized, configures memory headroom；Configuration memory headroom is not met, then is exited the program；Configure memory
Space, which meets, then to carry out in next step.Specifically include following steps：
Step S441：Obtain introversive handle.
Step S442：The resource of storage allocation handle.
Step S443：The physical start address of DMA transfer PCI is set.
Step S444：The address of DMA transfer Local Bus is set.
Step S445：DMA transfer FPGA is set to put data first address.
Step S446：DMA transfer bit wide and preparation are set.
Step S45：DMA read operations and DMA write operation.
The DMA read operations specifically include following steps：
Step SD451：DMA directions are set to read.
Step SD452：DMA is set to prepare the length read；Memory headroom of the length no more than opening space application
Size.
Step SD453：DMA is set to enable and transmit.
Step SD454：Start DMA to read.
Step SD455：DMA is detected to complete；Read PXIe bus datas.
The DMA write operation specifically includes following steps：
Step SX451：DMA directions are set to write.
Step SX452：Reading DMA data.
Step SX453：DMA is set to prepare the length read.
Step SX454：DMA is set to enable and transmit.
Step SX455：Start DMA to read.
Step SX456：DMA is detected to complete；Reading DMA data.
Step S46：DMA performance tests.Specifically refer to：When testing DMA performances, step S41- steps are directly pressed first
S44 is operated, to distinguish DMA read operations and the DMA write operation in invocation step S45, i.e., logical then by thread and mutual exclusion lock
DMA read-writes are crossed, send and receive RS422 data to realize the test to data performance.
The other parts of the present embodiment are same as the previously described embodiments, and so it will not be repeated.
Embodiment 4：
The present embodiment does further optimization on the basis of above-described embodiment, due to the backward compatible pci bus of PXIe, this hair
It is bright using PCI9054 chips and FPGA as hardware development platform, based on FPGA and PCI9054 bridge pieces come be realize VISA drive DMA
Transmission.
As shown in fig. 6, the hardware layer, driving layer and software layer being connected with each other successively are included in the system.
The hardware layer includes F and is connected with the FPGA module of function module, the PCI9054 bridges being connected with each other with FPGA module
Piece module；The driving layer includes driving by PXIe buses and the VISA that PCI9054 bridge pieces module is connected with each other；It is described soft
Part layer includes and VISA drivings and sequentially connected software API and UI modules.
UI modules：Major function is to realize that instruction issues and data monitoring；
API module：Major function is that the interface function of VISA feature operations and related algorithm operation is provided for UI, passes through this
A little interface functions, which are realized to drive VISA, carries out command operating, state passback and the read-write of data；
VISA drive modules：Major function is to receive the instruction of API, by pci bus, initiates the reading to FPGA registers
Write, and configured by related register, DMA transfer is initiated by PCI9054 bridge pieces, realizes the read-write operation to data.
Pci bus：Major function is to realize driving and the data interaction of hardware FPGA.
PCI9054 bridge chips：As shown in table 1：PCI9054 Register Allocation Tables, major function be connection pci bus and
The tie of FPGA buses.
Table 1
FPGA and hardware module：Mainly function realizes the operation operated to PCI9054 and to correlation module.
It is as follows for DMA communication tests, specific implementation step：
Step S41：Loading configuration file.As shown in showing table one.
Step S42：Open hardware FPGA resource.
Step S43：Register interrupt resources.
Step S44：DMA is initialized, configures memory headroom.
Step S45：DMA read operations and DMA write operation.
DMA drivings are developed by CVI, drives and develops also based on VISA.This driving exploitation passes through using PCI9054 as row
VISA drivings access hardware resource and realize DMAC transmission operations.The software and hardware environment built first, completes following operation.
Step S41：Loading configuration file.Loaded according to PCI9054 Register Allocation Tables, read PCI9054 registers and match somebody with somebody
The content in table is put, the register value letter in table is assigned to the variable of related definition.Wherein, BAR0 spaces are to PCI9054
Register manipulation, BAR3 spaces are to FPGA register manipulations.Configuration file can be .txt .ini and form document.Can
To be defined according to software service condition oneself.The reading manner of different files is different.Form document can be used directly
ExcelRpt_WorkBookOpen () excelRpt_WorkBookClose () the correlation such as excelRpt_ReadData ()
Function is to open, closing and read operation.
Step S42：Open hardware FPGA resource.Hardware resource how is opened, how to register interrupt resources, NI companies exist
There is detailed introduction in the Samples that CVI is carried.
C：Users Public Documents NationalInstruments NI-VISA Examples this mesh
Project file can be found under record.Mainly include the following steps that：
Step S421：The explorer for opening acquiescence uses viOpenDefaultRM (＆resMgr) function, by this
Function obtains the reply handle of resource management.
Step S422：Obtain resource descriptor and use viFindRsrc (resMgr, " PXI* INSTR ", 0,0,
Descriptor) function.The second parameter of function specifies the which type of resource descriptor to be obtained, we select here
The PXI buses selected, the resource with interrupt type.Parameter " descriptor " returns to resource descriptor.
Step S423：Open equipment and use viOpen (resMgr, descriptor, VI_NULL, VI_NULL, ＆
Session) function." session " parameter is that we carry out the resource handle of hardware operation.By the handle, indicating to grasp
The Bar spaces of work, you can complete the read-write operation to hardware register.
Step S43：Register the interrupt resources of the type.Specifically include following steps：
Step S431：Register interrupt resources：ViInstallHandler (vi, VI_EVENT_PXI_INTR, NT_H1040_
CallBackFunc, NULL)；Parameter NT_H1040_CallBackFunc indicates a call back function.
Step S432：PXI is registered with event viEnableEvent (vi, VI_EVENT_PXI_INTR, the VI_ interrupted
HNDLR, VI_NULL)；
Step S432：Interrupt register state is read, enables and interrupts
ViIn32 (vi, VI_PXI_BAR0_SPACE, INTCSR , ＆intcsr)；
Intcsr=0x68 | intcsr；
ViOut32 (vi, VI_PXI_BAR0_SPACE, INTCSR, intcsr)；// enable and interrupt
Step S44：DMA is initialized, configures memory headroom；Specifically include following steps：
Step S441：Obtain " PXI0：：The handle of MEMACC " introversions.
ViOpen (resMgr, " PXI0：：MEMACC ", VI_NULL, VI_NULL , ＆MemAllocSession)；Pass through ginseng
Number " MemAllocSession " obtains the handle of internal memory operation.
Step S442：The resource of storage allocation handle.
ViMemAlloc (MemAllocSession, sizeof (int) * DmaLength ,s ＆pDmaStruct->pBuf)；
The function second parameter specifies the memory size to be distributed, and passes through " pDmaStruct->PBuf " obtains the ground of this section distribution
The first address in location space.
Step S443：The physical start address of DMA transfer PCI is set.
ViOut32 (Session, VI_PXI_BAR0_SPACE, VISA_DMA_PCI_ADDRESS, pDmaStruct->
pBuf)。
Step S444：The address of DMA transfer Local Bus is set.
LocalAddr=0x20000；
Value=LocalAddr*4；// since pci bus is 32bit transmission, ensure the integral multiple for 4, otherwise easily
There is the situation of address exception.
ViOut32 (Session, VI_PXI_BAR3_SPACE, VISA_DMA_PCI_ADDRESS, value).
Step S445：DMA transfer FPGA is set to put data first address.
Value=0x20000；// this address can be with cooperation FPGA hardware definition；
ViOut32 (Session, VI_PXI_BAR3_SPACE, VISA_DMA_PCI_ADDRESS, value).
Step S446：DMA transfer bit wide and preparation are set.
Value=2+ (1<<6)；// setting bit wide is 32bit, and DMA prepares enabled viOut32 (Session, VI_PXI_
BAR0_SPACE, 0x80, Value).
Enter step S5：DMA read-write operations, the step S5 specifically include following steps：
Step SD45：DMA read operations and step SX45：DMA write operation.
As shown in figure 4, the step SX45 specifically includes following steps：
Step SX451：DMA directions are set to write：
Value=0；
ViOut32 (Session, VI_PXI_BAR0_SPACE, VISA_DMA_CH0_DESCRIPTOR_POINT,
Value)；
Step SX452：Reading DMA data：
Offset=pDmaStruct->pBuf；
ViMoveOut32 (Session, VI_PXI_ALLOC_SPACE, offset, Length, pValue)；Parameter two
" VI_PXI_ALLOC_SPACE " is indicated as being the parameter in PXI MEMACC spaces, mistake otherwise can be entered for, before parameter three is inserted
The address of application, the address offset address as DMA transfer；Parameter " Length " indicates the data length to be obtained；
" pValue " local cache, DMA data is ready for sending for storing.
Step SX452：DMA is set to prepare the length read：
ViOut32 (Session, VI_PXI_BAR0_SPACE, VISA_DMA_CH0_TRANSFER_COUNT, Value)；
ViOut32 (Session, VI_PXI_BAR3_SPACE, H1040_VISA_BRA3_DMA_LENGTH, Value)；
Step SX453：Enabled DMA transfer；
Value=1；
ViOut32 (Session, VI_PXI_BAR3_SPACE, VISA_DMA_CSR0, Value)；
Step SX454：Start DMA transfer：
Value=3；
ViOut32 (Session, VI_PXI_BAR3_SPACE, VISA_DMA_CSR0, Value)；
Step SX455：DMA is detected to complete；
ViIn32 (Session, VI_PXI_BAR3_SPACE, VISA_DMA_CSR0 , ＆Value)；
If((Value>>4)&0x1)
{
Complete DMA；
}
As shown in figure 5, the step SD45 bodies comprise the following steps：
Step SD451：DMA directions are set to read.
Value=1；
ViOut32 (Session, VI_PXI_BAR0_SPACEVISA_DMA_CH0_DESCRIPTOR_POINT,
Value)。
Step SD452：DMA is set to prepare the length read.
Memory headroom size of the length no more than opening space application.
ViOut32 (Session, VI_PXI_BAR0_SPACE, VISA_DMA_CH0_TRANSFER_COUNT,
Value)；// PCI address is set, indicate data byte number viOut32 (Session, the VI_PXI_BAR3_ to be transmitted
SPACE, H1040_VISA_BRA3_DMA_LENGTH, Value)；// local bus addresses are set, indicate the data to be transmitted
Byte number.This part is used to FPGA.
Step SD453：Enabled DMA transfer：
Value=1；
ViOut32 (Session, VI_PXI_BAR3_SPACE, VISA_DMA_CSR0, Value)；
Step SD454：Start DMA transfer：
Value=3；
ViOut32 (Session, VI_PXI_BAR3_SPACE, VISA_DMA_CSR0, Value)；
Step SD454：DMA is detected to complete：
ViIn32 (Session, VI_PXI_BAR3_SPACE, VISA_DMA_CSR0 , ＆Value)；
If((Value>>4)&0x1)
{
Complete DMA；The 4bit of //Value values puts 1 and indicates whether to be transmitted, and does not otherwise complete.
}
Step SD454：Reading DMA data：
Offset=pDmaStruct->pBuf；
ViMoveIn32 (Session, VI_PXI_ALLOC_SPACE, offset, Length, pValue)；Parameter two
" VI_PXI_ALLOC_SPACE " is indicated as being the parameter in PXI MEMACC spaces, mistake otherwise can be entered for, before parameter three is inserted
The address of application, the address offset address as DMA transfer；Parameter " Length " indicates the data length to be obtained；
" pValue " local cache, for storing the DMA data read.
Step S46：DMA performance tests.
The other parts of the present embodiment are same as the previously described embodiments, and so it will not be repeated.
The above, is only presently preferred embodiments of the present invention, not does limitation in any form to the present invention, it is every according to
Any simply modification, the equivalent variations made according to the technical spirit of the present invention to above example, each fall within the protection of the present invention
Within the scope of.
Claims (10)
1. the general DMA transfer method driven based on PXIe buses and VISA, it is characterised in that：The general DMA transfer method
Based on DMA transfer system realize, the DMA transfer system include be provided with PXIe buses and PXI e interface PXIe cabinets, with
The PCI9054 bridge pieces of PXI e interface connection, the FPGA boards that are connected with PCI9054 bridge pieces and it is connected with FPGA boards
RS422 transceiver modules.
2. the general DMA transfer method according to claim 1 driven based on PXIe buses and VISA, it is characterised in that：
Specifically include following steps：
Step S1：Software is installed；Specifically refer to that CVI2009 and NI MAX are installed on PXI cabinets, build software environment；
Step S2：Connect equipment；FPGA boards are connected with PXI e interface；
Step S3：Installation driving；Pass through NI MAX load drivers；
Step S4：Test DMA communications.
3. the general DMA transfer method according to claim 2 driven based on PXIe buses and VISA, it is characterised in that：
The step S3 specifically includes following steps：
Step S31：NI VISA Driver Wizard are opened, select equipment, into next step；
Step S32：Device parameter is filled in, indicates that the driving uses interruption；
Step S33：Configure Bar0 spaces, configuration status status register；It is 0x00000900 to set 0x68 addresses, in initialization
It is disconnected.
4. the general DMA transfer method driven based on PXIe buses and VISA according to Claims 2 or 3, its feature are existed
In：The step S4 specifically includes following steps：
Step S41：Loading configuration file；
Step S42：Open hardware FPGA resource；
Step S43：Register interrupt resources；
Step S44：DMA is initialized, configures memory headroom；
Step S45：DMA read operations and DMA write operation；
Step S46：DMA performance tests.
5. the general DMA transfer method according to claim 4 driven based on PXIe buses and VISA, it is characterised in that：
The step S41 specifically includes following steps：
Step S411：Load form configuration file；
Step S421：By CVI system functions, table content is read.
6. the general DMA transfer method according to claim 4 driven based on PXIe buses and VISA, it is characterised in that：
The step S42 specifically includes following steps：
Step S421：The explorer of acquiescence is opened, obtains the reply handle of resource management；
Step S422：Obtain resource descriptor and use function；
Step S423：Open equipment and use function；Find the resource handle for carrying out hardware operation；By the handle, indicating to grasp
The Bar spaces of work, complete the read-write operation to hardware register.
7. the general DMA transfer method according to claim 4 driven based on PXIe buses and VISA, it is characterised in that：
The step S43 specifically includes following steps：
Step S431：Register interrupt resources；
Step S432：PXI is registered with the event interrupted；
Step S433：Interrupt register state is read, enables and interrupts.
8. the general DMA transfer method according to claim 4 driven based on PXIe buses and VISA, it is characterised in that：
The step S44 specifically includes following steps：
Step S441：Obtain introversive handle；
Step S442：The resource of storage allocation handle；
Step S443：The physical start address of DMA transfer PCI is set；
Step S444：The address of DMA transfer Local Bus is set；
Step S445：DMA transfer FPGA is set to put data first address；
Step S446：DMA transfer bit wide and preparation are set.
9. the general DMA transfer method according to claim 4 driven based on PXIe buses and VISA, it is characterised in that：
DMA read operations in the step S45 specifically include following steps：
Step SD451：DMA directions are set to read；
Step SD452：DMA is set to prepare the length read；Memory headroom size of the length no more than opening space application；
Step SD453：DMA is set to enable and transmit；
Step SD454：Start DMA to read；
Step SD455：DMA is detected to complete；Read PXIe bus datas.
10. the general DMA transfer method according to claim 4 driven based on PXIe buses and VISA, it is characterised in that：
DMA write operation in the step S45 specifically includes following steps：
Step SX451：DMA directions are set to write；
Step SX452：Reading DMA data；
Step SX453：DMA is set to prepare the length read；
Step SX454：DMA is set to enable and transmit；
Step SX455：Start DMA to read；
Step SX456：DMA is detected to complete；Reading DMA data.
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| CN111045964A (en) * | 2019-12-06 | 2020-04-21 | 思尔芯(上海)信息科技有限公司 | PCIE interface-based high-speed transmission method, storage medium and terminal |
| CN114327664A (en) * | 2022-03-15 | 2022-04-12 | 武汉普赛斯电子技术有限公司 | Software management method for card-insertion type case equipment, computer equipment and storage medium |
| CN115827168A (en) * | 2023-02-01 | 2023-03-21 | 南京芯传汇电子科技有限公司 | Optimization method for virtual machine communication in binary simulation environment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111045964A (en) * | 2019-12-06 | 2020-04-21 | 思尔芯(上海)信息科技有限公司 | PCIE interface-based high-speed transmission method, storage medium and terminal |
| CN111045964B (en) * | 2019-12-06 | 2021-07-20 | 上海国微思尔芯技术股份有限公司 | PCIE interface-based high-speed transmission method, storage medium and terminal |
| CN114327664A (en) * | 2022-03-15 | 2022-04-12 | 武汉普赛斯电子技术有限公司 | Software management method for card-insertion type case equipment, computer equipment and storage medium |
| CN114327664B (en) * | 2022-03-15 | 2022-06-17 | 武汉普赛斯电子技术有限公司 | Software management method for card-insertion type case equipment, computer equipment and storage medium |
| CN115827168A (en) * | 2023-02-01 | 2023-03-21 | 南京芯传汇电子科技有限公司 | Optimization method for virtual machine communication in binary simulation environment |
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