CN107888336A - Spaceborne ADS B signals detection of preamble system and method - Google Patents

Spaceborne ADS B signals detection of preamble system and method Download PDF

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Publication number
CN107888336A
CN107888336A CN201711081745.5A CN201711081745A CN107888336A CN 107888336 A CN107888336 A CN 107888336A CN 201711081745 A CN201711081745 A CN 201711081745A CN 107888336 A CN107888336 A CN 107888336A
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signal
pulse
envelope
output
phase
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CN107888336B (en
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张程
吴小丹
胡浩
黄奕
双小川
刘伟亮
魏文超
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Shanghai Aerospace Measurement Control Communication Institute
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Shanghai Aerospace Measurement Control Communication Institute
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields

Abstract

The present invention proposes a kind of spaceborne ADS B signals detection of preamble system and method, and the system includes：Envelope extract block, to carry out envelope extraction to the baseband signal of the two-way orthogonal signalling received, obtain envelope signal；AGC modules, the output end of the envelope extract block is connected, to carry out automatic growth control to the envelope signal；Filtration module, the output end of the AGC modules is connected, to be filtered processing to the envelope signal after AGC resume modules；Digital phase-locked loop, the output end of the filtration module is connected, to realize tracking of the local clock to the signal after filtered resume module, carry-out bit lock-out pulse；Header framework detection module, to the station acquisition header data according to the bit synchronization pulse, frame synchronization is carried out with default header data form, framework is detected and passed through if frame synchronization can lock, and obtains header framework.The problem of overcoming traditional ADS B receiver sensitivities inadequate.

Description

Spaceborne ADS-B signal headers detecting system and method
Technical field
The present invention relates to digital processing field, more particularly to a kind of spaceborne ADS-B signal headers detecting system And method.
Background technology
Automatic dependent surveillance broadcast (abbreviation ADS-B) uses omni broadcast, plays its air position information, air speed Information, identity information, working condition and status information etc., there is aircraft automatically to be set to the aircraft, vehicle and ground receiver to walk Preparation send the signal of 1090MHz frequencies.ADS-B signal receivers air to air monitor except that can realize, outside air to surface monitoring, may be used also To realize other many functions, such as：The automatic identification mutual alignment of aerospace plane, keep safe distance；Grounded receiving station Commander can be monitored to the aircraft of Route reform.
The covering radius of spaceborne ADS-B receivers can reach 3000km, the covering compared to ground receiver 160km half It is a big advantage for footpath.When spaceborne ADS-B systems global coverage can from present 10% or so lifting to 100%.
Spaceborne ADS-B receivers are realized, then are primarily present following technological difficulties：
Airborne transmitter system, which is not made being correspondingly improved to adapt to onboard system, causes satellite reception power very It is small, therefore, it is desirable to detect and the place's of resolving information just need improve receiver sensitivity.For in theory, in spaceborne condition Under, receiver sensitivity has to reach the complete reception that -109dbm could realize signal in satellite antenna overlay area.At present In D0-260B in the sensitivity requirement of A class ADS-B receivers, highest also just only -84dbm (in the case of not interfering with The index that 90% signal receives could be realized), the spaceborne environmental requirement with reality has differed 25db.So existing ADS-B connects Receipts machine can not meet to require.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of spaceborne ADS-B signal headers detecting system and method, gram Take the problem of traditional ADS-B receiver sensitivities are inadequate.
To solve the above problems, the present invention proposes a kind of spaceborne ADS-B signal headers detecting system, including：
Envelope extract block, to carry out envelope extraction to the baseband signal of the two-way orthogonal signalling received, wrapped Network signal；
AGC modules, the output end of the envelope extract block is connected, to carry out automatic gain control to the envelope signal System；
Filtration module, the output end of the AGC modules is connected, to be carried out to the envelope signal after AGC resume modules Filtering process；
Digital phase-locked loop, the output end of the filtration module is connected, to realize local clock to filtered resume module The tracking of signal afterwards, carry-out bit lock-out pulse；
Header framework detection module, to the station acquisition header data according to the bit synchronization pulse, with default header Data format carries out frame synchronization, and framework is detected and passed through if frame synchronization can lock, and obtains header framework.
According to one embodiment of present invention, in addition to：
DF correction verification modules, to the collection number to the DF positions in the header framework passed through through the detection of header framework detection module Made decisions according to value, verify and pass through if the data format of the DF positions with acquiescence is equal；
Power consistency detection module, to through being 1 in the header framework that passes through of DF correction verification modules verification The power of position data carries out consistency detection, so that fluctuation is in certain threshold range.
According to one embodiment of present invention, the envelope module obtains the orthogonal two-way baseband signal I after ADC is sampled (k) with Q (k), modulus computing is carried out to I (k) and Q (k)：Obtain envelope signal S (k).
According to one embodiment of present invention, the AGC modules include：Divider, accumulator and IIR loop filters；
The automatic growth control coefficient that the divider feeds back according to the IIR loop filters, is realized to signal intensity Automatic growth control, and output-controlled envelope signal；
The accumulator receives the envelope signal, realizes the estimation to signal intensity, estimate is exported to the IIR Loop filter；
The IIR loop filters receive the estimate and noise filtering are carried out to it, output automatic growth control system Number.
According to one embodiment of present invention, the filtration module includes：
Autocorrelation filter, letter is obtained to carry out auto-correlation computation to the envelope signal S (k) after AGC resume modules Number S1(k), operational formula：
N is filter order；
Cross correlation filter, to the signal S exported to autocorrelation filter1(k) carry out computing cross-correlation and obtain signal S2 (k), operational formula：
S2(k)=(S1(k-1)coef(1)+S1(k-2)coef(2)+…+S1(k-n) coef (n)), coef (1), coef (1) ... coef (n) is default matching factor；
Narrow band filter, the signal to be exported to the cross correlation filter are filtered, and its passband is the signal Bandwidth.
According to one embodiment of present invention, the digital phase-locked loop includes：Integrator, quadrature integrator, first in the same direction Sampling retainer, the second sampling retainer, phase discriminator, controller；
The integrator in the same direction and quadrature integrator integrate to being filtered the envelope signal after handling respectively, respectively Output signal b and signal c；The time of integration of integrator and quadrature integrator in the same direction is all code-element period T and is controlled by position Lock-out pulse so that the integrating range of integrator in the same direction overlaps with the section of bit synchronization pulse, and the integrated area of quadrature integrator Between just across between the midpoint of two adjacent bit lock-out pulses；
The first sampling retainer and the second sampling retainer connect integrator and the quadrature integrator in the same direction respectively Output end, respectively to carry out sampling holding to the signal b and signal c, by duration extension a to code-element period Time T, obtain signal e and signal f；
The phase discriminator to detect the phase of the signal e and signal f, with determine the phase of bit synchronization pulse it is advanced or Hysteresis, the phase of lock-out pulse in place export a prepulsing k when advanced, output one is stagnant during the delayed phase of lock-out pulse in place Afterpulse j；
The controller moves backward to the identified result according to the phase discriminator, the phase of control bit lock-out pulse, control The past reach of the phase of bit synchronization pulse processed.
According to one embodiment of present invention, the phase discriminator includes：
Hopping edge detector, the output end of connection the first sampling retainer, to detect the saltus step of the signal e Edge, and a narrow pulse signal g is generated in each saltus step；
The output end of XOR gate, the connection first sampling retainer and the second sampling retainer, to the signal e XOR, output signal h are carried out with signal f；
First and door, receive the narrow pulse signal g and signal h negates signal and will both mutually and, output is stagnant Afterpulse j；
Second and door, receive the narrow pulse signal g and the signal h and will both mutually and, output prepulsing k.
According to one embodiment of present invention, in addition to crystal oscillator and converter；The crystal oscillator exports a clock signal；It is described Converter receives the clock signal, and its frequency reducing and generating after converting mutually staggered into a clock cycle and frequency is data frequency Preset multiple pulse train clk_d1 and pulse train clk_d2；
When the controller detects the prepulsing k or hysteresis pulse j, a high level signal is produced, is just caused An output of pulse signal in a pulse signal or pulse train clk_d2 in pulse train clk_d1.
According to one embodiment of present invention, in addition to frequency divider and pulse shaping device；The frequency divider connects the control The output end of device processed, the pulse shaping device connect the output end of the frequency divider；The pulse signal of controller output is divided Carry-out bit lock-out pulse after device and pulse shaping device.
According to one embodiment of present invention, in addition to digital filter, be connected to the phase discriminator and controller it Between, the digital filter includes：
Random-walk filtering device receives prepulsing and the hysteresis pulse of the phase discriminator output, is filtered and counts respectively Exported after number；
First divider, the count results and prepulsing of the random-walk filtering device filtering output are received, according to meter Number result is zeroed out to fragmentary prepulsing, exports the first reset signal；
Second divider, count results and the hysteresis pulse of the random-walk filtering device filtering output are received, according to meter Number result is zeroed out to fragmentary hysteresis pulse, exports the first reset signal；
3rd and door, input receives prepulsing and the first reset signal, by both mutually with to be exported in non-clearing Prepulsing；
4th and door, input receives hysteresis pulse and the second reset signal, by both mutually with to be exported in non-clearing Lag pulse.
The present invention also provides a kind of spaceborne ADS-B signal headers detection method, comprises the following steps：
S1：The baseband signal of two-way orthogonal signalling to receiving carries out envelope extraction, obtains envelope signal；
S2：Automatic growth control is carried out to the envelope signal；
S3：Processing is filtered to the envelope signal after automatic growth control is handled；
S4：Realize tracking of the local clock to the signal after filtered resume module, the bit synchronization pulse after output tracking；
S5：According to the station acquisition data of the bit synchronization pulse, frame synchronization is carried out with default header data form, if frame It can synchronously lock, framework detection passes through, and obtains header framework.
S6：The acquired data values of DF positions in the header framework that passes through after testing are made decisions, if the DF positions with acquiescence Data format it is equal, verification pass through；
S7：Consistency detection is carried out to the power for 1 position data through verifying in the header framework passed through, so that fluctuation In certain threshold range.
After adopting the above technical scheme, the present invention has the advantages that compared with prior art：
1. the amplitude control function with AGC, adapts to higher dynamic requirements；
2. using the clock tracing restoration methods of integration type phaselocked loop, the method for not carrying out clock recovery than tradition has about 3db gain, so as to greatly improve the detection range of receiver；
3. being suppressed using digital filter to clock jitter, in the case of low signal-to-noise ratio, have jamproof Function.
Brief description of the drawings
Fig. 1 is the structured flowchart of the spaceborne ADS-B signal headers detecting system of one embodiment of the invention；
Fig. 2 is the structured flowchart of the AGC modules of one embodiment of the invention；
Fig. 3 is the structured flowchart of the digital phase-locked loop of one embodiment of the invention；
Fig. 4 is the structured flowchart of the digital filter of one embodiment of the invention.
Fig. 5 is the schematic flow sheet of the spaceborne ADS-B signal headers detection method of one embodiment of the invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention Embodiment be described in detail.
Many details are elaborated in the following description in order to fully understand the present invention.But the present invention can be with Much it is different from other manner described here to implement, those skilled in the art can be in the situation without prejudice to intension of the present invention Under do similar popularization, therefore the present invention is not limited to the specific embodiments disclosed below.
Referring to Fig. 1, in one embodiment, spaceborne ADS-B signal headers detecting system includes：Envelope extract block N1, AGC module N2, filtration module, digital phase-locked loop N6 and header framework detection module N8.
Spaceborne ADS-B signal headers detecting system can the digital circuit based on FPGA, the signal of processing can be The digital baseband signal sampled by ADC (A-D converter), optionally, sample rate is 32MHz, and baseband signal bandwidth is 1.5MHz。
Envelope extract block N1 is wrapped to carry out envelope extraction to the baseband signal of the two-way orthogonal signalling received Network signal.
Preferably, modulus computing is done to I/Q two-way orthogonal signalling, so as to extract the envelope S (k) of baseband signal.Specifically Say, envelope extract block N1 obtains orthogonal two-way baseband signal I (k) after ADC is sampled and Q (k), and I (k) and Q (k) are entered Row modulus computing：Obtain envelope signal S (k).Thus envelope extract block N1 can also It is considered as modulo block.
For opening radical sign computing, the embodiment of the present invention uses a kind of method of interative computation： Make x1Value be more thanThen only need a small number of iteration several times, it is possible to which approximation obtainsNumerical value.
AGC (automatic growth control) module N2 connection envelope extract blocks N1 output end, envelope signal is received, to envelope Signal carries out automatic growth control.
Referring to Fig. 2, in one embodiment, AGC modules N2 includes：Divider, accumulator and IIR loop filters.Institute The automatic growth control coefficient that divider feeds back according to the IIR loop filters is stated, realizes the automatic gain to signal intensity Control, and output-controlled envelope signal；The accumulator receives the envelope signal, realizes the estimation to signal intensity, will estimate Evaluation is exported to the IIR loop filters；The IIR loop filters receive the estimate and carry out noise filter to it Remove, export automatic growth control coefficient.
Envelope signal controls its signal amplitude size to meet dynamic requirements by AGC modules N2.Envelope signal can pass through One divider, realizes the automatic growth control to signal intensity.The automatic growth control coefficient of divider is anti-by one It is fed back to road acquisition.The envelope signal of input obtains the estimation to signal intensity by an accumulator, then this estimate By a second order IIR loop filter, noise is filtered out, the output of loop filter is automatic growth control coefficient, afterwards The envelope signal of the input of the automatic growth control coefficient feedback of output to divider and input is subjected to division arithmetic together, Envelope signal S (k) after output-controlled.
Filtration module connection AGC modules N2 output end, to be filtered to the envelope signal after AGC modules N2 processing Ripple processing.
With continued reference to Fig. 1, filtration module includes the autocorrelation filter N3 being sequentially connected, cross correlation filter N4 and arrowband Wave filter N5.Can certainly be other wave filters.Autocorrelation filter N3 connection AGC modules N2 output end, arrowband filter Ripple device N5 connection digital phase-locked loops N6 input.
Autocorrelation filter N3 obtains to carry out auto-correlation computation to the envelope signal S (k) after AGC modules N2 processing Signal S1(k), operational formula：
N is filter order.
Cross correlation filter N4 is to the signal S that is exported to autocorrelation filter N31(k) carry out computing cross-correlation and obtain letter Number S2(k), operational formula：
S2(k)=(S1(k-1)coef(1)+S1(k-2)coef(2)+…+S1(k-n) coef (n)), coef (1), coef (1) ... coef (n) is default matching factor, can be stored in advance in FPGA RAM, matches with reception signal and (counts The concept of classical matched filter in word signal transacting), usual n can value be 5.
Narrow band filter N5 is filtered to the signal exported to cross correlation filter N4, and its passband is the band of the signal It is wide.Preferably, narrow band filter N5 is that high-order arrowband FIR (Finite Impulse Response, there is limit for length's unit impulse sound Answer wave filter) wave filter, by cross correlation process export signal noise is filtered out by a high-order narrow band FIR filter, this The passband of individual FIR filter is the bandwidth of information signal.
The output end of digital phase-locked loop N6 connection filtration modules, after realizing local clock to filtered resume module The tracking of signal, carry-out bit lock-out pulse.Tracking of the local clock to signal clock is carried out using digital phase-locked loop N6.
Signal after FIR filter is the information signal for more really filtering out a part of noise, but by With signal clock it is noncoherent in local clock, and its phase (i.e. the source location set of signal) must not also be known.So In the present invention, a kind of integral form numeral institute's phaselocked loop is employed to recover this clock.
Referring to Fig. 3, digital phase-locked loop can include：Integrator, quadrature integrator, the first sampling retainer, second in the same direction Sampling retainer, phase discriminator, controller.
Integrator and quadrature integrator in the same direction integrate to being filtered the envelope signal after handling respectively, export respectively Signal b and signal c；The time of integration of integrator and quadrature integrator in the same direction is all code-element period T and is controlled by bit synchronization Pulse so that the integrating range of integrator in the same direction overlaps with the section of bit synchronization pulse, and the integrating range of quadrature integrator is just Well across between the midpoint of two adjacent bit lock-out pulses.Bit synchronization pulse can be directly inputted in integrator in the same direction, and is passed through Delayer delay T/2 is input in quadrature integrator again.
The first sampling retainer and the second sampling retainer connect integrator and the quadrature integrator in the same direction respectively Output end, respectively to carry out sampling holding to the signal b and signal c, by duration extension a to code-element period Time T, obtain signal e and signal f.
The phase discriminator to detect the phase of the signal e and signal f, with determine the phase of bit synchronization pulse it is advanced or Hysteresis, the phase of lock-out pulse in place export a prepulsing k when advanced, output one is stagnant during the delayed phase of lock-out pulse in place Afterpulse j.
The controller moves backward to the identified result according to the phase discriminator, the phase of control bit lock-out pulse, control The past reach of the phase of bit synchronization pulse processed.
Further, phase discriminator includes：Hopping edge detector, XOR gate, first with door and second and door.Detect hopping edge The output end of device connection the first sampling retainer, to detect the hopping edge of the signal e, and is generated in each saltus step One narrow pulse signal g.The output end of the XOR gate connection first sampling retainer and the second sampling retainer, to described Signal e and signal f carries out XOR, output signal h.First and door, receive negating for the narrow pulse signal g and signal h Signal simultaneously will both phases and lag output pulse j.Second and door, receive the narrow pulse signal g and the signal h and by two Person's phase and output prepulsing k.
Specifically, signal first with quadrature integrator by being integrated in the same direction, and their time of integration is all code First cycle T, the integrating range of integrator in the same direction overlaps with the section of bit synchronization pulse, and the integrating range of quadrature integrator is just Overstate between the emphasis of two adjacent sync pulses, their integrating range just differs T/2, if the phase of bit synchronization pulse surpasses Before, then the output voltage polarity of two integrators is identical, if conversely, the delayed phase of bit synchronization pulse, two integrators it is defeated It is opposite to go out polarity of voltage.Utilize this rule, it is possible to judge the advanced of bit synchronization pulse or hysteresis.
In figure 3, the output of integrator and quadrature integrator in the same direction is respectively signal b and signal c.Then, first is passed through Retainer and the second sampling retainer sample by signal b and signal c duration extension to a code-element period time T, from And obtain signal e and signal f.Signal e is (defeated at each saltus step of signal by hopping edge detector, specifically differential rectification Go out a pulse signal) and monostable circuit (when detecting high level pulse signal, the continuous height electricity for exporting certain time length Flat pulse signal) after, zero crossing is detected, and a narrow pulse signal g is formed, this narrow pulse signal g causes first and door A1 In only data variation be possible to open with door B1 with second, synchronous signal e and signal f moulds 2 carry out different by XOR gate Or, obtain signal h.There is such relation between signal h and g：When bit synchronization pulse advance, signal g burst pulse falls within letter In the range of number h high level, the polarity that such case corresponds to the output of two integrators is identical, signal h and signal g phases with, just by Second exports a prepulsing k with door B1, the phase of bit synchronization pulse is moved backward.It is similar, when bit synchronization pulse is stagnant When afterwards, signal g burst pulse is fallen within the range of signal g low level, and such case corresponds to the polarity phase of two integrators output Instead, signal h is taken into ' non-' afterwards with signal g phases with just exporting a hysteresis pulse j by first and door A1 so that bit synchronization phase Toward reach.So repeatedly adjustment phase place, is achieved that bit synchronization.
Preferably, spaceborne ADS-B signal headers detecting system also includes crystal oscillator and converter.Crystal oscillator exports clock letter Number；The converter receives the clock signal, and its frequency reducing and generating after converting mutually staggered into a clock cycle and frequency is The pulse train clk_d1 and pulse train clk_d2 of the preset multiple of data frequency.
When the controller detects the prepulsing k or hysteresis pulse j, a high level signal is produced, is just caused An output of pulse signal in a pulse signal or pulse train clk_d2 in pulse train clk_d1.
Specifically, in figure 3, the output frequency of local crystal oscillator is 32 times (32MHz) of data rate, it is transformed after into For a clock cycle of mutually staggering, two the pulse trains clk_d1 and clk_d2 that frequency is 8 times of data rate are obtained.Control S1 and S2 in device are monostable trigger, when high level signal is detected, produce the high level letter in 4 crystal oscillator clock cycles Number, it can just open the pulse letter either closed in clk_d1 sequences pulse signal or clk_d2 sequences Number, it is passed to.
In one embodiment, spaceborne ADS-B signal headers detecting system also includes frequency divider and pulse shaping device.It is described Frequency divider connects the output end of the controller, and the pulse shaping device connects the output end of the frequency divider；Controller exports The divided device of pulse signal and pulse shaping device after carry-out bit lock-out pulse.Frequency divider is divided the clock of previous stage Frequently, then the clock of frequency dividing is molded over impulse form by pulse shaping device.
In one embodiment, digital filtering is also included referring to Fig. 1 and Fig. 4, spaceborne ADS-B signal headers detecting system Device N7, digital filter N7 are connected between the phase discriminator and controller.The digital filter N7 includes：
Random-walk filtering device receives prepulsing and the hysteresis pulse of the phase discriminator output, is filtered and counts respectively Exported after number；
First divider C1, the count results and prepulsing of the random-walk filtering device filtering output are received, according to Count results are zeroed out to fragmentary prepulsing, export the first reset signal；
Second divider C2, count results and the hysteresis pulse of the random-walk filtering device filtering output are received, according to Count results are zeroed out to fragmentary hysteresis pulse, export the first reset signal；
3rd receives prepulsing and the first reset signal with door D1, input, will both mutually with defeated in non-clearing Go out prepulsing；
4th receives hysteresis pulse and the second reset signal with door D2, input, will both mutually with defeated in non-clearing Go out to lag pulse.
In simple terms, first, the pulse advanced to the time in S3 of a random-walk filtering device and time are passed through The pulse of upper hysteresis is filtered, advanced or stagnant to what is sporadicly occurred at random then using two and door and two dividers Afterpulse is filtered out.Above-mentioned random-walk filtering device can be made up of a forward-backward counter and OR gate.
Specifically, digital filter N7 enters line number to advanced caused by digital institute phaselocked loop N6 or hysteresis pulse Word filters, and can increase its jamproof ability.It implements block diagram as shown in figure 4, being wrapped in figure in random-walk filtering device Two N counter is contained, when prepulsing or hysteresis step-by-step counting completely N, advanced or hysteresis arteries and veins could be exported Punching, is otherwise exactly fragmentary pulse, for anti-interference, fragmentary advanced or hysteresis the pulse when the output of phase discriminator When, these fragmentary pulses can cause the first divider C1 or the second divider C2 to reset, so as to anti-interference well Performance.That is, when continuous advanced or hysteresis pulse is detected just, the adjustment pulse of wave filter input is direct Exported by two and door D1 and D2, whole wave filter serves straight-through function, whenever detects what is sporadicly occurred at random During advanced or hysteresis pulse, because the first divider C1 or the second divider C2 clearing act on so that the 3rd and door D1 It is closed with the 4th and door D2, because realizing the filtering function to random pulses.
Header framework detection module N8 is to the station acquisition header data according to the bit synchronization pulse, i.e. FPGA used times The data of clock collection, frame synchronization is carried out with default header data form, framework is detected and passed through if frame synchronization can lock, and is obtained Header framework.The data of collection can be stored in RAM, and frame synchronization is carried out with the header data form in agreement.
In one embodiment, also include referring to Fig. 1, spaceborne ADS-B signal headers detecting system：DF correction verification modules N9 and Power consistency detection module N10.
DF correction verification modules N9 is to adopting to the DF positions in the header framework passed through through header framework detection module N8 detections Collection data value makes decisions, and verifies and passes through if the data format of the DF positions with acquiescence is equal.
The data format of the DF positions of acquiescence is (10001), so the collection of the DF in the frame structure passed through to detection Data value makes decisions, i.e., whether is equal to (10001).Position is fixed to DF in the protocol, if detecting 10001 signals, Then DF verifications pass through, conversely, verification does not pass through.
Power consistency detection module N10 to being in the header framework passed through through DF correction verification modules N9 verifications The power of 1 position data carries out consistency detection, so that fluctuation is in certain threshold range.Power consistency detection is i.e. to header The power for the data that bit in framework is 1 carries out consistency detection, it is desirable to which the power swing of these data is in certain thresholding model Within enclosing.In this example, can set, the fluctuation range of the power of these data is within positive and negative 3dbm.In Fig. 1, power The signal of consistency detection module N10 outputs is the signal after the ADS-B signal samplings received, and bit synchronization clock is with number According to clock, header flag signal is the pulse signal for indicating message position.
Referring to Fig. 5, the present invention also provides a kind of spaceborne ADS-B signal headers detection method, comprised the following steps：
S1：The baseband signal of two-way orthogonal signalling to receiving carries out envelope extraction, obtains envelope signal；
S2：Automatic growth control is carried out to the envelope signal；
S3：Processing is filtered to the envelope signal after automatic growth control is handled；
S4：Realize tracking of the local clock to the signal after filtered resume module, the bit synchronization pulse after output tracking；
S5：According to the station acquisition data of the bit synchronization pulse, frame synchronization is carried out with default header data form, if frame It can synchronously lock, framework detection passes through, and obtains header framework.
S6：The acquired data values of DF positions in the header framework that passes through after testing are made decisions, if the DF positions with acquiescence Data format it is equal, verification pass through；
S7：Consistency detection is carried out to the power for 1 position data through verifying in the header framework passed through, so that fluctuation In certain threshold range.
Particular content on the spaceborne ADS-B signal headers detection method of the present invention may refer in previous embodiment Embodiment content in spaceborne ADS-B signal headers detecting system, will not be repeated here.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting claim, any this area Technical staff without departing from the spirit and scope of the present invention, can make possible variation and modification, therefore the present invention Protection domain should be defined by the scope that the claims in the present invention are defined.

Claims (11)

  1. A kind of 1. spaceborne ADS-B signal headers detecting system, it is characterised in that including：
    Envelope extract block, to carry out envelope extraction to the baseband signal of the two-way orthogonal signalling received, obtain envelope letter Number；
    AGC modules, the output end of the envelope extract block is connected, to carry out automatic growth control to the envelope signal；
    Filtration module, the output end of the AGC modules is connected, to be filtered to the envelope signal after AGC resume modules Processing；
    Digital phase-locked loop, the output end of the filtration module is connected, after realizing local clock to filtered resume module The tracking of signal, carry-out bit lock-out pulse；
    Header framework detection module, to the station acquisition header data according to the bit synchronization pulse, with default header data Form carries out frame synchronization, and framework is detected and passed through if frame synchronization can lock, and obtains header framework.
  2. 2. spaceborne ADS-B signal headers detecting system as claimed in claim 1, it is characterised in that also include：
    DF correction verification modules, to the acquired data values to the DF positions in the header framework passed through through the detection of header framework detection module Make decisions, verify and pass through if the data format of the DF positions with acquiescence is equal；
    Power consistency detection module, to through the digit in the header framework that passes through of DF correction verification modules verification for 1 According to power carry out consistency detection so that fluctuation in certain threshold range.
  3. 3. spaceborne ADS-B signal headers detecting system as claimed in claim 1, it is characterised in that the envelope module is obtained and adopted through ADC Orthogonal two-way baseband signal I (k) and Q (k) after sample, modulus computing is carried out to I (k) and Q (k)： Obtain envelope signal S (k).
  4. 4. spaceborne ADS-B signal headers detecting system as claimed in claim 1, it is characterised in that the AGC modules include： Divider, accumulator and IIR loop filters；
    Automatic growth control coefficient that the divider feeds back according to the IIR loop filters, realize to signal intensity from Dynamic gain control, and output-controlled envelope signal；
    The accumulator receives the envelope signal, realizes the estimation to signal intensity, estimate is exported to the IIR loops Wave filter；
    The IIR loop filters receive the estimate and noise filtering are carried out to it, export automatic growth control coefficient.
  5. 5. spaceborne ADS-B signal headers detecting system as claimed in claim 1, it is characterised in that the filtration module includes：
    Autocorrelation filter, signal S is obtained to carry out auto-correlation computation to the envelope signal S (k) after AGC resume modules1 (k), operational formula：
    K=0-n-1, n are filter order；
    Cross correlation filter, to the signal S exported to autocorrelation filter1(k) carry out computing cross-correlation and obtain signal S2(k), Operational formula：
    S2(k)=(S1(k-1)coef(1)+S1(k-2)coef(2)+…+S1(k-n) coef (n)),
    Coef (1), coef (1) ... coef (n) is default matching factor；
    Narrow band filter, the signal to be exported to the cross correlation filter are filtered, and its passband is the bandwidth of the signal.
  6. 6. spaceborne ADS-B signal headers detecting system as claimed in claim 1, it is characterised in that the digital phase-locked loop bag Include：Integrator, quadrature integrator, the first sampling retainer, the second sampling retainer, phase discriminator, controller in the same direction；
    The integrator in the same direction and quadrature integrator integrate to being filtered the envelope signal after handling respectively, export respectively Signal b and signal c；The time of integration of integrator and quadrature integrator in the same direction is all code-element period T and is controlled by bit synchronization Pulse so that the integrating range of integrator in the same direction overlaps with the section of bit synchronization pulse, and the integrating range of quadrature integrator is just Well across between the midpoint of two adjacent bit lock-out pulses；
    The first sampling retainer and the second sampling retainer connect the defeated of the integrator in the same direction and quadrature integrator respectively Go out end, respectively to carry out sampling holding to the signal b and signal c, by duration extension to a code-element period time T, obtain signal e and signal f；
    The phase discriminator is to detect the phase of the signal e and signal f, to determine that the phase of bit synchronization pulse is advanced or stagnant Afterwards, a prepulsing k is exported when the phase of lock-out pulse in place is advanced, the hysteresis of output one during the delayed phase of lock-out pulse in place Pulse j；
    The controller moves backward to the identified result according to the phase discriminator, the phase of control bit lock-out pulse, control bit The past reach of the phase of lock-out pulse.
  7. 7. spaceborne ADS-B signal headers detecting system as claimed in claim 6, it is characterised in that the phase discriminator includes：
    Hopping edge detector, the output end of connection the first sampling retainer, to detect the hopping edge of the signal e, and A narrow pulse signal g is generated in each saltus step；
    The output end of XOR gate, the connection first sampling retainer and the second sampling retainer, to the signal e and letter Number f carries out XOR, output signal h；
    First and door, receive the narrow pulse signal g and signal h negates signal and will both mutually and lag output arteries and veins Rush j；
    Second and door, receive the narrow pulse signal g and the signal h and will both mutually and, output prepulsing k.
  8. 8. spaceborne ADS-B signal headers detecting system as claimed in claim 6, it is characterised in that also including crystal oscillator and conversion Device；The crystal oscillator exports a clock signal；The converter receives the clock signal, is generated by its frequency reducing and after converting mutual A clock cycle and the frequency of staggering for the preset multiple of data frequency pulse train clk_d1 and pulse train clk_d2；
    When the controller detects the prepulsing k or hysteresis pulse j, a high level signal is produced, just causes pulse An output of pulse signal in a pulse signal or pulse train clk_d2 in sequence clk_d1.
  9. 9. spaceborne ADS-B signal headers detecting system as claimed in claim 8, it is characterised in that also including frequency divider and arteries and veins Punch former；The frequency divider connects the output end of the controller, and the pulse shaping device connects the output of the frequency divider End；Carry-out bit lock-out pulse after the divided device of pulse signal and pulse shaping device of controller output.
  10. 10. spaceborne ADS-B signal headers detecting system as claimed in claim 6, it is characterised in that also including digital filtering Device, it is connected between the phase discriminator and controller, the digital filter includes：
    Random-walk filtering device receives prepulsing and the hysteresis pulse of the phase discriminator output, after being filtered and count respectively Output；
    First divider, the count results and prepulsing of the random-walk filtering device filtering output are received, are tied according to counting Fruit is zeroed out to fragmentary prepulsing, exports the first reset signal；
    Second divider, count results and the hysteresis pulse of the random-walk filtering device filtering output are received, is tied according to counting Fruit is zeroed out to fragmentary hysteresis pulse, exports the first reset signal；
    3rd and door, input receives prepulsing and the first reset signal, will both mutually with it is advanced to be exported in non-clearing Pulse；
    4th and door, input receives hysteresis pulse and the second reset signal, will both mutually with the lag output in non-clearing Pulse.
  11. 11. a kind of spaceborne ADS-B signal headers detection method, it is characterised in that comprise the following steps：
    S1：The baseband signal of two-way orthogonal signalling to receiving carries out envelope extraction, obtains envelope signal；
    S2：Automatic growth control is carried out to the envelope signal；
    S3：Processing is filtered to the envelope signal after automatic growth control is handled；
    S4：Realize tracking of the local clock to the signal after filtered resume module, the bit synchronization pulse after output tracking；
    S5：According to the station acquisition data of the bit synchronization pulse, frame synchronization is carried out with default header data form, if frame synchronization It can lock, framework detection passes through, and obtains header framework；
    S6：The acquired data values of DF positions in the header framework that passes through after testing are made decisions, if the number with the DF positions of acquiescence Equal according to form, verification passes through；
    S7：Consistency detection is carried out to the power for 1 position data through verifying in the header framework passed through, so that fluctuation is one Determine in threshold range.
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