CN107885509A - A kind of neutral net accelerator chip framework based on safety - Google Patents
A kind of neutral net accelerator chip framework based on safety Download PDFInfo
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- CN107885509A CN107885509A CN201711013715.0A CN201711013715A CN107885509A CN 107885509 A CN107885509 A CN 107885509A CN 201711013715 A CN201711013715 A CN 201711013715A CN 107885509 A CN107885509 A CN 107885509A
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- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
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Abstract
The present invention relates to a kind of neutral net accelerator chip framework based on safety.The present invention can programming module, content decryption module, the outer safety zone management module of piece including neutral net accelerating module, disposably.The order that neutral net accelerating module is used for neutral net carries out hardware-accelerated.Disposably can address administration of the programming module for safety zone division outside the key management to content decryption module and piece.Content decryption module is used to operation be decrypted to the neutral net order of encryption and parameter.The outer safety zone management module of piece be used for according to disposably can hardwired outer safety zone of programming module to modules access chip external memory when authority be controlled.Described neutral net accelerating module includes safety management module and programmable arithmetic element.Using technical scheme proposed by the present invention, even if hacker knows that entire content protects flow, neural network model can not be also exported.
Description
Technical field
The invention belongs to nerual network technique field, and in particular to a kind of neutral net accelerator chip frame based on safety
Structure.
Background technology
In the big data epoch, it is extensive better than the method for other machines study that neutral net has been proved to its performance
Using more and more outstanding machine learning algorithms are developed, and it is eventually deployed in hardware device.
Neutral net is deployed with two kinds of solutions at present：
1. being disposed beyond the clouds, terminal device is only responsible for the collection of data and the output of result.
2. directly disposing whole neutral net on Product Terminal, this is the consideration for real-time, also for without net
The consideration applied in the case of network.
For the 2nd kind of dispositions method, die terminals are proposed with the requirement of high security, high-performance, high flexibility：
Requirement for security, as fruit chip is not protected to the structure and parameter of neutral net, then be easy to by
Hack whole network.And in the application scheme of neutral net is related to, the part of its core is exactly neutral net, if should
The structure and parameter of network is obtained by a hacker to be arrived, and the core for substantially corresponding to product is cracked.
Requirement for performance, due to dispose whole neutral net, this just also has certain to the process performance of chip
It is required that.We have found that some operation (we for being not suitable for universal operating unit occur in a complete neutral net scheme
Define multiply-add in neutral net, convolution, Chi Hua, activate as general-purpose operation), such as transposition behaviour is carried out to a multi-dimensional matrix
Make, some embedded traditional algorithms etc. in neutral net.Add if whole neutral net is split into suitable neutral net by we
Fast device and unsuitable neutral net accelerator, it is very scattered that this can cause a neutral net to be split, add accelerator and
Scheduling times between CPU.And because CPU can also be operated in chip running to other modules, this just aggravates
CPU postpones to the dispatching response of neutral net accelerator, reduces the efficiency of neutral net operation.
Requirement for flexibility, it is now arranged in the rapid increase phase of neural network algorithm research, the renewal speed of algorithm
In units of the moon, and the chip development cycle is in units of year.In order to which the chip for ensureing to develop now can tackle the change in future,
Consider to be put into general arithmetic element in neutral net to adapt to the uncertainty in future so being also required to chip.
The content of the invention
The purpose of the present invention is aiming at the requirement for neutral net speed-up chip at present, there is provided a kind of based on safety
Neutral net accelerator chip framework, the framework also take into account neutral net accelerator to overall performance and versatility simultaneously
It is required that.
To achieve these goals, the present invention provides following solution：
Including neutral net accelerating module, disposably can programming module, content decryption module, management mould in safety zone outside piece
Block.Wherein：
Described neutral net accelerating module, carried out for the order to neutral net hardware-accelerated.
It is described it is disposable can programming module, divided for safety zone outside the key management to content decryption module and piece
Address administration；Its content can only be written over once in whole chip life cycle, and the content write cannot be non-
Correlation module is read.
Described content decryption module, for operation to be decrypted to the neutral net order of encryption and parameter, when pair plus
When close data are decrypted, its can only call disposably can the key of programming module be decrypted, and it can only be outside piece
The non-security district of storage medium is the data deciphering of encryption to the safety zone of piece outer storage medium, it is impossible to piece outer storage medium
Non-security district carry out write operation, read operation can not be carried out to the place of safety of piece outer storage medium.
The outer safety zone management module of described piece, disposably can hardwired outer place of safety of programming module for basis
Authority when domain accesses chip external memory to modules is controlled；It is according to the flag bit of privately owned definition to each in chip
Module carries out the division of safe class；Allow part of module safety zone outside piece is written and read, it is allowed to part of module to piece outside
Row write is entered in the safety zone of storage medium, does not allow other modules to be written and read safety zone outside piece.
Described neutral net accelerating module includes safety management module and programmable arithmetic element.
The safety management module, for the order to neutral net, whether the safety zone from chip external memory is carried out
Detection, and to may be programmed arithmetic element and universal operating unit to outside piece can the read-write process of storage medium be monitored；To god
Whether the order through network is judged from chip external memory safety zone, if order comes from the place of safety of chip external memory
Involved all safety zones that chip external memory can not be operated to chip external memory read-write in domain, then this order.
The programmable arithmetic element, the neutral net operation for that can not be realized to universal operating unit accelerate；
For general processor, digital signal processor or field programmable logic device.
Processing method based on framework of the present invention is specifically：
1. the nerve net that solution development business can identify the offline neural network model developed with Parameter Switch into chip
Network order；
Enciphering and deciphering algorithm is to its god used by 2. solution development business uses the unique key and chip known to them offline
It is encrypted through networking command；
3. after the completion of application scheme exploitation, to disposably can burned unique key in programming module, and specify piece external memory
Place of safety size in reservoir；
4. after application scheme work, if the neutral net order of encryption, CPU calls content decryption module encryption
Neutral net order is decrypted to the place of safety in piece outer storage medium；If non-encrypted neutral net order, CPU are then direct
The neutral net order is copied to the non-security district of piece outer storage medium；
5. when neutral net order is after the completion of the placement of piece outer storage medium, CPU calls neutral net accelerating module to read
Neutral net order in piece outer storage medium, and control of authority is carried out according to the source of neutral net order；I.e. in piece external memory
Neutral net order outside storage media safety zone is unable to control neural network accelerator and piece outer storage medium safety zone is entered
Row read-write operation；
6. during whole chip is run, all moulds in piece outer storage medium safety zone management module meeting detection chip
Access of the block to piece outer storage medium, if discovery content decryption module is read to safety zone or other modules pair
Safety zone is written and read operation, then performs the operation of reset chip；Other modules of neutral net accelerator are removed i.e. in chip
The safety zone access rights of chip external memory are responsible for by safety zone management module outside piece.
The present invention proposes a kind of neutral net accelerator chip framework based on content safety so that scheme business is deployed in
Neutral net product in hardware, even if hacker knows that entire content protects flow, it can not also export neural network model.Simultaneously
The optimization in performance and versatility has been done to present proprietary neutral net accelerator.In the present invention, programmable arithmetic element is
The order that universal operating unit can not be handled can be handled, this will cause a neutral net not to be split into some,
And can be run completely in neutral net accelerating module, so as to greatly improve the runnability of whole chip.In a typical case
Neutral net voice application in, neural network model needs to ensure real-time in 10ms ranks end of run；And CPU
In general operating system is linux, then the consumption dispatched every time can be in ms ranks.If a neutral net has split into 5
Part, do not consider that neural network accelerating module handles the time loss of the network, only consumed just in the scheduling of processing present networks
In more than 5ms.Programmable arithmetic element naturally solves the demand of flexibility.
Brief description of the drawings
Fig. 1 is the Organization Chart of chip of the present invention；
Fig. 2 is a kind of structure chart of neutral net accelerating module in the present invention.
Specific implementation method
For objects and advantages of the present invention are more clearly understood, the specific implementation method of the present invention will be done further in detail
Describe in detail bright.It may be noted that present implementation is used only for explaining the present invention, the implement scene of the present invention is not limited.
As shown in figure 1, a kind of neutral net accelerator chip framework based on safety, including neutral net accelerating module,
Disposably can programming module, content decryption module, the outer safety zone management module of piece.
One more complete neutral net speeding scheme contains and stores Jie outside neutral net speed-up chip 100 and a piece
Matter 200, wherein neutral net speed-up chip 100 contains neutral net accelerating module 10, disposably can programming module 20, content
The outer safety zone management module 40 of deciphering module 30, piece, CPU (central processing unit) 50, other modules 60.
Neural accelerating module 10, for carrying out acceleration computing to neutral net.It reads god from piece outer storage medium 200
Order through network, and the requirement in order, the general-purpose operation specified from specified location reading data and weight, such as
Multiplication, addition, activation, pond etc.；The non-universal operation that can also be specified.Neutral net accelerating module 10 in the process
Also receive come from disposably can be in the piece outer storage medium 200 that transmits of programming module 20 safety zone scope, so as to
Neutral net accelerating module 10 carries out control of authority to different neutral net orders.
As shown in Fig. 2 neutral net accelerating module 10 includes command analysis device 11, safety management module 12, programmable fortune
Calculate unit 13, universal operating unit 14, piece internal memory storage media 15.
Command analysis device 11, the maintenance and the interaction with CPU50 of responsible nerve networking command queue.Because except computing is ordered
Order, there is the unrelated operation of some other computings in neutral net order, such as after all orders of a neutral net terminate
CPU50 is notified, informs that it can take the result after Processing with Neural Network to carry out subsequent operation.
Safety management module 12, the order to arithmetic element processing carry out control of authority.Come from piece outer storage medium
Order outside safety zone can not access the content in piece outer storage medium safety zone；Order in safety zone outside piece
The content of piece outer storage medium arbitrary region can be accessed.
Programmable arithmetic element 13, can be general processor, digital signal processor or field programmable logic device
Part.For this unit, it will load a privately owned firmware before activation, and it is different can to assign this programmable arithmetic element
Function.That is, the function of this module can re-define after chip production, it is also assumed that in chip running
Its attribute can be changed.The shortcomings that this unit is that area can be bigger than the hardware of fixing function, and advantage is flexible.
Universal operating unit 14, is used as the processing of some general-purpose operations of neutral net, such as multiplication, addition, activation primitive,
Chi Hua, convolution etc..Because these operations are the frequency of occurrences highest computings in neutral net, and its operand often compares
Greatly, so we select to harden these units, to lift the overall performance of chip, power consumption is reduced.
Piece internal memory storage media 15, effect are in order to which the data relay between internal several modules uses, because in nerve net
In network processing, data are the structures of a flowing water, i.e., the result of last computing can be taken as the input of computing next time.By it
Be placed in piece, IO access can be saved.
Disposably can programming module 20, for the key of storage content deciphering module and the content of piece outer storage medium 200
The position of safety zone.These contents can only be modified once after chip production, and power down still has.This module also has
There is the content that CPU50 can not access this module；The information that this module passes to other modules is hardwired, rather than by general
Bus passes to corresponding module.Shield the passage that software obtains decruption key.Again because this module is disposable programming, prevent
Software is stopped and the position of safety zone in piece outer storage medium 200 is changed to other positions, so that CPU50 can be accessed
Neutral net order and parameter after to decryption.
Content decryption module 30, is responsible for the neutral net order by encryption and piece outer storage medium 200 is arrived in parameter decryption
Safety zone.Safety zone is determined by value that disposably can be in programming module, can only be modified after dispatching from the factory and once (be determined by scheme
It is fixed).When the neutral net to encryption is decrypted, this module calls key pair encryption net that disposably can be in programming module 20
Network is decrypted, and the content after decryption is write and can only write the content safety region of piece outer storage medium.
The outer safety zone management module 40 of piece, this module can be entered according to the flag bit of privately owned definition to modules in chip
The division of row safe class.Some modules are allowed to be written and read to safety zone outside piece (such as neutral net accelerating module), it is allowed to
Some modules enter row write (such as content decryption module) to safety zone outside piece, do not allow other modules to carry out safety zone outside piece
Read-write.
CPU50 is responsible for dispatching the work of modules.
Other modules 60, the basic application for neutral net, be bound to the input and output for being related to data.At voice
Input and the output module of voice are had exemplified by reason, in chip.
Piece outer storage medium 200, because neutral net possesses the characteristic of quantity of parameters.Storage medium in piece in general
The parameter (consideration based on area) of whole network can not be put down.In general chip solution, can all there is piece outer storage medium, such as
Dynamic RAM.
Solution development business carries out a neutral net speeding scheme based on content safety using above-mentioned hardware module and developed
When, it is necessary to carry out following step：
1. the nerve net that solution development business can identify the offline neural network model developed with Parameter Switch into chip
Network order；
Enciphering and deciphering algorithm is to its god used by 2. solution development business uses the unique key and chip known to them offline
It is encrypted through networking command；
3. after the completion of application scheme exploitation, to disposably can burned unique key in programming module 20, and specify outside piece
Place of safety size in memory；
4. after application scheme work, if the neutral net order of encryption, CPU50 calls content decryption module 30 to add
Close neutral net order is decrypted to the place of safety in piece outer storage medium 200；If non-encrypted neutral net order,
CPU50 then directly copies the neutral net order to the non-security district of piece outer storage medium 200；
5. when neutral net order is after the completion of the placement of piece outer storage medium 200, CPU50 calls neutral net accelerating module
10 read the neutral net order in piece outer storage medium 200, and carry out control of authority according to the source of neutral net order；I.e.
Neutral net order outside piece outer storage medium safety zone is unable to control neural network accelerator and piece outer storage medium is pacified
It is region-wide to be written and read operation；
It is 6. all in the meeting detection chip of piece outer storage medium safety zone management module 40 during whole chip is run
Access of the module to piece outer storage medium, if discovery content decryption module is read to safety zone or other modules
Operation is written and read to safety zone, then performs the operation of reset chip；Other moulds of neutral net accelerator are removed i.e. in chip
Block is responsible for by safety zone management module 40 outside piece the safety zone access rights of piece outer storage medium 200.
Claims (2)
1. a kind of neutral net accelerator chip framework based on safety, including neutral net accelerating module, disposably can programming
The outer safety zone management module of module, content decryption module, piece；It is characterized in that：
Described neutral net accelerating module, carried out for the order to neutral net hardware-accelerated；
It is described it is disposable can programming module, the ground divided for safety zone outside the key management to content decryption module and piece
Location manages；Its content can only be written over once in whole chip life cycle, and the content write cannot be irrelevant
Module is read；
Described content decryption module, for operation to be decrypted to the neutral net order of encryption and parameter, when to encryption
When data are decrypted, its can only call disposably can the key of programming module be decrypted, and it can only be stored outside piece
The non-security district of medium is the data deciphering of encryption to the safety zone of piece outer storage medium, it is impossible to the non-of piece outer storage medium
Place of safety carries out write operation, can not carry out read operation to the place of safety of piece outer storage medium；
The outer safety zone management module of described piece, disposably can hardwired outer safety zone pair of programming module for basis
Authority when modules access chip external memory is controlled；It is according to the flag bit of privately owned definition to modules in chip
Carry out the division of safe class；Part of module is allowed to be written and read safety zone outside piece, it is allowed to which part of module outside piece to storing
Row write is entered in the safety zone of medium, does not allow other modules to be written and read safety zone outside piece.
A kind of 2. neutral net accelerator chip framework based on safety as claimed in claim 1, it is characterised in that：Described
Neutral net accelerating module includes safety management module and programmable arithmetic element；
The safety management module, for the order to neutral net, whether the safety zone from chip external memory is examined
Survey, and to may be programmed arithmetic element and universal operating unit to outside piece can the read-write process of storage medium be monitored；To nerve
Whether the order of network is judged from chip external memory safety zone, if order comes from the place of safety of chip external memory
Involved all safety zones that chip external memory can not be operated to chip external memory read-write in domain, then this order；
The programmable arithmetic element, the neutral net operation for that can not be realized to universal operating unit accelerate；It is logical
With processor, digital signal processor or field programmable logic device.
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Cited By (6)
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| CN109040091A (en) * | 2018-08-17 | 2018-12-18 | 中科物栖（北京）科技有限责任公司 | The encryption method and device of deep neural network model |
| CN109981252A (en) * | 2019-03-12 | 2019-07-05 | 中国科学院信息工程研究所 | A kind of artificial intelligence process device safety enhancing system and method based on critical path encryption |
| CN112396168A (en) * | 2019-08-13 | 2021-02-23 | 三星电子株式会社 | Processor chip and control method thereof |
| CN113656086A (en) * | 2020-04-28 | 2021-11-16 | 瑞昱半导体股份有限公司 | Method for safely storing and loading firmware and electronic device |
| WO2023016030A1 (en) * | 2021-08-11 | 2023-02-16 | 华为技术有限公司 | Neural network parameter deployment method, ai integrated chip, and related apparatus thereof |
| CN116150784A (en) * | 2022-12-30 | 2023-05-23 | 上海物骐微电子有限公司 | Neural network safety protection method, system, accelerator and chip |
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Application publication date: 20180406 |