CN107872657A - The method of color gamut space conversion based on FPGA - Google Patents
The method of color gamut space conversion based on FPGA Download PDFInfo
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- CN107872657A CN107872657A CN201711220625.9A CN201711220625A CN107872657A CN 107872657 A CN107872657 A CN 107872657A CN 201711220625 A CN201711220625 A CN 201711220625A CN 107872657 A CN107872657 A CN 107872657A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/10—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths
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Abstract
The invention discloses a kind of method of the color gamut space conversion based on FPGA, adopt the present invention and processing procedure is divided into five parallel parts；Tri- component values of RGB of a pixel are received in the Part I of streamline and are deposited, and are completed in the Part II of streamline and position and subtraction operate, determine the size ordering scenario of tri- component values of this pixel RGB；In the algorithmic formula that the Part III of streamline is changed to HSV color gamut spaces according to the size ordering scenario and RGB color domain space of tri- components of RGB of this pixel into the parameter assignment needed for streamline lower part, dividing module is called in the Part IV of streamline and required parameter is inputted into dividing module, the value of tri- components of HSV after color gamut space conversion is calculated in the Part V of streamline using obtained dividing module output result, the present invention substantially increases the conversion speed in image gamut space, is provided a great convenience for follow-up image procossing.
Description
Technical field
The invention belongs to industrial machine visual field, and in particular to a kind of RGB color domain space based on FPGA to HSV colors
The implementation method of domain space high-speed transitions method.
Background technology
Rgb color model is a kind of color standard of industrial quarters, be by the change to redgreenblue passage and he
Mutual superposition obtain model color；HSV colour models are then the intuitive natures according to color, by face in model
Color is divided into tone, saturation degree, three passages of lightness；Compared with RGB colour models, HSV colour models are more suitable for figure
As the application in terms of segmentation.In industrial machine visual field, because the view data of imaging sensor collection is usually rgb color
Model, so being frequently necessary to carry out view data the conversion of color gamut space；In the conventional technology, generally by DSP or on
Position machine completes the realization of color gamut space transfer algorithm, it is difficult to accomplishes the real-time conversion of view data color gamut space.
The content of the invention
The present invention is in view of the shortcomings of the prior art, it is proposed that a kind of RGB color domain space based on FPGA is empty to HSV colour gamuts
Between high-speed transitions method：Conversion process is carried out to the view data of input using pipelined fabric, processing procedure is divided into
Five parallel parts, the conversion process of a pixel data is completed by the way of Pyatyi flowing water.At first of streamline
Tap is received tri- component values of RGB of a pixel and deposited, and is completed in the Part II of streamline and position and subtraction operate, really
The size ordering scenario of fixed this pixel tri- component values of RGB；Streamline Part III according to tri- points of the RGB of this pixel
The formula that the size ordering scenario and RGB color domain space of amount are changed to HSV color gamut spaces is the ginseng needed for streamline lower part
Number assignment, call dividing module in the Part IV of streamline and required parameter is inputted into dividing module, using obtained division
The value of tri- components of HSV after color gamut space conversion is calculated in the Part V of streamline for module output result.
RGB color domain space realizes that step includes to HSV color gamut space high-speed transitions methods：
Step 1：Definition register R_Raw, G_Raw, B_Raw are used for depositing the original of tri- components of RGB of a pixel
Data value, and gather and receive these three values, the step is located at the Part I of streamline；
Step 2：Define sub_R_G, sub_G_R, sub_R_B, sub_B_R, sub_B_G and sub_G_B；6 differences
Register is used for depositing R_Raw, the difference in tri- registers of G_Raw, B_Raw between any two；And 6 difference registers are entered
Row assignment；Wherein sub_R_G value be equal to R_Raw before highest order and it is upper one 0 after value subtract G_Raw before highest order simultaneously
Value after upper one 0；Sub_G_R value is equal to the value that G_Raw values subtract R_Raw；Sub_B_R value is equal to B_Raw in highest
Before position and it is upper one 0 after value subtract R_Raw before highest order and it is upper one 0 after value；Sub_R_B value is equal to R_Raw values
Subtract B_Raw value；Sub_G_B value be equal to G_Raw before highest order and it is upper one 0 after value subtract B_Raw in highest order
Value after preceding and upper one 0；Sub_B_G value is equal to the value that B_Raw values subtract G_Raw.The step is located at the second of streamline
Part；
Step 3：Take sub_R_G, the highest order of these three difference registers of sub_G_B, sub_B_R and into 3 digits
According to register Comp is deposited at, tri- component size ordering scenarios of RGB of original pixels are judged according to this Comp value.
During as subtraction before the highest order of subtrahend and minuend and upper 10 is used as flag bit, then carry out subtraction fortune
Calculate, if big number subtracts hour, then a high position for minuend does not borrow, the highest order of difference or 0；If decimal subtracts greatly
Number, can be borrowed, the highest order of difference can become 1 in a high position for minuend.For tri- component values of RGB of a pixel, remove
Situation all equal RGB, share 6 kinds of arrangement modes；Therefore according to Comp 6 kinds of situations of value can include come：Work as Comp
R_Raw can be obtained during equal to 001>G_Raw>B_Raw；R_Raw can be obtained when Comp is equal to 011>B_Raw>G_Raw；As Comp etc.
G_Raw can be obtained when 101>R_Raw>B_Raw；G_Raw can be obtained when Comp is equal to 100>B_Raw>R_Raw；When Comp is equal to
B_Raw can be obtained when 010>R_Raw>G_Raw；B_Raw can be obtained when Comp is equal to 110>G_Raw>R_Raw.The step is positioned at stream
The Part II of waterline；
Step 4：Define symbol flag bit sign_flag；Definition calculates the dividend register h_ used during H components
Dividend, divisor register h_divisor and addened register h_add；Definition calculates the dividend used during S components and posted
Storage s_dividend and divisor register s_divisor；Definition calculates the cache register v used during component V；
When Comp value is equal to values of the 001 seasonal sign_flag equal to 0, h_dividend equal to 60*sub_G_B's
Value, h_divisor value are equal to sub_R_B value, and h_addd value of the value equal to 0, s_dividend is equal to (2N-1)*
The value of sub_R_B value, wherein N is the bit wide of output data, and s_divisor value is equal to R_Raw value, and v value is equal to R_
Raw value；When Comp value is equal to values of the 011 seasonal sign_flag equal to 1, h_dividend equal to 60*sub_B_G's
Value, h_divisor value are equal to sub_R_G value, and h_addd value of the value equal to 360, s_dividend is equal to (2N-1)*
Sub_R_G value, s_divisor value are equal to R_Raw value, and v value is equal to R_Raw value；When Comp value is equal to 101
Values of the seasonal sign_flag equal to 1, h_dividend is equal to 60*sub_R_B value, and h_divisor value is equal to sub_G_B
Value, the value of h_addd value equal to 120, s_dividend is equal to (2N- 1) * sub_G_B value, s_divisor value etc.
In G_Raw value, v value is equal to G_Raw value；It is equal to 0, h_ when Comp value is equal to 100 seasonal sign_flag
Dividend value is equal to 60*sub_B_R value, and h_divisor value is equal to sub_G_R value, and h_addd value is equal to
120, s_dividend value is equal to (2N- 1) * sub_G_R value, s_divisor value are equal to G_Raw value, v value etc.
In G_Raw value；It is equal to 60*sub_R_G when Comp value is equal to values of the 010 seasonal sign_flag equal to 0, h_dividend
Value, h_divisor value is equal to sub_B_G value, and h_addd value of the value equal to 240, s_dividend is equal to (2N-
1) * sub_B_G value, s_divisor value are equal to B_Raw value, and v value is equal to B_Raw value；When Comp value is equal to
Values of the 110 seasonal sign_flag equal to 1, h_dividend is equal to 60*sub_R_G value, and h_divisor value is equal to sub_
B_G value, h_addd value of the value equal to 240, s_dividend are equal to (2N- 1) * sub_B_G value, s_divisor value
Value equal to B_Raw, v value are equal to B_Raw value；It is equal to 0 when Comp value is not equal to above-mentioned value season sign_flag,
Value value equal to 0, s_dividend of value of the h_dividend value equal to 0, h_divisor equal to 1, h_addd is equal to 0
Value, s_divisor value are equal to 1 value, and v value is equal to R_Raw value；
Because the definition of S components is that maximum in tri- components of RGB subtracts minimum value and obtained again divided by after maximum
Business, it is a decimal between 0 to 1, first will be by the calculating of progress S components because the bit wide of output be N positions
Divisor is multiplied by (2N- 1) codomain of S components thus, is mapped to 0 to (2N- 1) in scope；The step is located at the of streamline
Three parts；
Step 5：Two LPM dividing modules u_div_h, u_div_s are called to be respectively used to calculate H components and S components,
Dividing module u_div_h dividend is that h_diviend divisors are h_divisor, and its result is stored in into register h_
In quotient, dividing module u_div_s dividend is that s_diviend divisors are s_divisor, and the deposit of its result is posted
In storage s_quotient.The step is located at the Part IV of streamline；
Step 6：Value and the output of tri- components of HSV are calculated according to the result of dividing module：According to sign_flag value
The value of H components is determined, when sign_flag is equal to 0, value of the value equal to h_quotient of H components adds h_add value, when
Value of the value of H components equal to h_add subtracts h_quotient value when sign_flag is equal to 1, because the bit wide position N of output
Position, the codomain of H components is 0 to 360, so carrying out codomain conversion to H components：When (2N- 1) when being more than 360, the H components of output
It is worth and is multiplied by ((2 for the value obtained by calculatingN/ 360), -1) codomain is expanded and ensured 0 to (2N- 1) in the range of, when (2N-1)
During less than 360, the H component values of output are the value divided by (360/ (2 obtained by calculatingN- 1))+1, codomain is reduced and ensured
0 to (2N- 1) in the range of；The value of S components is equal to s_quotient value, and the value of V component is equal to register v in step 5
Value.The step is located at the Part V of streamline.
Compared with prior art, the beneficial effects of the invention are as follows：Realize a kind of RGB color gamut spaces based on FPGA
To the method for HSV color gamut space high-speed transitions, conversion process is carried out to the view data of input using pipelined fabric, can be
Transformation result is exported after single clock, the conversion of real-time color gamut space is carried out to the view data of collection by way of hardware,
The conversion speed in image gamut space is substantially increased, is provided a great convenience for follow-up image procossing.
Brief description of the drawings
Fig. 1 is the algorithm flow chart that RGB color domain space is changed to HSV color gamut spaces；
Fig. 2 is the pipelined fabric schematic diagram for realizing algorithm.
Embodiment
A kind of method of RGB color domain space based on FPGA to HSV color gamut space high-speed transitions；As shown in Figure 1：RGB color
Domain space reads in an original image pixels value to the algorithm that HSV color gamut spaces are changed and deposits R_Raw first, G_Raw, B_Raw
In register, then carry out mathematic interpolation, make sub_R_G value be equal to R_Raw before highest order and it is upper one 0 after value subtract
Go G_Raw before highest order and it is upper one 0 after value；Sub_G_R value is equal to the value that G_Raw values subtract R_Raw；sub_B_R
Value be equal to B_Raw before highest order and it is upper one 0 after value subtract R_Raw before highest order and it is upper one 0 after value；sub_
R_B value is equal to the value that R_Raw values subtract B_Raw；Sub_G_B value be equal to G_Raw before highest order and it is upper one 0 after
Value subtract B_Raw before highest order and it is upper one 0 after value；Sub_B_G value is equal to the value that B_Raw values subtract G_Raw；Connect
And take sub_R_G, the highest order of these three difference registers of sub_G_B, sub_B_R is simultaneously deposited at deposit into 3 data
Device Comp, tri- component size ordering scenarios of RGB of original pixels are judged according to this Comp value；Finally according to different
Conversion formula corresponding to tri- component size ordering scenario applications of RGB obtains the value of HSV components.
As shown in Figure 2：Conversion process is carried out to the view data of input using pipelined fabric, processing procedure is divided into
Five parallel parts, the conversion process of a pixel data is completed by the way of Pyatyi flowing water.At first of streamline
Tap is received tri- component values of RGB of a pixel and deposited, and is completed in the Part II of streamline and position and subtraction operate, really
The size ordering scenario of fixed this pixel tri- component values of RGB；Streamline Part III according to tri- points of the RGB of this pixel
The algorithmic formula that the size ordering scenario and RGB color domain space of amount are changed to HSV color gamut spaces is needed for streamline lower part
Parameter assignment, streamline Part IV call dividing module and by required parameter input dividing module, using what is obtained
The value of tri- components of HSV after color gamut space conversion is calculated in the Part V of streamline for dividing module output result.
RGB color domain space realizes that step includes to HSV color gamut space high-speed transitions methods：
Step 1：Definition register R_Raw, G_Raw, B_Raw are used for depositing the original of tri- components of RGB of a pixel
Data value, and gather and receive these three values, the step is located at the Part I of streamline；
Step 2：Define sub_R_G, sub_G_R, sub_R_B, sub_B_R, sub_B_G and sub_G_B；6 differences are posted
Storage is used for depositing R_Raw, the difference in tri- registers of G_Raw, B_Raw between any two；And 6 difference registers are carried out
Assignment；Wherein sub_R_G value be equal to R_Raw before highest order and it is upper one 0 after value subtract G_Raw before highest order and on
Value after one 0；Sub_G_R value is equal to the value that G_Raw values subtract R_Raw；Sub_B_R value is equal to B_Raw in highest order
Value after preceding and upper one 0 subtract R_Raw before highest order and it is upper one 0 after value；Sub_R_B value subtracts equal to R_Raw values
Go B_Raw value；Sub_G_B value be equal to G_Raw before highest order and it is upper one 0 after value subtract B_Raw before highest order
And the value after upper one 0.Sub_B_G value is equal to the value that B_Raw values subtract G_Raw.The step is located at second of streamline
Point；
Step 3：Take sub_R_G, the highest order of these three difference registers of sub_G_B, sub_B_R and into 3 digits
According to register Comp is deposited at, tri- component size ordering scenarios of RGB of original pixels are judged according to this Comp value.
During as subtraction before the highest order of subtrahend and minuend and upper 10 is used as flag bit, then carry out subtraction fortune
Calculate, if big number subtracts hour, then a high position for minuend does not borrow, the highest order of difference or 0；If decimal subtracts greatly
Number, can be borrowed, the highest order of difference can become 1 in a high position for minuend.For tri- component values of RGB of a pixel, remove
Situation all equal RGB, share 6 kinds of arrangement modes；Therefore according to Comp 6 kinds of situations of value can include come：Work as Comp
R_Raw can be obtained during equal to 001>G_Raw>B_Raw；R_Raw can be obtained when Comp is equal to 011>B_Raw>G_Raw；As Comp etc.
G_Raw can be obtained when 101>R_Raw>B_Raw；G_Raw can be obtained when Comp is equal to 100>B_Raw>R_Raw；When Comp is equal to
B_Raw can be obtained when 010>R_Raw>G_Raw；B_Raw can be obtained when Comp is equal to 110>G_Raw>R_Raw.The step is positioned at stream
The Part II of waterline；
Step 4：Define symbol flag bit sign_flag；Definition calculates the dividend register h_ used during H components
Dividend, divisor register h_divisor and addened register h_add；Definition calculates the dividend used during S components and posted
Storage s_dividend and divisor register s_divisor；Definition calculates the cache register v used during component V.The step
Positioned at the Part III of streamline；
Step 5：Assignment is carried out to the register defined in step 4 according to Comp result：When Comp value is equal to
Values of the 001 seasonal sign_flag equal to 0, h_dividend is equal to 60*sub_G_B value, and h_divisor value is equal to sub_
R_B value, h_addd value of the value equal to 0, s_dividend are equal to 255*sub_R_B value, and wherein N value is output data
Bit wide, s_divisor value is equal to R_Raw value, and v value is equal to R_Raw value；When Comp value was equal to for 011 season
Values of the sign_flag equal to 1, h_dividend is equal to 60*sub_B_G value, and h_divisor value is equal to sub_R_G value,
Value of the h_addd value equal to 360, s_dividend is equal to 255*sub_R_G value, and s_divisor value is equal to R_Raw's
Value, v value are equal to R_Raw value；It is equal to when Comp value is equal to values of the 101 seasonal sign_flag equal to 1, h_dividend
60*sub_R_B value, h_divisor value are equal to sub_G_B value, and h_addd value is equal to 120, s_dividend value
Value equal to 255*sub_G_B, s_divisor value are equal to G_Raw value, and v value is equal to G_Raw value；When Comp value
Values of the sign_flag seasonal equal to 100 equal to 0, h_dividend is equal to 60*sub_B_R value, and h_divisor value is equal to
Sub_G_R value, h_addd value of the value equal to 120, s_dividend are equal to 255*sub_G_R value, s_divisor value
Value equal to G_Raw, v value are equal to G_Raw value；It is equal to 0, h_ when Comp value is equal to 010 seasonal sign_flag
Dividend value is equal to 60*sub_R_G value, and h_divisor value is equal to sub_B_G value, and h_addd value is equal to
240, s_dividend value is equal to 255*sub_B_G value, and s_divisor value is equal to B_Raw value, and v value is equal to B_
Raw value；When Comp value is equal to values of the 110 seasonal sign_flag equal to 1, h_dividend equal to 60*sub_R_G's
Value, h_divisor value are equal to sub_B_G value, and h_addd value of the value equal to 240, s_dividend is equal to 255*sub_
B_G value, s_divisor value are equal to B_Raw value, and v value is equal to B_Raw value；When Comp value is not equal to above-mentioned value
Value value equal to 1, h_addd of values of the seasonal sign_flag equal to 0, h_dividend equal to 0, h_divisor is equal to 0, s_
Dividend value is equal to 0 value, and s_divisor value is equal to 1 value, and v value is equal to R_Raw value；
Because the definition of S components is that maximum in tri- components of RGB subtracts minimum value and obtained again divided by after maximum
Business, it is a decimal between 0 to 1, first will be by when carrying out the calculating of S components because the bit wide of output is 8
Divisor is multiplied by 255, and thus the codomain of S components is mapped in 0 to 255 scope；
Step 6：Two LPM dividing modules u_div_h, u_div_s are called to be respectively used to calculating H components and S components,
Dividing module u_div_h dividend is that h_diviend divisors are h_divisor, and its result is stored in into register h_
In quotient, dividing module u_div_s dividend is that s_diviend divisors are s_divisor, and the deposit of its result is posted
In storage s_quotient.The step is located at the Part IV of streamline；
Step 7：Value and the output of tri- components of HSV are calculated according to the result of dividing module：According to sign_flag value
The value of H components is determined, when sign_flag is equal to 0, value of the value equal to h_quotient of H components adds h_add value, when
Value of the value of H components equal to h_add subtracts h_quotient value when sign_flag is equal to 1, because the bit wide position 8 of output
Position, the codomain of H components is 0 to 360, so carrying out codomain conversion to H components：The H component values of output are the value obtained by calculating
Divided by 2, codomain is mapped in the range of 0 to 180；The value of S components is equal to s_quotient value, and the value of V component is equal to
Register v value in step 5.The step is located at the Part V of streamline.
Claims (1)
1. the method for the color gamut space conversion based on FPGA, it is characterised in that:This method specifically includes following steps：
Step 1：Definition register R_Raw, G_Raw, B_Raw are used for depositing the initial data of tri- components of RGB of a pixel
Value, and gather and receive these three values；
Step 2：Define sub_R_G, sub_G_R, sub_R_B, sub_B_R, sub_B_G and sub_G_B；6 difference registers
For depositing R_Raw, the difference in tri- registers of G_Raw, B_Raw between any two；And 6 difference registers are assigned
Value；Wherein sub_R_G value be equal to R_Raw before highest order and it is upper one 0 after value subtract G_Raw before highest order and upper one
Value after individual 0；Sub_G_R value is equal to the value that G_Raw values subtract R_Raw；Sub_B_R value is equal to B_Raw before highest order
And the value after upper one 0 subtract R_Raw before highest order and it is upper one 0 after value；Sub_R_B value subtracts equal to R_Raw values
B_Raw value；Sub_G_B value be equal to G_Raw before highest order and it is upper one 0 after value subtract B_Raw before highest order simultaneously
Value after upper one 0；Sub_B_G value is equal to the value that B_Raw values subtract G_Raw；
Step 3：Sub_R_G is taken, the highest order of these three difference registers of sub_G_B, sub_B_R is simultaneously posted into 3 data
Register Comp is stored in, tri- component size ordering scenarios of RGB of original pixels are judged according to this Comp value；
During as subtraction before the highest order of subtrahend and minuend and upper 10 is used as flag bit, then subtraction is carried out,
If big number subtracts hour, then a high position for minuend does not borrow, the highest order of difference or 0；If decimal subtracts big number,
A high position for minuend can borrow, and the highest order of difference can become 1；For tri- component values of RGB of a pixel, RGB is removed all
Equal situation, share 6 kinds of arrangement modes；Therefore according to Comp 6 kinds of situations of value can include come：When Comp is equal to
R_Raw can be obtained when 001>G_Raw>B_Raw；R_Raw can be obtained when Comp is equal to 011>B_Raw>G_Raw；When Comp is equal to 101
When can obtain G_Raw>R_Raw>B_Raw；G_Raw can be obtained when Comp is equal to 100>B_Raw>R_Raw；When Comp is equal to 010
B_Raw can be obtained>R_Raw>G_Raw；B_Raw can be obtained when Comp is equal to 110>G_Raw>R_Raw；
Step 4：Define symbol flag bit sign_flag；Definition calculates the dividend register h_ used during H components
Dividend, divisor register h_divisor and addened register h_add；Definition calculates the dividend used during S components and posted
Storage s_dividend and divisor register s_divisor；Definition calculates the cache register v used during component V；
When Comp value is equal to value of values of the 001 seasonal sign_flag equal to 0, h_dividend equal to 60*sub_G_B, h_
Divisor value is equal to sub_R_B value, and h_addd value of the value equal to 0, s_dividend is equal to (2N- 1) * sub_R_B
Value, wherein N value are the bit wide of output data, and s_divisor value is equal to R_Raw value, and v value is equal to R_Raw value；When
Comp value is equal to the value that values of the 011 seasonal sign_flag equal to 1, h_dividend is equal to 60*sub_B_G, h_divisor
Value be equal to sub_R_G value, the value of h_addd value equal to 360, s_dividend is equal to (2N- 1) * sub_R_G value, s_
Divisor value is equal to R_Raw value, and v value is equal to R_Raw value；When Comp value is equal to 101 seasonal sign_flag etc.
It is equal to 60*sub_R_B value in 1, h_dividend value, h_divisor value is equal to sub_G_B value, h_addd value
Value equal to 120, s_dividend is equal to (2N- 1) * sub_G_B value, s_divisor value are equal to G_Raw value, v value
Value equal to G_Raw；It is equal to 60*sub_B_ when Comp value is equal to values of the 100 seasonal sign_flag equal to 0, h_dividend
R value, h_divisor value are equal to sub_G_R value, and h_addd value of the value equal to 120, s_dividend is equal to (2N-
1) * sub_G_R value, s_divisor value are equal to G_Raw value, and v value is equal to G_Raw value；When Comp value is equal to
Values of the 010 seasonal sign_flag equal to 0, h_dividend is equal to 60*sub_R_G value, and h_divisor value is equal to sub_
B_G value, h_addd value of the value equal to 240, s_dividend are equal to (2N- 1) * sub_B_G value, s_divisor value
Value equal to B_Raw, v value are equal to B_Raw value；It is equal to 1, h_ when Comp value is equal to 110 seasonal sign_flag
Dividend value is equal to 60*sub_R_G value, and h_divisor value is equal to sub_B_G value, and h_addd value is equal to
240, s_dividend value is equal to (2N- 1) * sub_B_G value, s_divisor value are equal to B_Raw value, and v value is equal to
B_Raw value；When Comp value is equal to 0, h_ not equal to value of above-mentioned value season sign_flag equal to 0, h_dividend
Value of value of the divisor value equal to 1, h_addd equal to 0, s_dividend is equal to 0 value, and s_divisor value is equal to 1
Value, v value are equal to R_Raw value；
Because the definition of S components is the business that maximum in tri- components of RGB subtracts that minimum value obtains again divided by after maximum, it is
One decimal between 0 to 1, because the bit wide of output is N positions, when carrying out the calculating of S components first by dividend
It is multiplied by (2N- 1) codomain of S components thus, is mapped to 0 to (2N- 1) in scope；
Step 5：Two LPM dividing modules u_div_h, u_div_s are called to be respectively used to calculate H components and S components, division
Module u_div_h dividend is that h_diviend divisors are h_divisor, and its result is stored in register h_quotient,
Dividing module u_div_s dividend is that s_diviend divisors are s_divisor, and its result is stored in into register s_
In quotient；
Step 6：Value and the output of tri- components of HSV are calculated according to the result of dividing module：H is determined according to sign_flag value
The value of component, when sign_flag is equal to 0, value of the value equal to h_quotient of H components adds h_add value, works as sign_
Value of the value of H components equal to h_add subtracts h_quotient value when flag is equal to 1, because the bit wide position N positions of output, H components
Codomain be 0 to 360, so to H components carry out codomain conversion：When (2N- 1) when being more than 360, the H component values of output are calculating
Resulting value is multiplied by ((2N/ 360), -1) codomain is expanded and ensured 0 to (2N- 1) in the range of, when (2N- 1) it is less than 360
When, the H component values of output are the value divided by (360/ (2 obtained by calculatingN- 1))+1, codomain is reduced and ensured 0 to (2N-1)
In the range of；The value of S components is equal to s_quotient value, and the value of V component is equal to the value of register v in step 5.
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