CN107871520A - The adaptive operation of 3D memories - Google Patents
The adaptive operation of 3D memories Download PDFInfo
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- CN107871520A CN107871520A CN201710511496.2A CN201710511496A CN107871520A CN 107871520 A CN107871520 A CN 107871520A CN 201710511496 A CN201710511496 A CN 201710511496A CN 107871520 A CN107871520 A CN 107871520A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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Abstract
A kind of three dimensional nonvolatile accumulator system includes：Sensing element, the sensing element be configured for reading the bit line of multiple parts that can be selected respectively of block bit line current and/or voltage and for will corresponding result with reference to compared with；And adjustment unit, the adjustment unit are configured for individually changing the operating parameter for the part that one or more of the multiple part that can be selected respectively can select respectively in response to the comparison to the corresponding result and the reference.
Description
The application is the part continuation application for the U.S. Patent Application No. 15/190,749 submitted on June 23rd, 2016,
The U.S. Patent application is the U.S. Patent Application No. 14/861,951 submitted for 22nd in September in 2015, and the present U.S. is special
The continuation application of profit number 9,401,216.
Background technology
The application is related to Reprogrammable nonvolatile memory (such as semiconductor flash memory, resistance-type memory, phase
Transition storage etc.) operation.
The solid-state memory that non-volatile memories can be carried out to electric charge (is particularly taken and is encapsulated as small form factor card
EEPROM and flash-EEPROM form) have changed into various movements and portable equipment (especially information appliance and consumption
Person's electronic product) in selected storage device.Unlike the same RAM (random access memory) as solid-state memory, flash memory
It is non-volatile and even retains its data storage after power off.Moreover, unlike ROM (read-only storage), class
Disk storage equipment is similar to, flash memory is rewritable.
Flash-EEPROM is similar to EEPROM (Electrically Erasable Read Only Memory), because it can be wiped free of
And the nonvolatile memory for making new data write or be " programmed " into its memory cell.Both field effect transistor is utilized
Floating on the channel region between source region and drain region in the semiconductor substrate is positioned in tubular construction (not connect
Connect) conductive grid.Then, control gate is provided by floating boom.The threshold voltage characteristic of transistor is by being retained on floating boom
The amount control of electric charge.That is, for the given charge level on floating boom, in " on " transistor to allow its source area
Between domain and drain region before conduction, the relevant voltage (threshold value) that will apply to control gate be present.Such as flash-EEPROM
Flash memory allows simultaneously erased whole memory cell block.
Floating boom can keep some electric charges, and therefore may be programmed into the intraoral any threshold voltage of threshold voltage window
It is horizontal.The size of threshold voltage window is defined by the minimum and maximum threshold level of equipment, the minimum and maximum threshold level
And then with can be programmed on floating boom described in some electric charges it is corresponding.Threshold window generally depends on the spy of memory devices
Property, operating condition and history.In principle, each different decomposable asymmetric choice net threshold voltage level scope in window can be used for specifying
The definite memory state of unit.
Non-volatile memory devices are also by with the memory cell system for storage or the dielectric layer of " capture " electric charge
Into.Use dielectric layer rather than previously described conductive floating gates element.ONO dielectric layer extends across source diffusion and drain diffusion
Between raceway groove.The electric charge of one data bit is positioned in the dielectric layer adjacent with draining, and the electric charge of another data bit
It is positioned in the dielectric layer adjacent with source electrode.The two of charge storage region entered by reading being spatially separating in dielectric respectively
State processed implements multi-state data storage.
Many nonvolatile memories are formed as two-dimentional (2D) along substrate (for example, silicon substrate) surface or plane stores
Device.Other nonvolatile memories are three-dimensional (3D) memories, and the 3D memories are monolithically formed in being disposed in lining
In one or more physical memory cells arc levels of active region above bottom.
The content of the invention
In three dimensional memory system, block can be formed by the part that can be selected respectively.For example, in nand flash memory, trail
Conjunction can share selection line, so that this set of strings in block can select respectively.In other memories, other peaces
Row can cause the part that can select respectively, and the part that can be selected respectively may have and can measure and can be used for marking
Know when the characteristic being adjusted to the operating parameter (such as program voltage) of corresponding part.In resistance-type memory (example
Such as, ReRAM), local bitline can extend between horizontally extending wordline and the local bitline and wordline at place not at the same level
Resistance-type memory element vertically extend.This local bitline of a line can be selected together by row select line.Similar arrangement can
For other memory components such as such as phase transition storage.Can be referred to as " cross point memory " alternative arrangement include with
Square different height and in the different (examples of memory component from vertically extending between wordline and bit line on the surface of a substrate
Such as, it is orthogonal) direction on horizontally extending wordline and bit line.Memory component can be resistive element, electric charge storage or
Capture element, phase-change element or any other appropriate memory component.
Block in three dimensional nonvolatile memory can include multiple NAND string set that can be selected respectively, it is the multiple can
Some NAND string set that can be selected respectively in the NAND string set selected respectively can have NAND string characteristic just
Characteristic outside normal scope, this may make them in the failure of some point (either during test or during operation).For example,
Because the electric current for the NAND string set that can be selected respectively is flowed through due to being connected with being wiped free of memory cell during checking is wiped
Resistance and it is very low, can occur in which erasing failure.This resistance may for example due between NAND string and bit line or
Bad connection between NAND string and common-source, or may be due to one or more selection transistors or some other members
Part.The low current and caused by can be overcome due to this resistance by applying higher bit-line voltage.Can be in the base by string
On plinth, by column on the basis of it is (wherein, row include multiple bit lines) or complete for the NAND string set that can entirely select respectively
Into this point.The record for indicating the bit-line voltage to be used can be kept.Can be by applying the selection line voltage increased
To make the low current as caused by selection transistor reach acceptable level.In (such as the increase of the needs of block modified parameters
Bit line or selection line voltage) part in the data that store can be stored with the redundancy rate of increase to ensure safely
Safeguard data.
A kind of example of three dimensional nonvolatile accumulator system includes：Three dimensional nonvolatile memory block, the three-dimensional are non-
Volatile memory block includes multiple parts that can be selected respectively, and the part that can individually select respectively is included perpendicular to substrate table
Face and the multiple bit lines extended；Sensing element, the sensing element are configured for reading described piece the multiple and divided
The bit line current and/or voltage of the bit line for the part not selected and for by for the reading for the part that can individually select respectively
The corresponding result gone out is compared with reference；And adjustment unit, the adjustment unit communicate with the sensing element, the tune
Whole unit is configured for divide in response to one or more of the multiple part that can be selected respectively to described piece
The corresponding result for the part not selected is individually changed described piece the multiple with the comparison of the reference and distinguished
The operating parameter of one or more of parts that can be selected respectively in the part of selection.
The three dimensional nonvolatile memory block and the sensing element can be located in memory die and the tune
Whole unit can be located in controller nude film.A plurality of global bit line can prolong parallel to the substrate surface in a first direction
Stretch, and the multiple bit lines can be connected to a plurality of global bit line by multiple selection transistors.Selection line can
To extend on the second direction of the first direction is orthogonal to parallel to the substrate surface, the selection line is coupled to institute
Multiple selection transistors are stated to select the multiple bit lines respectively.Single bit line can extend through multiple wordline levels simultaneously
And single memory component can be formed at the horizontal place of each wordline in the multiple wordline level.The memory component
Can be electric charge storage or charge trapping element, resistive element or phase change memory component.The adjustment unit can by with
It is set to and each can be selected respectively for individually changed in response to the comparison in the multiple part that can be selected respectively
Part program voltage and/or selection voltage.Temperature input, and the adjustment unit can be provided to the adjustment unit
It can be further configured to be used to input in response to the temperature and change operating parameter.
A kind of example of three dimensional nonvolatile memory includes：A plurality of First Line, a plurality of First Line is with more than substrate
First height on surface extends along a first direction；A plurality of second line, a plurality of second line is with more than the substrate surface
Second height extends along second direction, and the second direction is orthogonal with the first direction；Multiple memory components, individually
The second line that memory component is extended at second height from the First Line at first height；Sensing element,
The sensing element is configured for reading the electric current and/or voltage and for by the result of the reading of the First Line
Compared with reference；And adjustment unit, the adjustment unit communicate with the sensing element, the adjustment unit is configured
Into for changing the operating parameter for the memory component for being connected to the First Line in response to the comparison.
The adjustment unit is configured for changing in response to the comparison and being connected to depositing for the First Line
The program voltage of memory element.The adjustment unit be configured in response to the comparison and change be connected to it is described
The reading voltage of the memory component of First Line.The multiple memory component can be that resistance-type memory element, phase transformation are deposited
Memory element or charge storage cell.Additional First Line can be with the additional height more than the substrate surface in a first direction
Extension, additional second line can be extended in a second direction with the additional height more than the substrate surface, and additional storage
Device element can extend to additional second line from the additional First Line, and the adjustment unit may be configured to use
According to the respective heights for the memory component being positioned at multiple different heights more than the substrate surface to change
State the operating parameter of memory component.Temperature input can be provided to the adjustment unit, and the adjustment unit can be by
It is further configured to be used to input in response to the temperature and change operating parameter.The a plurality of First Line, described a plurality of second
Line, the multiple memory component and the sensing element can be located in the first nude film, and the adjustment unit can be with
In the second nude film, the input of the adjustment unit is generated by the temperature sensor in second nude film.
A kind of side operated to the three dimensional nonvolatile memory including multiple parts that can be selected respectively in block
The example of method includes：Measurement passes through the electric current of the wire in the part that can be selected respectively；The electric current and preassigned are carried out
Compare；If the electric current is unsatisfactory for the preassigned, one or more variations are calculated；And then, to institute
Other voltages for stating other parts that can be selected respectively application of block are accessing the portion that other can be selected respectively described in described piece
Timesharing is kept while be not adjusted, during memory component in the part that can be selected respectively described in access, will to it is described can
The voltage that line in the part selected respectively applies adjusts one or more of variations.
One or more of variations of the part that can be selected respectively can be recorded in table, and then
One or more of variations can be obtained from the table before the part that can be selected respectively described in access.It can incite somebody to action
Enhanced redundancy scheme is applied to the data stored in the part that can be selected respectively for being unsatisfactory for the preassigned, the increasing
Strong type redundancy scheme is provided than the usual redundancy side applied to the data stored in the set of strings for meeting the preassigned
The error correcting capability of case higher degree.The temperature of the three dimensional nonvolatile memory can be measured, and can be according to the institute
What the temperature of measurement applied to adjust the line into the part that can be selected respectively and in the part that other can be selected respectively
Voltage.
A kind of example of three dimensional nonvolatile accumulator system includes：Block, described piece can select respectively comprising multiple
NAND string set；Bit line current sensing element, the bit line current sensing element are configured for reading described piece and divided
The bit line current for the NAND string set not selected and for by the bit line current compared with minimum current；And bit line
Voltage-adjusting unit, institute's bitline voltage adjustment unit communicate with the bit line current sensing element, institute's bitline voltage adjustment
Unit is configured for applying to the NAND string set that can be selected respectively with the bit line current bigger than the minimum current
Add the first bit-line voltage, and be configured for select respectively to the bit line current smaller than the minimum current
NAND string set apply the second bit-line voltage, second bit-line voltage is more than first bit-line voltage.
Can be to applying first and second bit-line voltage during described piece of programming, reading or erasing.Institute's rheme
Line current sensing element is configured for reading in described piece of the multiple NAND string set that can be selected respectively
The bit line current for the NAND string set that can each select respectively and for by each bit line current in the bit line current with
The minimum current is compared, and institute's bitline voltage adjustment unit is configured at least in described piece
In the multiple NAND string set that can be selected respectively there is bit line current any smaller than the minimum current to distinguish
The NAND string set of selection applies second bit-line voltage.Table, which can record, at least receives each of second bit-line voltage
The entry for the NAND string set that can be selected respectively, the bit line that entry instruction will apply to the NAND string set that can accordingly select respectively
Voltage.Selection line voltage sensing element is configured for reading selection line threshold voltage and is used for selection line threshold value
Voltage is compared with minimum threshold voltage；And selection line voltage-adjusting unit is configured for than described
The selection line voltage of the selection line of the smaller selection line threshold voltage of minimum threshold voltage is adjusted.Table can record with than
The entry of each NAND string set that can be selected respectively of the smaller selection line threshold voltage of the minimum threshold voltage, in table
The selection line voltage that the selection line into the NAND string set that can accordingly select respectively applies is treated in entry instruction.Self-adapting data is compiled
Code unit can be encoded using variable redundancy to data before storing, and the self-adapting data coding unit can be by
It is disposed for being applied to select respectively with the bit line current bigger than the minimum current by the first redundancy scheme
NAND string set in the data that store and be configured for the second redundancy scheme being applied to than the minimum
The data stored in the NAND string set that can be selected respectively of the smaller bit line current of electric current.Table can record with than it is described most
The entry of each NAND string set that can be selected respectively of the smaller bit line current of low current, the entry in the table indicates to treat should
For the redundancy scheme of the data stored in the NAND string set that can accordingly select respectively.
A kind of example of three dimensional nonvolatile memory includes：First in the block NAND string set that can be selected respectively, makes
Encoded with the first redundant level come the data in the NAND string set that can select respectively described first；And in described piece
The second NAND string set that can be selected respectively, using the second redundant level come in the NAND string set that can select respectively described second
Data encoded, second redundant level provides the error correcting capability than the first redundant level higher degree.
Adaptive coder/decoder is configured for the NAND string collection that can be selected respectively according to data storage
The characteristic of conjunction is coded and decoded using variable redundant level to data.Bit line adjustment unit is configured for institute
State the bit line in the first NAND string set that can be selected respectively and apply the first bit-line voltage, and for that can distinguish to described second
Bit line in the NAND string set of selection applies the second bit-line voltage.Configuration to the adaptive coder/decoder and
It can be to institute that the bit line adjustment unit, which is disposed for applying first bit-line voltage and second bit-line voltage,
State the response of the test of the first and second NAND string set that can be selected respectively.Selection line adjustment unit is configured for
First choice line in the NAND string set that can be selected respectively to described first applies first choice voltage, and is used for described
The second selection line in the second NAND string set that can be selected respectively applies the second selection voltage.First redundant level and described
What the second redundant level can select respectively according to the described first NAND string set that can be selected respectively and described second respectively
The characteristic of NAND string set determines.
It is a kind of that the three dimensional nonvolatile memory including multiple NAND string set that can be selected respectively in block is grasped
The example of the method for work includes：The electric current that measurement passes through the NAND string set that can be selected respectively with shared selection line；By institute
Electric current is stated compared with preassigned；If the electric current is unsatisfactory for the preassigned, one or more bit lines are calculated
Variation；And then, keep not adjusted in other bit-line voltages that the NAND string set that can be selected respectively to other applies
While whole, the bit-line voltage applied to the bit line for being connected to the NAND string set that can be selected respectively is adjusted.
One or more of bit line voltage shifts of the NAND string set that can be selected respectively can be recorded.Described one
Individual or multiple bit line voltage shifts can be recorded in include to be divided with measurement each of electric current for being unsatisfactory for the preassigned
In the table of the calculating bit line voltage shift for the NAND string set not selected.Enhanced redundancy scheme can be applied to be unsatisfactory for
The data stored in the set of strings of the preassigned, the enhanced redundancy scheme are provided than being applied to meeting described make a reservation for
The error correcting capability of the usual redundancy scheme higher degree of the data stored in the set of strings of standard.Can read to select respectively
NAND string set in selection line selection gate threshold voltage；Can be by the selection gate threshold voltage and minimum threshold
Voltage is compared；Can calculate can select respectively with the selection line threshold voltage smaller than the minimum threshold voltage
The selection line variation of NAND string set；And the selection line variation can be applied to then can described in access
The selection line voltage applied during the NAND string set selected respectively to the selection line.
The selection line variation of the NAND string set that can be selected respectively can be recorded, and it can be recorded
The additional selection line voltage skew for the NAND string set that he can select respectively.To be stored in the NAND string collection that can be selected respectively
Data in conjunction can be encoded using enhanced encoding scheme.
Various aspects, advantage, feature and embodiment are included in the following description of its illustrative examples, and the description should
Carried out with reference to accompanying drawing.
Brief description of the drawings
Fig. 1 schematically illustrates the main hardware components of accumulator system.
Fig. 2 schematically illustrates Nonvolatile memery unit.
Fig. 3 illustrates four kinds of different charge Qs 1 that floating boom can store to Q4 source-drain current IDWith control gate
Voltage VCGBetween relation.
Fig. 4 A schematically illustrate the memory cell strings for being organized into NAND string.
Fig. 4 B shows example of the NAND array 210 of memory cell, the NAND array is by (such as Fig. 4 A of NAND string 50
Shown in NAND string) form.
Fig. 5 illustrate with NAND configurations come tissue by parallel read-out or the page of memory cells of programming.
Fig. 6 A to Fig. 6 C illustrate the example being programmed to memory cell group.
Fig. 7 shows the example of the physical arrangement of 3D NAND strings.
Fig. 8 shows the example of the physical arrangement of U-shaped 3D NAND strings.
Fig. 9 shows the example of the cross section of the 3D NAND memory arrays with U-shaped NAND string in y-z plane.
Figure 10 A to Figure 10 C illustrate the 3-D nand memories with multiple set of strings that can be selected respectively in block
Example.
Figure 11 A and Figure 11 B shows vertical nand string.
Figure 12 illustrates the connection of vertical nand string and common-source.
Figure 13 shows the example of the block with four NAND string that can be selected respectively set.
Figure 14 A and Figure 14 B show the example of current measurement circuit.
Figure 15 shows the example of the scheme for the NAND string set that can be selected respectively for examination and maintenance.
Figure 16 illustrates the example of accumulator system.
Figure 17 shows the example of the string that can be selected respectively in nand flash memory block.
Figure 18 schematically illustrates the example of 3 D memory array.
Figure 19 shows the example of three-dimensional memory structure.
Figure 20 shows the example of resistance-type memory element.
Figure 21 A and Figure 21 B show the details of the three-dimensional storage with resistive element.
Figure 22 A and Figure 22 B shows example of cross point memory array.
Figure 23 illustrates the method operated to accumulator system.
Embodiment
Accumulator system
Semiconductor memory devices include volatile memory devices (such as dynamic random access memory (" DRAM ")
Or static RAM (" SRAM ")), non-volatile memory devices (such as resistive random access memory
(" ReRAM "), Electrically Erasable Read Only Memory (" EEPROM "), (it can also be considered EEPROM to flash memory
Collection), ferroelectric RAM (" FRAM ") and magnetic random access memory (" MRAM ")) and being capable of storage information
Other semiconductor elements.Each type of memory devices can have various configuration.For example, flash memory device can be with NAND
Or NOR configurations are configured.
Memory devices can be formed by passive and/or active component with any combinations.Pass through the side of non-limiting example
Formula, passive semiconductor memory component include ReRAM equipment components, and in certain embodiments, the element includes such as antifuse
The resistivity such as phase-change material switch memory element and (alternatively) such as diode actuation member.Further by non-limiting
The mode of example, active semi-conductor memory component include EEPROM and flash memory device element, in certain embodiments, the member
Part includes the element that such as floating boom, conductive nano-particles or charge storage dielectric material contain charge storage region.
Multiple memory components may be configured so that they are connected in series or so that each element is individually accessible
's.By way of non-limiting example, generally comprised and be connected in series using the flash memory device of NAND configurations (nand memory)
Memory component.NAND memory array may be configured so that array includes multiple memory strings, wherein, string is included altogether
Enjoy single bit line and the multiple memory components being accessed as overall.Alternately, memory component may be configured to
So that each element is individually accessible (for example, NOR memory array).NAND and NOR memory configurations are exemplary
, and memory component can be configured otherwise.
In substrate and/or top semiconductor memery device can be arranged in two or three dimensions (ratio
Such as, two dimensional memory structure or three-dimensional memory structure).
In two dimensional memory structure, semiconductor memery device is arranged at single plane or single memory equipment level
In.Generally, in two dimensional memory structure, memory component is arranged at the substrate for being arranged essentially parallel to support memory component
Major surfaces and (for example, in x-z direction planes) in the plane that extends.Substrate can be formed above it or wherein
The chip of memory element layer, or it can be that carrier substrates thereon are attached to after memory component is formed.As
Non-limiting example, substrate can include such as silicon semiconductor.
Memory component can be arranged to oldered array in single memory equipment level, such as in multiple rows and/or row
In.However, it is possible to memory component is arranged using irregular or nonopiate configuration.Each storage element in memory component
Part can have two or more electrodes or contact line, such as, bit line and wordline.
3 D memory array is arranged so that memory component occupies multiple planes or multiple memory devices levels, by
This three dimensions (that is, on x directions, y directions and z directions, wherein, y directions are substantially perpendicular to and x and z directions are basic
On parallel to substrate main surface) in formed structure.
As non-limiting example, three-dimensional memory structure can be multiple two dimensional memory device levels by vertically arranging
Stacking.As another non-limiting example, 3 D memory array may be arranged to multiple vertical rows (for example, basic
On the row that extend perpendicular to the main surface of substrate, i.e. in y-direction), each row are with multiple storage elements in each row
Part.The row can be arranged using two dimensional configurations (for example, in x-z-plane), so as to cause the three-dimensional peace of memory component
Row, element are located on the memory plane of multiple vertical stackings.Other configurations of memory component in three dimensions can also
Form 3 D memory array.
By way of non-limiting example, in three dimensional NAND memory array, memory component can be coupling in one
Rise to form NAND string in single horizontal (for example, x-z) memory devices level.Alternately, memory component can be with coupling
It is combined to be developed across the vertical nand string of multiple level memory device levels.It is contemplated that other 3-d modellings, its
In, some NAND strings include the memory component in single memory level, and other strings include depositing across multiple storage levels
Memory element.3 D memory array can also be designed using NOR configurations and ReRAM configurations.
Generally, it is square into one or more memory devices on a single substrate in monolithic three dimensional memory array
Level.Alternatively, monolithic three dimensional memory array can also have the one or more being at least partly in single substrate
Memory layer.As non-limiting example, substrate can include such as silicon semiconductor.In monolithic three dimensional array, battle array is formed
The layer of each memory devices level of row is generally formed on the layer of the background memory device level of array.However, one chip three
Tieing up the layer of the adjacent memory device level of memory array can be shared or have intermediate layer between memory devices level.
Then, again, two-dimensional array can be formed independently and be then encapsulated in and be deposited together to be formed with multiple
The non-slice memory equipment of reservoir layer.For example, non-one chip stacked memory can be deposited by being formed on the individual substrates
Then storage level is stacked on top of each other to construct by reservoir level.Can with organic semiconductor device or can before stacking by its from
Removed in memory devices level, but because memory devices level is primitively square into caused on the individual substrates
Memory array is not monolithic three dimensional memory array.In addition, multiple two dimensional memory arrays or 3 D memory array are (single
Chip or non-one chip) it can on a single chip be formed and be then encapsulated in together to form stacked chips memory devices.
Operation to memory component and usually require associated circuits system with the communication of memory component.As non-
Limitative examples, memory devices, which can have, to be used to control and drive memory component to complete such as the function such as programming and reading
Circuit system.This associated circuits system may be at on memory component identical substrate and/or on independent substrate.
For example, the controller for memory write-read operations can be located on separate controller chip and/or be located at and memory component
On identical substrate.
In other embodiments, the storage in addition to two and three dimensions example arrangement described herein can be used
Device type.
Fig. 1 schematically illustrates the accumulator system for some technologies being adapted for carrying out in technology described herein
Main hardware components.Accumulator system 90 is generally operated by HPI together with main frame 80.Accumulator system can use
Such as the form of memory card removable memory or can use embedded storage system form.Accumulator system 90
Including memory 102, the operation of the memory is controlled by controller 100.Memory 102 includes being distributed in one or more collection
Into one or more Nonvolatile memory unit arrays on circuit chip.Controller 100 can include interface circuit 110,
Processor 120, ROM (read-only storage) 122, RAM (random access memory) 130, programmable non-volatile memory 124 with
And additional component.Controller is formed generally as ASIC (application specific integrated circuit), and the part being included in this ASIC leads to
It is often dependant on application-specific.In various varying environments, accumulator system can be used together with various main frames.For example, main frame
Can be mobile device, such as, cell phone, laptop computer, music player (for example, MP3 player), global location
System (GPS) equipment, tablet PC etc..This accumulator system can be inactive in long duration and not have electric power,
During the long duration, they can suffer from including the various situations such as high temperature, vibration, electromagnetic field.Can be for wide scope ring
Low-power consumption under border condition (for example, wide temperature range), high data retain and reliability and select the memory of this main frame
System (either removable is still Embedded).Other main frames can be fixed.For example, the clothes for the Internet, applications
Business device can store the data sent and received by internet using Nonvolatile memory system.This system can be
It is kept powered on without interrupting, and can be continually visited through these periods in the period (for example, 1 year or more) of extension
Ask.Independent block can be frequently write into and be wiped, so that durability is probably issue of concern.
Physical memory structure
Fig. 2 schematically illustrates Nonvolatile memery unit.Memory cell 10 can be by with charge storage elements
20 field-effect transistor is implemented, such as, floating boom or electric charge capture (dielectric) layer.Memory cell 10 also includes source electrode 14, leakage
Pole 16 and control gate 30.
In practice, the source electrode of sensing element when applying reference voltage to control gate and drain electrode electricity are generally passed through
Conduction electric current between pole carrys out the memory state of reading unit.Therefore, can be with to each given electric charge on the floating boom of unit
Detect the respective conductive electric current on fixed reference control gate voltage.Similarly, the scope for the electric charge being programmed on floating boom
Limit respective threshold voltage window or respective conductive current window.
Alternately, instead of detecting conduction electric current among the current window of division, it is possible to set at control gate
The threshold voltage of given memory state in test, and in conduction electric current, below or above threshold current, (unit reads ginseng
Examine electric current) when detected.In one embodiment, by check conduction electric current be released through bit line electric capacity speed come
Complete the detection to the conduction electric current relative to threshold current.
Fig. 3 illustrates the source electrode-leakage of four kinds of different charge Qs 1 that floating boom can be stored optionally at any time to Q4
Electrode current IDWith control gate voltage VCGBetween relation.Biased for fixed drain voltage, four solid line IDTo VCGCurve table
Show and four kinds of possible memory shapes are corresponded respectively in the seven kinds of possible charge levels that can be programmed on the floating boom of memory cell
Four kinds of possible charge levels of state.As an example, the threshold voltage window of one-element group may range from from 0.5V to 3.5V.Can
With by threshold window is divided into by region with respective 0.5V interval come define seven kinds of possible programmable memory states " 0 ",
" 1 ", " 2 ", " 3 ", " 4 ", " 5 ", " 6 " and erase status (not shown).If for example, reference using 2 μ A as shown
Electric current IWith reference to, then memory state " 1 " can be considered at come the unit programmed using Q1, because its curve and IWith reference toIntersect at
In the threshold window region defined by VCG=0.5V and 1.0V.Similarly, Q4 is in memory state " 5 ".
As it can be seen, the state for storing memory cell is more, its threshold voltage window is drawn from the above description
Get finer.For example, memory devices can have memory cell, it is from -1.5V that the memory cell, which has scope,
To 5V threshold voltage window.This provides 6.5V Breadth Maximum.If memory cell is used to store 16 kinds of states, often
Kind state can take up from 200mV to 300mV in threshold window.This will need to program and the higher precision of read operation, with
Just required resolution ratio can be reached.
NAND structures
Fig. 4 A schematically illustrate the memory cell strings for being organized into NAND string.NAND string 50 include by its source electrode and
Drain daisy chain memory transistor M1, M2 ..., Mn (for example, n=4,8,16 or higher) series.Selection transistor S1, S2
The external world is connected to via the source terminal 54 and drain terminal 56 of NAND string respectively to control memory transistor chains.Storing
In device array, when drain selection transistor S1 is connected, source terminal is coupled to source electrode line (see Fig. 4 B).Similarly, drain electrode is worked as
When selection transistor S2 is connected, the drain terminal of NAND string is coupled to the bit line of memory array.Each memory in chain is brilliant
Body pipe 10 serves as memory cell.There is the charge storage cell 20 for the electric charge for being used to store specified rate to be deposited to represent expected for it
Reservoir state.The control gate 30 of each memory transistor allows to be controlled reading and write operation.As in figure 4b
It will be seen that, the control gate 30 of the respective memory transistor of NAND string row is all connected to same wordline.Similarly, select
The control gate 32 of each selection transistor in transistor S1, S2 is provided to respectively via its source terminal 54 and drain terminal
The control of the access of 56 pairs of NAND strings.Similarly, the control gate 32 of the corresponding selection transistor of NAND string row is all connected to
Same selection line.
When being read during programming or verifying the addressed memory transistor 10 in NAND string, its control gate 30 is supplied
There should be appropriate voltage.Meanwhile the remainder of the nonaddressable memory transistor in NAND string 50 passes through in its control gate
It is upper to apply enough voltage and be either completely switched on.In this way, effectively create from the source electrode of single memory transistor to
The conductive path of the source terminal 54 of NAND string, and it is same to the drain terminal 56 of drain electrode to the unit of single memory transistor
Sample is such.
Fig. 4 B shows example of the NAND array 210 of memory cell, the NAND array is by (such as Fig. 4 A of NAND string 50
Shown in NAND string) form.Arranged along each NAND string, bit line (such as bit line 36) is coupled to the leakage of each NAND string
Extreme son 56.Arranged along individual NAND string, source electrode line (such as source electrode line 34) is coupled to the source terminal 54 of each NAND string.And
And the control gate of the column of memory cells in being arranged along NAND string is connected to wordline (such as wordline 42).Arranged along NAND string
In the control gate of selection transistor row be connected to selection line (such as selection line 44).Whole memory in NAND string row
The appropriate voltage in wordline and selection line that cell row can be arranged by the NAND string is addressed.
Fig. 5 illustrate with NAND configurations come tissue by parallel read-out or the page of memory cells of programming.Fig. 5 substantially shows
The row of NAND string 50 gone out in Fig. 4 B memory array 210, wherein, each NAND string is explicitly show as in Fig. 4 A
Details.Physical Page (such as page 60) is the groups of memory cells for being capable of parallel read-out or programming.This passes through sense amplifier
212 corresponding page is completed.Result will be read to be latched in respective latch group 214.Each sense amplifier can be via bit line
Coupled to NAND string.Page is enabled by the shared control gate for being connected to wordline 42 of the unit of page, and each unit can be by reading
Go out amplifier access, the sense amplifier can access via bit line 36.As an example, ought read respectively or programming unit 60
During page, read-out voltage or program voltage are applied on common word line WL3 together with the appropriate voltage on bit line respectively.
The physical organization of memory
A difference between flash memory and other kinds of memory is that flash cell generally programs from erase status.Also
It is to say, generally empties the electric charge of floating boom.Then program and the electric charge addition of desired amount is back in floating boom.Flash memory is generally supported from floating
A part for electric charge is removed in grid so as to from more programming states to less programming state.This means the data of renewal can not be covered
Available data is write, and the non-writing position before being conversely written to.
In addition, wiping for all electric charges to be emptied from floating boom, and generally take the considerable time.Due to this
Reason, it will be cumbersome and very slow even to wipe by unit or page by page.In practice, memory cell array is divided into
A large amount of memory cell blocks.As for flash EEPROM system, common, block is erasure unit.That is, each block includes
The memory cell for the minimum number being wiped free of simultaneously.Wiped although concurrently polymerizeing a large amount of units in cleaning block and will improve
Performance, but size block also needs to handle a large amount of renewals and outdated data.
Each block is usually divided into many Physical Page.Logical page (LPAGE) is many for including the element number being equal in Physical Page
The programming of position or the unit of reading.In the memory that every unit stores a position (single stage unit, or " SLC " memory), one
Individual Physical Page stores the data of a logical page (LPAGE).In the memory that every unit stores two positions, Physical Page stores two logics
Page.Therefore the quantity for the logical page (LPAGE) being stored in Physical Page reflects the quantity of the position of storage per unit.Term multi-level unit (or
" MLC ") it is generally used for referring to the memory that every unit stores more than one position, including every unit stores three positions (TLC), per unit
Store four positions or the memory of more multidigit is stored per unit.In one embodiment, single page can be divided into multiple
Section, and each section can include the unit of the minimum number as basic programming operation write-once.One or more logics
The data of page are generally stored inside in a column of memory cells.Page can store one or more sectors.Sector includes number of users
According to and overhead data.
MLC is programmed
Fig. 6 A to Fig. 6 C illustrate the example being programmed to 4 state memory cells groups.Fig. 6 A, which are illustrated, to be programmed to
The memory cell group in four kinds of different distributions of the threshold voltage of memory state " E ", " A ", " B " and " C " is represented respectively.Figure
6B illustrates the initial distribution of " erasing " threshold voltage of erasing memory.The many that Fig. 6 C illustrate in a memory cell is deposited
The example of memory after storage unit is programmed.Substantially, unit initially has " erasing " threshold voltage, and compiles
Journey is moved into much higher value and entered by the horizontal vV of checking1、vV2And vV3In a region in three regions defined.With this
Mode, each memory cell may be programmed into one of three kinds of programming states " A ", " B " and " C " or under " erasing " states
Keep unprogrammed.As memory is more programmed, the initial distribution of " erasing " state as illustrated in figure 6b will become
It is narrower, and erase status is by " 0 " state representation.
Every kind of memory state in four kinds of memory states is can be used to indicate that with low level and 2 high-order codes.
For example, " E ", " A ", " B " and " C " state is represented by " 11 ", " 01 ", " 00 " and " 10 " respectively.Can be by " complete sequence "
2 data of reading from memory are read out under pattern, under the pattern, by being respectively relative in three sub- passbands
Reading define threshold value rV1、rV2And rV3Read out and read the two positions together.
3D NAND structures
The alternative arrangement of conventional two dimension (2D) NAND array is three-dimensional (3D) array.Compared to 2D NAND arrays (its edge
The plane surface for semiconductor wafer is formed), 3D arrays upwardly extend from wafer surface and generally include to upwardly extend deposits
Storage unit heap or row.It is possible that various 3D, which are arranged,.In one kind arranges, with one end (for example, source electrode) at wafer surface
And the other end (for example, drain electrode) at top is vertically formed NAND string.In another kind arranges, formed with U-shape
NAND string, so that the both ends of NAND string are accessed at top, so as to promote the connection between this string.
Fig. 7 shows what the Vertical Square in the x-y plane perpendicular to substrate was upwardly extended and (that is, extended in a z-direction)
First example of NAND string 701.Formed in vertical bit lines (local bitline) 703 through the place of wordline (for example, WL0, WL1 etc.)
Memory cell.Electric charge capture layer storage electric charge between local bitline and wordline, the electric charge are influenceed by being wrapped coupled to it
The threshold voltage for the transistor that the wordline (grid) of the vertical bit lines (raceway groove) enclosed is formed.Can by formed word line stacks and
Then the memory hole of memory cell will be formed at which to form this memory cell by etching.Then, by memory
Hole be lined with electric charge capture layer and fill with appropriate local bitline/channel material (fill with appropriate dielectric layer so as to carry out every
From).
As plane NAND string, the either end that selection gate 705,707 is positioned in string sentences just permission NAND string choosing
Externally connected element 709,711 or it is isolated from it to selecting property.This outer member is usually that wire (for example is a large amount of NAND
The common source line of string service).Can be to operate vertical nand string and single stage unit with plane NAND string similar mode
(SLC) or multi-level unit (MLC) is both possible.Although Fig. 7 is shown with 32 units (0 to 31) being connected in series
NAND string example, but the unit number in NAND string can be any right quantity.For clarity, it is not shown all
Unit.It will be appreciated that form extra cell in the place that the (not shown) of wordline 3 to 29 intersects with partial vertical bit line.
Fig. 8 shows the second example of the NAND string 815 extended in vertical direction (z directions).In this case,
NAND string 815 forms U-shape, is connected with the outer member (source electrode line " SL " and bit line " BL ") positioned at structural top.Connection
Two wings 816A, 816B of NAND string 815 controllable grid (backgate " BG ") are in the bottom of NAND string 815.In wordline WL0
To WL63 intersect with vertical local bit line 817 place formed altogether 64 units (although in other examples, it can be provided
The unit of his quantity).The either end that selection gate SGS, SGD is positioned in NAND string 815 is sentenced and just controlled to NAND string 815
Connection/isolation.
Vertical nand string can be arranged to form 3D NAND arrays in a variety of ways.Fig. 9 shows multiple U in block
Shape NAND string is connected to the example of bit line.In this case, can be selected respectively in the presence of n that are connected to bit line (" BL ") in block
The set of strings (string 1 to string n) selected.The value of " n " can be any appropriate numeral, for example, 8,12,16,32 or more.String is being orientated
The upper odd number string being connected with its source electrode in left and its source electrode are in the even number string alternating of right.This arrangement is suitable
But not necessarily, and other patterns are also possible.
Common source line " SL " is connected to one end (opposite with the end for being connected to bit line) of each NAND string.This can be regarded
For the source terminal of NAND string, bit line end is considered as to the drain electrode end of NAND string.Common source line can be connected to the institute of block
There is source electrode line to be controlled together by peripheral circuit.Therefore, the NAND string of block extend parallel at one end between bit line and
Other end extension parallel between common source line.
Figure 10 A show memory construction with the cross section along bit line direction (along y directions), wherein, straight line is vertical
NAND string is from substrate or the connection of neighbouring common-source extends on the physical level of memory cell the global bit line extended
(GBL0 to GBL3).The wordline in given physical level in block is formed by sheet of conductive material.Memory pore structure extends downwardly
Deposited through these sheet of conductive material to be formed by what vertical bit lines (BL0 to BL3) were vertically connected in series (along z directions)
Storage unit is so as to forming vertical nand string.In given block, the multiple NAND string (examples for being connected to given global bit line be present
Such as, GBL0 is connected with multiple BL0).NAND string is grouped into the set of strings of shared shared selection line.Thus, for example, can will be by
Drain selection line SGS0 and the NAND string of drain electrode selection line SGD0 selections are considered as NAND string set and can be assigned therein as going here and there
0, and the NAND string by drain selection line SGS1 and the SGD1 selections of drain electrode selection line can be considered as another NAND string collection and merged
And string 1 as shown can be assigned therein as.Block can be charge-coupled by any an appropriate number of this trail that can select respectively
Into.It will be appreciated that Figure 10 A illustrate only GBL0 to GBL3 part, and these bit lines further extend simultaneously in y-direction
And it can be connected with the additional NAND string in described piece and in other blocks.In addition, additional bit line and GBL0 to GBL3 are abreast
Extend (for example, at diverse location along x-axis, in the position above or below of Figure 10 A cross section).
Figure 10 B schematically illustrate Figure 10 A NAND string set that can be selected respectively.It can be seen that global bit line
Every global bit line in (GBL0 to GBL3) is connected to multiple NAND strings that can be selected respectively in the part of shown block
Set (for example, GBL0 is connected to the vertical bit lines BL0 of string 0 and is additionally coupled to the vertical bit lines BL0 of string 1).In certain situation
Under, the wordline electrical connection of all strings of block, for example, the WL0 in string 0 can be connected to string 1, the WL0 of string 2 etc..Can will be this
Wordline is formed as extending through the continuous conduction material piece of all set of strings of block.Source electrode line can also be total to by all strings of block
With.For example, a part for substrate can be doped to be formed similar with below other blocks conductive below block
The continuous conduction region of zone isolation, so as to allow to be biased respectively to wipe block as entirety.Source electrode and drain electrode are selected
Line is selected not shared by different set of strings, so that SGD0 and SGS0 can be for example biased to select string 0, and nothing
SGD1 and SGS1 need to be biased in a similar manner.Therefore, can be in the holding of 1 (and other set of strings) of string and global bit line
0 (being connected to global bit line and common-source) of string is individually selected while isolation with common-source.In programming and read operation phase
Between memory cell in access block generally include to apply (for example, SGS0 and SGD0) selection voltage to selection line, while to
The every other selection line (for example, SGS1 and SGD1) of block, which applies, cancels selection voltage.Then, appropriate electricity is applied to the wordline of block
Pressure so that selected by accessing in set of strings particular word line (read voltage for example, applying to particular word line, at the same to
Other wordline apply reading and pass through voltage).Can be to whole block (all set of strings in block) rather than to the specific string in block
Erasing operation is applied in set.
Figure 10 C show Figure 10 A and Figure 10 B the NAND string set that can be selected respectively with the cross section along X-Z plane
(string 0).It can be seen that every global bit line (GBL0 to GBLm) is connected to a vertical nand string (vertical bit lines in string 0
BL0 to BLm).Can be by applying appropriate voltage to selection line SGD0 and SGS0 to select string 0.Other set of strings are along Y side
To diverse location sentence similar fashion be connected to global bit line (GBL0 to GBLm) and with have selected string 0 when can receive
Cancel the different choice line connection of selection voltage.
Bad block, bad row, bad row
In accumulator system, bad block is detected and marked, so that then not by them for storing user
Data.For example, the detection and mark to bad block can perform during factory testing.Bad block can be the failure to meet with for example reading
Take, write and/or wipe one group of standard (for example, failing to be read out, write or wipe in time restriction), the tool of correlation
Had high error rate or excessive bad element and/or fail the block for meeting other standards.If particular die, which has, is more than threshold value
The bad block of quantity, then it can abandon the nude film.In some cases, the quantity for the bad block that can be included according to nude film come pair
They are classified.Typically, since the data storage capacity of memory is reduced by the quantity of bad block, so with less bad block
Nude film be preferable.
In some cases, block can have some inoperable parts, and miscellaneous part keeps operable.For example, can
It can find that one or more of block row are inoperable, and it can be substituted by spare columns.Similarly, in some cases, may be used
To substitute one or more column of memory cells.A small amount of bad element can be acceptable, and condition is produced by this bad element
Error rate it is low enough to allow to be corrected by error correcting code (ECC) or other certain redundant forms.
In this example, the block for being identified as " bad " block with multiple set of strings that can be selected respectively is further surveyed
Try to whether there is exercisable set of strings in decision block (for example, even if block is as entirety and is unsatisfactory for testing standard, still
Some set of strings may meet the standard).Although some Failure Modes may cause the bad block without operable unit,
It is that other Failure Modes may influence the specific part of block and may leave at least some operable memory cells.Some lose
The single NAND string set that can be selected respectively in block may be influenceed by losing pattern, and other NAND string set keep operable.
The test of block to being identified as " bad " block can identify many pieces of the mixing comprising operable and inoperable part.One
In the case of a little, then this part bad block can be used for data storage, thus increase the capacity of memory.In certain situation
Under, the part for failing to meet testing standard of block can be reconfigured, so that they meet testing standard.Example
Such as, memory fail when using default operation parameters by test it is a part of can use some modified operations
Pass through during parameter.
When failing to wipe a part for block or block, a kind of Failure Mode is likely encountered.Can be during test or at certain
Kind significantly use and to detect this erasing mistake after (for example, after some period of user data is stored using block)
Lose.Generally, after block is subjected to wiping step, shape is wiped free of to judge whether memory cell is in using erasing verification step
Condition, or whether need further to wipe.Although the situation of erasing can be applied to all memory cells of block by wiping step
So that block is wiped free of as overall, but it can will wipe a part of the checking applied to block.For example, it can once select
Select in block NAND string set that can be selected respectively be used for wipe checking.By applying appropriate selection to the selection line of block
Voltage is selected with cancelling, specific NAND string set can be selected, while cancels and selects other NAND string set.Can be to all words
Line applies appropriate erasing verifying voltage, so that connecting all units, this should allow the electric current by NAND string.Can be with
This electric current is measured to determine whether to wipe memory cell.If not by abundant erasing (for example, not in selected NAND string set
With the electric current bigger than minimum circuit) the quantity of NAND string be more than maximum allowable quantity, then can perform another erasing
Step, followed by another erasing verification step.Generally, erasing step and erasing verification step are repeated, it is maximum until reaching
Untill the circulation of time or maximum quantity.When reaching this maximum, erasing failure may be reported, and can be by NAND string
Set is considered as bad (and in some cases, block can be considered as into bad block).
In some cases, because even failing to wipe (holding is programmed) memory list after multiple erasing circulations
Member, so erasing failure occurs.In other cases, erasing failure may occur due to other reasonses.Even if fully erasing
Memory cell, NAND string may also can not by wiping verification step.For example, by the electric current of NAND string may due to except
Some part of notable contribution made to the resistance of NAND string beyond memory cell and keeps very low, the resistance makes to pass through
The electric current of NAND string keeps below minimum current.For example, in some cases, selection transistor can contribute notable resistance.
Under certain situation, the connection in the end of NAND string may contribute notable resistance.For example, it is connected to common-source in NAND string
Or be connected to the place of global bit line and there may be bad connection, the bad connection can provide the electricity reduced by NAND string
The relative high resistance of stream.
Figure 11 A illustrate a part for the 3D NAND string blocks of the NAND string set including that can select respectively.Hard contact
(for example, contact 150) extends between drain electrode selection transistor (selection gate " SG ") and global bit line (" GBL ").At some
In the case of, these contacts for example can have the resistance higher than normal condition due to process associated change, and this may cause
Pass through the more low current of corresponding NAND string.
Figure 11 B shows Figure 11 A independent NAND string, the individually NAND string include itself and corresponding global bit line
The connection of (" GBL ") and its connected by underlying substrate with by the source electrode of vertical conductor, or by the source electrode line in substrate
The local interlinkage (" LI ") being connected with the source terminal of memory.Resistance at any point along shown current path
The low current by NAND string may be caused.For example, global bit line (GBL) NAND is connected at contact 150 in NAND string
At string top, the source region in the source region that NAND string is connected in substrate or substrate is connected with vertical common-source
(LI) resistance at the NAND string bottom of connection.Resistance is also possible to by defective selection transistor (or drain selection crystal
Pipe or drain electrode selection transistor) or the generation of defective dummy unit.The resistance of increase can be specific to independent NAND string, example
Such as, the resistance caused by the bad connection between NAND string and global bit line.The resistance of increase is for multiple NAND strings
It is probably common, for example, caused by the bad connection between the source region in substrate connects with vertical common-source
Resistance may influence the NAND string set that can entirely select respectively.
Figure 12 illustrates the example in the memory hole (" MH ") in the common-source region 154 being connected in substrate.Electric current stream
The vertical local interlinkage (" LI ") formed in source terminal (" ST ") by N+ doped regions (common-source region 154) is crossed,
And flow through the raceway groove of the vertical nand string formed in memory hole.By giving the electric current in memory hole by selection transistor
(for example, shown drain selection transistor 156) controls.Dummy word lines (" DWL ") pair and the memory for storing user data
The virtual memory unit that unit is connected in series is controlled.
Low level line current
Four NAND string set (string 0 to string 3) that can be selected respectively that Figure 13 schematically illustrates block.For reclaiming this
The example of the operation of the bad part of kind block can once be directed to a NAND string set, and can be by different solution applications
In different NAND string set.For example, when failing to wipe block (for example, erasing checking instruction can not more than having for maximum quantity
Receive the NAND string quantity of low electric current), then it can investigate this low current by individually testing NAND string set
Reason.During this test, by applying appropriate choosing while other selection lines of same block receive and cancel selection voltage
Line voltage is selected to select set of strings.It can be wiped free of by being wordline read to judge whether memory cell is in
State.When the electric current by NAND string is very low, and erase all or substantially all memory lists in memory cell
When first, this is indicated generally at low current and caused by another element (such as resistance of another part).By identifying this electricity
Resistance, can identify and apply appropriate solution, so that reclaiming NAND string and then using it for storing number
According to.
In some cases, the low current by NAND string can be overcome by applying more high bit line voltage.Giving tacit consent to
When bit-line voltage fails to generate required electric current due to some resistance, according to equation V=IR, the bit-line voltage of increase may be enough
Electric current needed for offer.Therefore, the global bit line application that a solution can be included to the NAND string with low current is higher
Bit-line voltage.Relatively small amount (for example, being less than number of thresholds) NAND string in the NAND string set that can be selected respectively has
In the case of low current, this point can be completed on the basis of line by turn.In some accumulator systems, bit line is grouped into
Row, wherein, wherein, row can include such as 8,16,32 or more bit lines.It can apply on a column-by-column basis higher
Bit-line voltage.Relatively large amount NAND string (for example, being more than number of thresholds) in the NAND string set that can be selected respectively has
Under the certain situation of low current, then it can apply the bit-line voltage of increase to all NAND strings in NAND string set.It can protect
Hold for indicating to access the record of the modified bit-line voltage applied during the NAND string set that can be selected respectively.It can pass through
Wear this set and use the bit-line voltage of single increase, or the bit-line voltage of different increases can be used for different lines or use
In independent NAND string, it is for instance possible to obtain the set of different bit line voltage shifts is to adjust different bit-line voltages so as to provide
Sufficient current.Record can be with the NAND string set that can be selected respectively single entry or can with arrange (row can
With including multiple bit lines) entry or can have the independent entry of the bit line of voltage for needing to increase.Entry can refer to
Show an entry of the bit-line voltage of increase, or can be the bigger entry of the amplitude of the bit-line voltage of instruction increase.
Figure 14 A and Figure 14 B show the example of the circuit of the other parts for testing NAND string or memory array.When
When memory cell in the NAND string set that can be selected respectively is read and is confirmed as being wiped free of, this circuit can be used for surveying
Measure electric current and the increase of the sufficient current by other of NAND string or memory array unit can be provided for identifying
Bit-line voltage.The resistance 401 shown in this circuit diagram is unit under test and can include (the storage of one or more NAND strings
Device unit is connected) together with the part being connected in series with NAND string.Digital analog converter (DAC) (shows being connected to fixed voltage herein
In example, 2 volts) the grid of transistor be controlled to control the electric current by NAND string.Comparator 405 is by input node
Voltage at 403 is compared with predetermined voltage (in Figure 14 A example, 0.5*VCCQ or 1 volt).If at input node
Voltage more than one volt, then be less than by the electric current of NAND string by/failure border.By to applying to input node 403
Voltage modify and (pass through transistor), it can be found that providing the appropriate voltage by the sufficient current of NAND string.It can lead to
Cross and the voltage of input node is found when applying fixed current to obtain the resistance of NAND string, so that applying appropriate electricity
Press to generate required electric current.For example, NAND string can have the resistance of 5 hundred to one hundred kilohms (500k Ω to 1M Ω).More
High-resistance NAND string can receive the bit-line voltage for being increased to compensate to the resistance of increase (that is, for giving R
Value, according to I=V/R, some V value can produce sufficient current).
Test can be performed at different conditions, and can be by test result with including the electric current under various different conditions
Various standards be compared.For example, as shown in Figure 14 B, low-power test can apply relative low current, so as to
So that the expection voltage at input node is correspondingly smaller, and comparator voltage reduction (in this example, is decreased to
0.25VCCQ or 0.5 volt).Test different condition can allow more accurately to use bit line voltage shift.For example, bit-line voltage
Skew can be used for certain operations rather than for other operation.For example, bit line voltage shift can be used for being wiped (relatively
High current) but may not be usable for being read out (with respect to low current).Can be according to the electric current used when accessing memory (i.e.,
For wipe, read and the electric current of write operation) apply appropriate testing scheme.
In some cases, the increase resistance (for example, NAND string resistance) of unit may be caused by selection transistor.It is logical
Often, because all NAND strings in the NAND string set that can be selected respectively are shared by selection line, selection line problem may shadow
The most or all of NAND string for the NAND string set that sound can select respectively.In this example, to showing with low current (high electricity
Resistance) the NAND string set of a large amount of NAND strings be tested to check whether higher selection line voltage can overcome problem.
The selection line voltage of increase can be tested to check whether the quantity of high resistance NAND string can be decreased to be subjected to
Quantity.If the selection line voltage of increase substantially reduces the quantity of high resistance NAND string, this instruction selection transistor is electricity
The substantive reason of resistance.Then, the selection line voltage of increase can be used at least one selection line by the access to NAND string set.
The NAND string set that can keep selecting respectively for indicating this needs the selection line voltage increased and subsequent access is grasped
Making can be correspondingly using the record of the selection line voltage increased.In some cases, the selection line voltage of single increase can be with
For any NAND string set that can be selected respectively that can be fixed in this way.In other cases, can be tied according to test
Fruit and will selection line voltage increase not same amount.It may be preferred that lower selection line voltage is used in the conceived case, from
And allow to apply a series of choosings according to seriousness the problem of running into the NAND string set that can be selected respectively in difference
Select line voltage.
In some cases, can be by combination (for example, selection line voltage and increase position by applying increase
Line voltage) reclaim a part for block.It will be appreciated that these modes not exclusively and can be with any effective side
Formula (including by being combined with other modes) is applied.
Block it is a part of it is doubtful be to a certain extent some defective examples, can take additional steps to protect
Protect the data stored in this part.For example, more highly redundant level can be applied to this in addition to other parts
The data stored in part.Can be using the default code scheme with certain error correcting capability come the storage that is encoded to data
Device system can be using the enhanced encoding scheme with higher error correcting capability come to entering to be stored in the data in suspicious region
Row coding.For example, can by the first error correcting code (ECC) scheme by default scheme and applied to storing in memory arrays
Data, and the second ECC scheme that can will have more highly redundant rate (and therefore, bigger error correcting capability) is applied to suspicious
The data stored in region.In some cases, additional redundancy scheme can be applied to the data stored in suspicious portion.
For example, in addition to giving tacit consent to ECC scheme, another redundancy scheme can be added to specific data division.This additional aspects
Example be applied to number of data portions and allow recalculated from other parts and redundant data the part it
One exclusiveness OR (XOR) scheme.The redundancy rate of increase is probably enhanced redundancy scheme or is selectively used for suspicious area
The result of the additional redundancy scheme of data in domain.
Region can be considered as suspicious, and the data stored in this region may be subjected to attached due to many reasons
Add measurement.(the ratio in the case where a part (such as the NAND string set that can be selected respectively) for block fails to meet some standards
Such as, there are a large amount of low current NAND strings), the part can be considered as suspicious.The selection higher than normal conditions can be used
Line voltage and/or can apply the bit-line voltage higher than normal conditions and/or can by higher redundancy rate be applied to deposited
The data of storage.Can keep indicating block which should partly have using the redundancy rate of increase the table of data that encodes.
, can be by this table with indicating (such as the selection of the bit-line voltage of increase and/or increase of other operating parameters under certain situation
Line voltage) table pack.When block includes suspicious portion, access time may increase (for example, due to additional code and configuration when
Between), and loss of data risk may be higher.Therefore, can be using this piece as only making when in the absence of available good blocks
Spare block and safeguard.Therefore, after using all good blocks, user data can be only stored in this piece, so as to
So that performance is unaffected.
Figure 15 illustrates the part of inspection three dimensional NAND block and the correspondingly example of some schemes for safeguarding step of application.
For in the internuncial auditing routine in memory hole, carrying out checking to ensure that they are fully wiped it to memory cell
Afterwards the electric conductivity 501 in memory hole is checked by measuring the electric conductivity 503 in memory hole (" MH ").If memory hole has
Low current (high resistance), then confirm memory hole problem 505, and initiate finger and safeguard 507 (term " finger " can be applied to as one
The NAND string set that can be selected respectively that group finger equally extends parallel to).In another auditing routine, selection gate is determined
Threshold voltage (VT) distribution 511, and by its compared with target threshold voltage range 513 to identify problem.It is alternative
Ground, the logic 1 and the quantity of logical zero position read can be counted (for example, by direct memory counter " DMC ")
To identify problematic selection transistor.If the quantity of bad string (is carried with the threshold voltage outside expected range
The string of selection gate) be not more than threshold value 515, then the part of block can be considered as normal and can be come using default operation parameters
Operate on it 517.If the quantity of bad string exceedes number of thresholds 515, the NAND string collection that can respectively select this
Conjunction is considered as suspicious and can be by it 519 compared with the suspicious aggregate list that pending finger is safeguarded.If finger does not exist
In list, then add it to 521 in list.During finger safeguards 507, the one of the set of strings that can be selected respectively can be calculated
Individual or multiple modified operating parameters, such as, the bit-line voltage of increase, the selection line voltage of increase, the redundancy rate that increases or
Other specification.
Then, when accessing finger, make on access whether be programming operation determination 525.If it is programming behaviour
Make, then 527 be adjusted to the condition for being programmed wordline (WL), for example, by increase one or more selection line voltages and/or
Increase one or more bit-line voltages and/or more highly redundant rate is applied to stored data and (added by being provided in finger
Parity data 531).
If the operation is not programming operation, make on its whether based on machine-readable extract operation determination 535.If
It is main frame read operation, then can be adjusted 537 to selection gate (SG) voltage and/or bit line (BL) voltage to perform
Read.Adjustment can be indicated by record entry.After reading data and returning it to main frame, data can be repositioned
539 to safer position (for example, not needing the finger of adjusted voltage).
If operation be not programming or host write operation, make on its whether be erasing operation determination 545.Such as
It is erasing operation to fruit, then can be adjusted 547 to selection gate (SG) voltage and/or bit line (BL) voltage.Adjustment can be by
Record entry instruction.Then, erasing operation 549 is carried out using adjusted voltage.
If operation is not programming, main frame write-in or erasing operation, perform the health of finger is measured (for example,
Quantity with the horizontal unit of same disturbance is measured) and the reading that interference volume can be measured clean operation
555.Modified parameter (such as selection line voltage and bit-line voltage) can be used to be cleaned to perform to read.By data again
557 are positioned to another position (correcting any mistake in data using ECC).
Figure 16 shows the example of the part for being connected to main frame 80 of accumulator system 601.Accumulator system 601 includes depositing
Memory controller 603 and memory die 605 (and annex memory nude film).Memory die 605 can be independent including many
The memory block (for example, 3D nand flash memories block) of erasing.Each block has the part that can be selected respectively (for example, NAND string collection
Close).Some blocks are identified as bad block (" bad ") and are not used.Some blocks have be unsatisfactory at least one of some standards can
(for example, block 607 includes four NAND string set that can be selected respectively, go here and there the part (for example, NAND string set) selected respectively
609 fail to meet some standards).Memory die 605 also includes bit line driver 611, and institute's bit line driver can be configured to
For applying different bit-line voltages (for example, applying in reference string 609 when accessing the NAND string set that difference can select respectively
More high bit line voltage).Bit line sensing element 613 is configured for readout bit line electric current and enters bit line current and threshold current
Row compares.Selection line sensing element 615 is configured for reading selection line threshold voltage and is used for itself and minimum threshold
Voltage is compared.Memory Controller 603 includes to control with reference to the peripheral circuit in memory die 605 to storage
Programmed circuit 617, reading circuit 619 and the erasing circuit 621 of the access of device nude film 605.Bit-line voltage (VBL) adjustment unit
623 are configured for applying not corresponding lines electricity to the NAND string set (with reference to bit line driver 611) that difference can select respectively
Pressure.Bit-line voltage adjustment unit 623 communicates with bit-line voltage table 625, and institute's bitline voltage token record will can divide accessing difference
The bit-line voltage (or skew) used during the NAND string not selected.Selection gate voltage (VSG) adjustment unit 627 is configured to use
Peripheral circuit in reference to memory die 605 and NAND string set that the difference into block can select respectively apply different choosings
Select line voltage (for example, applying more high selection line voltage to the string 609 in addition to other strings of block 607).Selection gate voltage
Adjustment unit 627 communicates with selection gate voltmeter 629, and the selection gate voltmeter records the selection gate of different set of strings
Voltage (or skew).Self-adaptive redundant unit 631 is configured for for different redundancy rates being applied to the difference in memory block
The data stored in region are (for example, more highly redundant rate is applied in the NAND string collection in addition to other set in block 607
Close the data stored in 609).Self-adaptive redundant unit can include the ECC Engine with variable redundancy.Self-adaptive redundant unit
It can include being used for the different parts (for example, ECC Engine and XOR circuit) using different schemes.Self-adaptive redundant unit 631 with
Redundancy table 633 communicates, and the redundancy token record is ready to use in the redundancy rate of the data stored in the different piece of block.
Figure 17 shows the set of strings (string 0 to string 3) that can be selected respectively including sharing source electrode connection (local interlinkage)
Another example of 3D nand memories.Because set of strings and local interlinkage are at different distances, in each set of strings
Series resistance at source side is different.For example, series resistance when series resistance during reference string 0 is more than reference string 3.
In the case of these significant differences, certain adjustment to access voltage (reading voltage, write-in voltage and erasing voltage) is probably
Appropriate.For example, some voltages during reference string 0 are higher when may be than reference string 3, to compensate the series resistance of increase.
In addition to the change of each string, it is understood that there may be other changes (such as this change) of nand memory.For example,
In this example, the raceway groove of NAND string is formed in memory hole, and the diameter in this memory hole is typically due to etchingization
Learn and reduce as depth increases.Therefore, the letter as the height above substrate is there may be between memory cell
Several predictable difference.In some cases, this species diversity can be detected and can be made according to memory bore dia
Certain adjustment.Measurement and adjustment be not limited to set of strings or any other unit and can apply to except three dimensional NAND flash memory with
Outer various memories.
Resistance-type memory and other memories
In addition to nand flash memory, various other memories can include the part that can be selected respectively in block, and can
To have benefited from structure and technology described herein.Referring initially to Figure 18, with the equivalent electric of a part for three-dimensional storage 10
The form on road illustrates schematically and generally the framework of this memory.This is the particular example of cubical array.Standard
Three-dimensional rectangular coordinate system 11 is used as referring to, and two vectors in each vectorial direction and other in vector x, y and z are orthogonal.
For the circuit that internal storage element is connected with external data circuit optionally can be formed at into semiconductor
In substrate 13.In this particular example, selection or switching equipment Qxy two-dimensional array are make use of, wherein, x gives equipment in x
Relative position and y on direction give its relative position in y-direction.As an example, individually equipment Qxy can be
Selection gate or selection transistor.Global bit line (GBLx) extends and had in the x direction by subscript instruction in y-direction
Relative position.Although during reading and generally also during programming, one be connected with specific global bit line is once only turned on
Individual selection equipment, but global bit line (GBLx) can be with having the selection equipment Q of same position source electrode or leakage in the x direction
Extremely individually connection.Individually one of the other of selection equipment Q source electrode or drain electrode and local bitline (LBLxy) are connected.It is local
Bit line vertically extends in a z-direction, and the formation rule array on x (OK) and y (row) direction.
In order to which one group of local bitline (in this example, being designated as a line) is connected with corresponding global bit line, control gate
Polar curve SGy extends and with having the control terminal of the single selection equipment Qxy rows of common location in y-direction in the x direction
(grid) connects.Therefore, which bar control gate polar curve in control gate polar curve SGy, which receives, connects connected selection equipment
Logical voltage, equipment Qxy is selected once by a line local bitline (LBLxy) (in y-direction with same position) on x directions
The corresponding global bit line being connected in global bit line (GBLx).Remaining control gate polar curve, which receives, makes its connection selection equipment keep disconnected
The voltage opened.It is pointed out that due to only one selection equipment (Qxy) and every local position in local bitline (LBLxy)
Line is used together, it is possible to and make spacing of the array on both x directions and y directions on a semiconductor substrate very small, with
And therefore make the density of memory storage element very big.
Memory storage element Mzxy is formed in multiple planes, with different distances on the z directions above substrate 13
To position the multiple plane.Two planes 1 and 2 are illustrated in figure 18, but there typically will be more, such as, 4,6
It is or even more more.In each plane at distance z, wordline WLzy extends and in y-direction in local bitline in the x direction
(LBLxy) it is spaced apart between.The wordline WLzy of each plane is individually across in the local bitline LBLxy on the either side of wordline
Adjacent two local bitlines.Single memory storage element Mzxy is connected to an office adjacent with these single crosspoints
Between bit line LBLxy and a wordline WLzy.Therefore, single memory component Mzxy can be by being placed in office by appropriate voltage
Addressed on bit line LBLxy and wordline WLzy (memory component is connected between it).Voltage is chosen to provide
The state for making memory component is changed to be necessary electro photoluminescence for desired new state from standing state.These voltages
Horizontal, duration and other characteristics depend on the material for memory component.
Each " plane " of three-dimensional memory cell structure is generally formed by least two layers, and conductive word lines WLzy is positioned
One of which layer and another layer that plane is electrically isolated from one being made up of dielectric material.Such as according to storage element
Part Mzxy structure, extra play is there is likely to be in each plane.Plane is stacked in top of each other, office on a semiconductor substrate
The memory component Mzxy for each plane that bit line LBLxy extends through with local bitline is connected.
Figure 19 shows the embodiment of three-dimensional storage with sectional view, and the three-dimensional storage is deposited including having between it
The local bitline and wordline of memory element.This example is configured to when depositing first time using non-conductive non-volatile memories
Device (NVM) material.Metal oxide or other suitable materials may have this characteristic.Can be in response to being placed on those electrodes
Appropriate voltage and form electrically conductive filament between electrode on the opposite side of material.These electrodes are bit line and word in array
Line.Because material is otherwise non-conductive, but need not be by the memory component of wordline and the intersection of bit line
It is isolated from each other.Many memory components can be implemented by single continuous layer of material, in the case of Figure 19, the single continuous material
Layer is NVM materials that are being vertically oriented in y-direction along the opposite side of vertical bit lines and extending up through all planes
Material strip.The remarkable advantage of Figure 19 structure is that all wordline and insulation strip in one group of plane under the wordline can be with
Limited simultaneously by using single mask, thus largely simplify manufacturing process.
Reference picture 19, show the sub-fraction in four planes 101,103,105 and 107 of cubical array.It is described flat
All planes in face have grid, dielectric and memory storage element (NVM) material of identical horizontal pattern.Each
In plane, metal word lines (WL) extend and are spaced apart in y-direction in the x direction.Each plane is included its wordline and its
Under plane (in the case of plane 101, substrate circuitry part under it) wordline isolation insulation dielectric
Layer.Many metal local bitlines (LBL) " post " extend on vertical z directions and formation rule array in x-y direction
Extend through each plane.
Each bit line post is driven by its grid formed in the substrate by the selection grid polar curve (SG) extended in the x direction
Selection equipment (Qxy) to be connected to extend in y-direction in silicon substrate one group of global bit line every identical spacing with intercolumniation
One of (GBL), the selection grid polar curve is similarly formed in substrate.Switching equipment Qxy can be conventional CMOS transistor (or
Vertical n pn transistors) and can use with being made for forming the technique identical technique of other custom circuit systems.
In the case of using npn transistor rather than MOS transistor, substituted using the substrate contact electrode wires extended in the x direction
Selection gate (SG) line.The still sense amplifier not shown in Figure 19, input-output (I/O) electricity have also been made in the substrate
Road system, control circuit system and any other necessary peripheral circuit system.
In the x direction for each local bitline post row, a selection grid polar curve (SG) be present, and for every individually
Local bitline (LBL), exist one selection equipment (Q).Thus, for example, SG3 is control selections equipment Q13、Q23And along
The selection grid polar curve of the additional selection equipment (not shown) in x directions.Local bitline LBL13、LBL23And adding along x directions
Bit line (not shown) and be connected to these local bitlines memory component formed memory the part that can be selected respectively.
In some cases, the parts that can select respectively of difference of memory, which can have, to be found by performing a certain test
Different qualities.For example, it can be seen that, global bit line extends in y-direction, so that the series electrical of global bit line in Figure 19
Resistance increases with the increase of the distance with global bit line driver along y directions.Therefore, can be selected respectively when access difference
During part, different series resistances are observed that due to the different length of the global bit line for accessing corresponding part.If
This series resistance exceedes limitation, then can change operating parameter.For example, one or more applied to global bit line can be increased
Individual voltage is to compensate the voltage drop along global bit line.Compared to closer to and can be selected respectively with smaller global bit line resistance
The part selected, bit line driver are configured for farther and can select respectively with higher global bit line resistance
Transmit higher voltage in the part selected.
Each vertical non-volatile memory device (NVM) material strips are interposed in vertical local bit line (LBL) and in institute
Have between a plurality of wordline (WL) of vertical stacking in plane.Preferably, NVM be present between local bitline (LBL) in the x direction
Material.Memory storage element (M) is positioned in each intersection of wordline (WL) and local bitline (LBL).In memory
In the case that memory element (M) is resistive element, the small NVM materials between intersecting local bitline (LBL) and wordline (WL)
Material region can between conductive (setting) state and non-conductive (replacement) state by the appropriate voltage that applies to intersecting lens and
Controllably replace.
It there is likely to be the parasitic NVM elements formed between the dielectric between LBL and plane.Compared with NVM
The thickness of material layer and be very big by the selection of the thickness (that is, the interval between local bitline and wordline) of dielectric strips, can make by
Field caused by different voltages between wordline in same vertical word line stacks is sufficiently small, so that parasitic antenna never conducts
A large amount of electric currents.Similarly, in other embodiments, it is non-if the operating voltage between adjacent LBL keeps below programming thresholds
Conductive NVM materials can be in the left side between adjacent local bitline in position.
Various materials can be used as NVM materials.For forming resistance-type memory element (for example, for forming Figure 19
Array in memory component Mzxy) material can be chalkogenide, metal oxide or in response to applying to material
External voltage shows any one of many materials that stable reversible resistance is offset material by the electric current of material.
Although there has been described particular example, it is to be understood that any suitable material can be used.
Metal oxide is to be characterizing for insulation when initially depositing.A kind of appropriate metal oxide is titanyl
Thing (TiOx).In Figure 20 example, docking near-stoichiometric TiO2 block of material is changed so as to the bottom of in annealing process
Portion's electrode nearby creates anoxic layer (or oxygen vacancy layer).Top platinum electrode with its high work function creates the height electricity for electronics
Position Pt/TiO2 barrier layers.Therefore, under medium voltate (being less than one volt), low-down electric current will flow through the structure.Bottom
Pt/TiO2-x barrier layers are reduced by the presence of oxygen vacancy (O+2) and show as low resistance contact (Ohmic contact).It is (known
Oxygen vacancy in TiO2 serves as the n-type dopant of the insulation oxide in conversion conductiving doping semiconductor.) caused by composite junction
Structure is in non-conductive (high resistance) state.
But when applying big negative voltage (such as 1.5 volts) at structure both ends, oxygen vacancy is drifted about towards top electrodes,
And therefore, potential barrier Pt/TiO2 reduces and relatively high electric current can flow through the structure.Then, equipment is in
Low resistance (conduction) state.The experiment that other people report has shown that and sent out in the TiO2 regions (may be along crystal boundary) as long filament
It is raw conductive.
By applying big positive voltage at Figure 20 structure both ends to destroy conductive path.Under this positive bias, oxygen is empty
Lack and move away from top Pt/TiO2 barrier layers nearby and " destruction " long filament.Equipment returns to its high resistance state.Conduction state
It is both non-volatile with non-conductive state.Memory storage element is read by applying about 0.5 volt of voltage
Conduction can readily determine that the state of memory component.
Although this particular conductivity mechanism may not be suitable for all metal oxides, as overall, the metal
Oxide has similar behavior：When an appropriate voltage is applied, the transformation from low conduction state to highly conductive state occurs, and
Both states are non-volatile.The example of other materials include HfOx, ZrOx, WOx, NiOx, CoOx, CoalOx, MnOx,
ZnMn2O4、ZnOx、TaOx、NbOx、HfSiOx、HfAlOx.Appropriate top electrodes include have contacted with metal oxide with
Just the oxygen absorbent ability of oxygen vacancy is created at contact has high work function (generally>Metal 4.5eV).Some examples are
TaCN, TiCN, Ru, RuO, Pt, rich Ti TiOx, TiAlN, TaAlN, TiSiN, TaSiN, IrO2.For the appropriate of bottom electrode
Material is any conductive oxygen-rich material, such as, Ti (O) N, Ta (O) N, TiN and TaN.The thickness of electrode is usually 1nm or bigger.
The thickness of metal oxide is generally in the range of 5nm to 50nm.
The another kind of material for being adapted to memory storage element is solid electrolyte, but because they are conductive in deposition
, so needing to form single memory component and being isolated from each other.Solid electrolyte is somewhat similarly to metal oxide,
And conductive mechanism is assumed to be the construction of the metal filament between top electrodes and bottom electrode.In this structure, pass through by
Ion from an electrode (solid electrolyte) dissolves into the main body (oxidizable electrode) of unit to form long filament.Show at one
In example, solid electrolyte includes silver ion or copper ion, and preferably, oxidizable electrode is to be embedded into such as Ax (MB2) 1-x
Metal in transient metal sulfide or selenide material, wherein, A is Ag or Cu, B are S or Se, and M is such as Ta, V or Ti
Deng transition metal, and x scope is from about 0.1 to about 0.7.This composition makes undesired material oxidation into solid electrolytic
Matter minimizes.One example of this composition is Agx (TaS2) 1-x.Alternative composition material includes α-AgI.Another electrode
(indifferent electrode or neutral electrode) should be good electric conductor, while maintain insolubility in solid electrolyte material.Example includes
Metal and compound, such as, W, Ni, Mo, Pt, metal silicide etc..
The example of solid electrolyte material is TaO, GeSe or GeS.It is suitable as the other systems of solid electrolyte cells
For：Cu/TaO/W, Ag/GeSe/W, Cu/GeSe/W, Cu/GeS/W and Ag/GeS/W, wherein, the first material is oxidable electricity
Pole, intermediate materials are solid electrolytes, and the third material is unrelated (neutrality) electrode.The typical thickness of solid electrolyte exists
Between 30nm and 100nm.
In recent years, widely studied using carbon as nonvolatile memory material.Deposited as non-volatile
Memory element, carbon is often used in two forms：Conductive (or class graphene carbon) and insulation (or amorphous carbon).Both types
Carbon material difference be carbon chemical bond (so-called sp2 and sp3 hydridization) content.In sp3 configurations, carbon valence electron is maintained at
In strong covalent bond, and therefore, sp3 hydridization is non-conductive.Sp3 configurations account for leading carbon film and are commonly known as tetrahedron without fixed
Shape carbon or DLC.In sp2 configurations, not every carbon valence electron is held in covalent bond.Weak compactness electronics (phi keys)
Contribution is conductive, mainly sp2 is configured as conductive carbon material.Operation to carbon resistive switching nonvolatile memory is based on such one
Kind is true：Sp3 configurations are transformed into sp2 configurations possibly through appropriate electric current (or voltage) pulse is applied to carbon structure.
For example, when applying the high amplitude voltage pulse of very short (1 to 5ns) at material both ends, electric conductivity is changing into material sp2
Sp3 forms (" replacement " state) and greatly reduce.Reasoning, the high local temperature generated by this pulse cause material
It is unordered, and if pulse is very short, then carbon " quenching " arrives amorphous state (sp3 hydridization).On the other hand, when in replacement shape
When under state, application more low-voltage makes a part for material become sp2 forms (" setting " shape within the longer time (~300nsec)
State).Carbon resistance switching non-volatile memory device has as the configuration of capacitor, wherein, top electrodes and bottom electrode are by height
Warm melting point metals (such as W, Pd, Pt and TaN) are made.
It is nonvolatile memory material significantly to have paid close attention to CNT (CNT) application recently.(single wall) carbon is received
The hollow circular cylinder that mitron is made up of carbon, usually thickness is the thin slice of the rolling and self-closing of a carbon atom, and diameter leads to
Normal is 1 to 2nm and length is than its big hundred times.This nanotube can show very high electric conductivity, and make
Go out on the compatible various proposals with production of integrated circuits.Have been proposed " short " CNT being encapsulated in inertia with reference to mixed
Close in material to form CNT construction.CNT can be deposited on silicon using spin coating or spraying, and in use,
CNT has random orientation relative to each other.When applying electric field at this construction both ends, CNT tends to from flexure or from right
Standard, so that the conduction of construction sexually revises.Resistance and the switching mechanism of reverse situation are not well understood from low to high.Picture
The same in other resistance-type switching nonvolatile memories based on carbon, the memory based on CNT has as the structure of capacitor
Type, wherein, top electrodes and bottom electrode are made up of refractory metals such as refractory metals as mentioned above.
The material for being suitable for the still another category of memory storage element is phase-change material.Preferable phase-change material group bag
The chalcogenide glass generally formed by combining GexSbyTez is included, wherein it is preferred to, x=2, y=2 and z=5.Also
It is found that GeSb is useful.Other materials includes AgInSbTe, GeTe, GaSb, BaSbTe, InSbTe and these are substantially first
The various other combinations of element.Thickness is generally in the range of 1nm to 500nm.Generally accepted explanation to switching mechanism is, when
When applying high energy pulse within the very short time to make the region thawing being made up of the material, the material " quenching " arrives nothing
Amorphous condition (it is low conduction state).When applying more low energy pulse within the longer time, so that temperature is maintained at crystallization
When more than temperature but below melt temperature, material crystalline is to form more crystalline phases of high conductivity.Commonly using with heating
Device electrode integrated sublithographic post makes these equipment.The localized areas that undergo phase transformation can be often designed to and step
Transformation or material on edge is corresponding across the region of the groove etched in low thermal conductivity material.Contact electrode can be thick
Spend for any refractory metal from 1nm to 500nm, such as, TiN, W, WN and TaN.
It will be noted that using the electrode on its either side, (it is formed the storage material in most of aforementioned exemplaries
Through especially selecting).(wherein, wordline (WL) and/or local bitline in the embodiment of 3 D memory array herein
(LBL) these electrodes are formed again by the direct contact with storage material), those lines are preferably by described above
Conductive material is made.In at least one memory component electrode that additional conductive segment is used in the two memory component electrodes
Embodiment in, therefore those sections are made up of the material for memory component electrode described above.
Actuation member is typically integrated into controllable resistor type superconducting memory storage element.Actuation member can be transistor or two
Pole pipe.Although the advantages of three-dimensional architecture described herein, is that this actuation member not necessarily, may have
It is expected the particular configuration for including actuation member.Diode can be p-n junction (being not necessarily made up of silicon), metal/insulator/insulation
Body/metal (MIIM) or Schottky type metal/semiconductor contacts, but replace alternately, can be solid electrolyte component.This
The characteristic of the diode of type is：For the correct operation in memory array, it is necessary to will during each address function
Its " on " or "off".Before memory component is addressed to, diode be in high resistance state ("off" state) and
Influence of " protection " resistance-type memory element from interference voltage.In order to access resistance-type memory element, it is necessary to three not
Biconditional operation：A) diode is converted into low resistance from high resistance；B) by applying appropriate voltage at diode both ends or applying logical
The electric current of diode is crossed to be programmed, read or reset to memory component (erasing)；And c) diode is reset
(erasing).In certain embodiments, one or more operations in these operations can be combined in identical step.It can lead to
Cross and diode is reset to realize to the memory component application backward voltage including diode, the application makes diode
Long filament collapses and diode is returned to high resistance state.
For simplicity, above description already has accounted for the most simple feelings being stored in a data value in each unit
Condition：Each unit is either reset or is set and keeps a data.However, the technology not limited to this of the application is simple
Situation.Many values in this value are designed to be able to by using the various values for connecting (ON) resistance and by sense amplifier
Between distinguished, no matter each memory component of what memory component type is configured for long numeric data
It is maintained in multi-level unit (MLC).
Figure 21 A show another view of the ReRAM memories of the memory string including extending in vertical direction, its
In, it can be selected respectively by row select line this serial.More detailed cross section, the figure displaying are shown in Figure 21 B
How part is formed in the memory holes of multiple alternate wordline and dielectric (in this example, SiO2) layer are extended through
Bit line or vertical bit lines (VBL).Because memory hole is etched through multiple layers, the size in memory hole (and therefore
The size of vertical bit lines) change with the height above substrate.In addition, along the series resistance of memory string with serving as a contrast
The increase of height above bottom and increase.The series resistance of layer in this arrangement of Figure 21 B shows to layer.In some memories
In, the threshold value of some parts of memory can be can exceed that along the series resistance of vertical bit lines.For example, in some elevation-over,
Series resistance can exceed that threshold value.Test can be found that the degree that when this thing happens and this thing happens, so as to
Allow to correspondingly adjust operating parameter.For example, when accessing the memory component of higher level, higher bit line electricity can be used
Pressure.Can in the part that can be selected respectively and by partly making adjustment so that test and adjustment be not limited to it is specific
Unit and can be applied according to the change found in specific memory.
Appropriate Adjusted Option can be stored, its mode is whenever the appropriate section of memory array is accessed, to hold
Row adjustment.For example, variation (skew that voltage, write-in voltage, erasing voltage etc. are read with acquiescence) can be stored in bag
In the table for including the entry of the different piece of memory array.This table can be stored in the nonvolatile memory, and can
To be conducted interviews when needed to it.In some instances, adjustment unit is positioned in by memory bus to be connected to one
In the Memory Controller of individual or multiple memory dies.One or more tables, which can record, to be deposited in access block in difference
The variation used during different piece in reservoir nude film.Can be by this token record in the nonvolatile memory and can
To be read out (for example, being loaded into RAM or other memories being readily accessible to) by memory when needed.
In addition to changing the voltage for the part for being used for accessing memory array, other adjustment can be made.For example, storage
The some parts of device can be identified as with higher loss of data risk (for example, due to data retention issue or other ask
Topic).When identifying this part, a certain adjustment can be made to reduce risk of missing.It is it is, for example, possible to use enhanced superfluous
Remaining scheme.Generally, the ECC scheme with more redundancies allows to correct greater amount of mistake and therefore provide lower data to lose
Go wrong danger.However, this enhanced redundancy needs more memory spaces.In the characteristic of the different piece of known as memory device array
In the case of, redundancy can be adapted on the basis of by part, so that based on the risk in given part and in institute
State and sufficient redundancy is provided in part.
It can be made according to the various characteristics of the part including series resistance as described above of memory array
Go out adjustment.This adjustment can be made in a static manner, so that one-time calculation offsets and then in the longevity of product
The skew is used in life.Alternately, can make adjustment in a dynamic fashion, so that the basis during life of product
Need and recalculate skew.For example, it can be updated based on time, write-in-erasing circulation and/or other factors with some intervals
Offset table.Furthermore it is possible to made adjustment according to environmental factor or other factors.
In one example, when being adjusted to operating parameter, it may be considered that temperature.In some memories, storage
Device characteristic changes with temperature, and can correspondingly make a certain adjustment to operating parameter.For example, if temperature exceedes
Threshold value, then it can use different operating parameter (for example, reading voltage, write-in voltage, erasing voltage etc.).Can be to memory array
All parts of row are uniformly applied this adjustment, where it is assumed that all be partially in substantially the same temperature (for example, base
Single temperature survey in memory die or in Memory Controller nude film or other nude films).Alternately, it is repeatedly warm
Degree measurement can allow the different temperatures adjustment for the different piece of memory array.For example, different memory nude film can be with
Temperature sensor with the temperature for providing their corresponding nude films.It is then possible to adjustment is performed on the basis of nude film.
Cross point memory
Although Figure 21 A and Figure 21 B example show horizontally extending storage between vertical bit lines and horizontal wordline
Device element, but other arrangements can be used.For example, during the crosspoint shown in such as Figure 22 A and Figure 22 B arranges, wordline
It is on varying level and horizontally extending with different orientation with both bit lines.In example shown in Figure 22 A, wordline edge
The extension of x directions, and bit line extends along y directions.Therefore, wordline and bit line are orthogonal.Wordline and bit line are arranged to replace
Layer in so that given word line layer is between two bit line layers, and given bit line layer is between two word line layers.
Memory component is connected between wordline and bit line, so that individually memory component is located at the friendship of particular word line and bit line
At crunode.Therefore, memory component is formed in layer, and single memory element layer is between word line layer and bit line layer.
In this example, memory component vertically extends.Memory component may belong to any appropriate type, for example, being retouched as before
Resistance-type memory element, phase-change element, charge storage cell, charge trapping element or other the appropriate storage elements stated
Part.
When the line in being arranged to arrangement gone out as shown in FIG. 22 A etc. applies voltage, some electricity be present along the line
Pressure drop (is indicated) in Figure 22 A by " IR drops ".It will be appreciated that can be by equation：Voltage=electric current × resistance (V=IR) application
In the part of the conductor wires such as such as wordline or bit line, and all this lines have and caused according to distance (for example, from drive circuit
Distance) voltage drop some resistance.Therefore, for the given voltage exported from drive circuit, to the portion of memory
Giving the voltage added may be due to voltage drop and inconsistent.In some instances, this voltage drop can be tested and is incited somebody to action
It quantifies, for example, by measuring series resistance when accessing the different piece of memory array.If voltage drop exceedes threshold value,
Some compensation can then be applied.For example, if memory array is accessed by the line with the series resistance bigger than threshold value
Some parts (for example, because these partial distance drive circuits far), then this can be by testing determine (or can
To be found from the modeling carried out based on design geometry).As response, the operating parameter of this part can be adjusted.Example
Such as, the logical of memory array can be increased compared to the part connected by the line with low series resistance of memory array
Cross the reading voltage, write-in voltage and/or erasing voltage for the part that the line with high series resistance connects.
The appropriate voltage and/or other operating parameters of different piece can be recorded.For example, one or more can be offset
Applied to different piece, and skew can be recorded in table or other interrecord structures., can be with as in exemplified earlier
Made adjustment according to environmental factors such as such as temperature.Can be according to the characteristic of corresponding part and by different redundancy applications in memory
Data in the different piece of element.
Memory as described above can be operated using various methods.Figure 23 is illustrated and institute in Figure 15
The similar example of the example of displaying, wherein, it with the addition of step to address choice transistor operation.In step 301, one is checked
Or multiple selection transistors current drift (for example, by measure memory cell connect in the case of electric current and applied
The known voltage added).Whether make on current drift higher than the determination limited.If drift is not less than limitation, memory
It is considered as good and for example can continues normal operating 305 using default operation parameters.If drift is higher than limitation,
Can then initiate as before on Figure 15 and described in memory maintenance 507.
Conclusion
Previous embodiment is presented for the purpose of explanation and illustration.It is not intended as exhaustive or limitation institute
Attached claims.In view of teachings above, many modifications and variations are all possible.
Claims (22)
1. a kind of three dimensional nonvolatile accumulator system, including：
Three dimensional nonvolatile memory block, the three dimensional nonvolatile memory block include multiple parts that can be selected respectively, single
Only part that can be selected respectively includes the multiple bit lines extended perpendicular to substrate surface；
Sensing element, the sensing element are configured for reading the position of described piece of the multiple part that can be selected respectively
The bit line current and/or voltage of line and for by for the corresponding result of the reading of part that can individually select respectively with joining
Examine and be compared；And
Adjustment unit, the adjustment unit are communicated with the sensing element, and the adjustment unit is configured in response to right
The corresponding result for the part that one or more of described piece the multiple part that can be selected respectively can select respectively and institute
It is one or more in stating the comparison of reference and individually changing described piece of the multiple part that can be selected respectively
The operating parameter of the individual part that can be selected respectively.
2. three dimensional nonvolatile accumulator system as claimed in claim 1, wherein, the three dimensional nonvolatile memory block and
The sensing element is located in memory die, and the adjustment unit is located in controller nude film.
3. three dimensional nonvolatile accumulator system as claimed in claim 1, further comprise in a first direction parallel to institute
The a plurality of global bit line stated substrate surface and extended, wherein, the multiple bit lines are by multiple selection transistors to be connected to
State a plurality of global bit line.
4. three dimensional nonvolatile accumulator system as claimed in claim 3, further comprise being orthogonal to the first direction
Second direction on the selection line that extends parallel to the substrate surface, the selection line is coupled to the multiple selection crystal
Pipe to select the multiple bit lines respectively.
5. three dimensional nonvolatile accumulator system as claimed in claim 1, wherein, single bit line extends through multiple wordline
Single memory component is formed at level and each word line level in the multiple word line level.
6. three dimensional nonvolatile accumulator system as claimed in claim 5, wherein, the memory component is electric charge storage member
Part or charge trapping element.
7. three dimensional nonvolatile accumulator system as claimed in claim 5, wherein, the memory component is resistance-type member
Part.
8. three dimensional nonvolatile accumulator system as claimed in claim 5, wherein, the memory component is phase transition storage
Element.
9. three dimensional nonvolatile accumulator system as claimed in claim 8, wherein, the adjustment unit is configured for ringing
Compare described in Ying Yu and individually change the volume of each part that can be selected respectively in the multiple part that can be selected respectively
Journey voltage and/or selection voltage.
10. three dimensional nonvolatile memory as claimed in claim 1, further comprise the temperature input of the adjustment unit,
And wherein, the adjustment unit is further configured to be used to input in response to the temperature and change operating parameter.
11. a kind of three dimensional nonvolatile memory, including：
A plurality of First Line, square the first height extends a plurality of First Line along a first direction on the surface of a substrate；
A plurality of second line, second height of a plurality of second line above the substrate surface extend along second direction, institute
It is orthogonal with the first direction to state second direction；
Multiple memory components, single memory component from first height First Line extend to it is high described second
Second line of degree；
Sensing element, the sensing element be configured for reading the First Line electric current and/or voltage and for will
The result of the reading is compared with reference；And
Adjustment unit, the adjustment unit are communicated with the sensing element, and the adjustment unit is configured in response to institute
State and compare and change the operating parameter for the memory component for being connected to the First Line.
12. three dimensional nonvolatile memory as claimed in claim 11, wherein, the adjustment unit is configured for responding
The program voltage for the memory component for being connected to the First Line is changed in the comparison.
13. three dimensional nonvolatile memory as claimed in claim 11, wherein, the adjustment unit is configured for responding
The reading voltage for the memory component for being connected to the First Line is changed in the comparison.
14. three dimensional nonvolatile memory as claimed in claim 11, wherein, the multiple memory component is that resistance-type is deposited
Memory element.
15. three dimensional nonvolatile memory as claimed in claim 14, wherein, the multiple memory component is phase change memory
Device element.
16. three dimensional nonvolatile memory as claimed in claim 11, further comprises：Additional First Line, described additional the
Additional height of one line above the substrate surface extends in said first direction；Additional second line, described additional second
Additional height of the line above the substrate surface extends in this second direction；And annex memory element, it is described attached
Memory component is added to extend to additional second line from the additional First Line, and wherein, the adjustment unit is configured
Changed into the respective heights for the memory component according to the multiple different heights being positioned in above the substrate surface
The operating parameter of the memory component.
17. three dimensional nonvolatile memory as claimed in claim 11, further comprise the temperature input of the adjustment unit,
And wherein, the adjustment unit is further configured to be used to input in response to the temperature and change operating parameter.
18. three dimensional nonvolatile memory as claimed in claim 17, wherein, a plurality of First Line, described a plurality of second
Line, the multiple memory component and the sensing element are located in the first nude film；And
The adjustment unit is located in the second nude film, and the input of the adjustment unit is passed by the temperature in second nude film
Sensor generates.
A kind of 19. side operated to the three dimensional nonvolatile memory including multiple parts that can be selected respectively in block
Method, methods described include：
Measurement passes through the electric current of the wire in the part that can be selected respectively；
By the electric current compared with preassigned；
If the electric current is unsatisfactory for the preassigned, one or more variations are calculated；And
Then, to other voltages that described piece other parts that can be selected respectively apply access described piece described in other
While keeping not being adjusted during the part that can be selected respectively, the memory component in the part that can be selected respectively described in access
When, the voltage that the line into the part that can be selected respectively is applied adjusts one or more of variations.
20. method as claimed in claim 19, further comprises：By the one or more of the part that can be selected respectively
Individual variation is recorded in table and then obtained before the part that can be selected respectively described in access from the table described
One or more variations.
21. method as claimed in claim 19, further comprises：By enhanced redundancy scheme be applied to be unsatisfactory for it is described pre-
The data stored in the accurate part that can be selected respectively are calibrated, the enhanced redundancy scheme is provided than being applied to meet described
The error correcting capability of the usual redundancy scheme higher degree of the data stored in the set of strings of preassigned.
22. method as claimed in claim 19, further comprises：Measure the temperature of the three dimensional nonvolatile memory and
Further adjusted according to the measured temperature into the part that can be selected respectively and other can be selected respectively
The voltage that line in part applies.
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|---|---|---|---|
| US15/276,635 US9691473B2 (en) | 2015-09-22 | 2016-09-26 | Adaptive operation of 3D memory |
| US15/276,635 | 2016-09-26 |
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| Publication number | Publication date |
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| CN107871520B (en) | 2019-04-23 |
| DE102017113967A1 (en) | 2018-03-29 |
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