CN107871428B

CN107871428B - Inverter power supply circuit

Info

Publication number: CN107871428B
Application number: CN201711049541.3A
Authority: CN
Inventors: 杜鹏英; 任国海; 江皓; 陈慧; 姚立海
Original assignee: Hangzhou City University
Current assignee: Hangzhou City University
Priority date: 2017-10-31
Filing date: 2017-10-31
Publication date: 2023-06-30
Anticipated expiration: 2037-10-31
Also published as: CN107871428A

Abstract

The present invention relates to an inverter power supply circuit. At present, the teaching of the inverter circuit mostly adopts a conventional inverter circuit, and students can obtain a certain knowledge on the principle of the inverter circuit in experiments, but the teaching cannot be realized for innovative and designed experiments. The invention comprises a main circuit, an output filter circuit, a driving circuit, an SPWM generating circuit, a signal amplifying circuit and a main control circuit which are connected in sequence. The invention designs the modular inversion power supply circuit, which can be disassembled, accumulated and controlled flexibly, increases the flexibility and diversity of the inversion circuit teaching and effectively improves the teaching efficiency. The invention greatly improves the teaching effect and excites the study and innovation spirit of students in teaching, and is beneficial to improving the innovation and practice of the students on the new method and new means of the inverter circuit.

Description

Inverter power supply circuit

Technical Field

The invention belongs to the technical field of power supplies, and particularly relates to an inverter power supply circuit.

Background

Currently, inverter circuits are increasingly widely used. In some existing power supplies, a storage battery, a solar battery and the like are all direct current power supplies, and for an alternating current load, the power supplies need to be converted into alternating current for supplying the alternating current to the load; the core circuits in the ac motor speed-regulating frequency converter, induction heating power supply, uninterruptible power supply and other equipment also need to invert the dc power into ac circuits. The inverter circuit is an important part of power electronic equipment and is an important content in power electronic technology teaching. At present, the teaching of the inverter circuit adopts a conventional inverter circuit, emphasizes verification experiments of various principles, and has relatively fixed circuits and driving methods, so that students can know the principles of the inverter circuit to a certain extent in the experiments, but the innovative and design experiments cannot be realized. In order to more clearly embody each part of circuits and working mechanisms of the inverter circuit and simultaneously give consideration to innovation, design and expansibility of the inverter circuit, the invention provides a modularized and modular inverter circuit system architecture, which modularly decomposes the inverter circuit system to clearly show the relation and signal flow direction among each part, and simultaneously utilizes different inverter control methods of adjustment of circuit parameters in a module and different expansibility experiments of software in a controller. The complex inverter circuit system is decomposed in building blocks, so that the deep analysis and research of the local circuit can be performed, and meanwhile, in the working of the circuit system, the analysis and research of different methods of the whole inverter circuit can be performed by utilizing different control methods. The modular, modularized and various regulation and control methods are beneficial to improving the contrast teaching and performance analysis of the inverter circuit, and the effects of 24V output alternating voltage, power frequency output, adjustable power and the like of the inverter circuit can be realized under various methods.

Disclosure of Invention

Aiming at the defects existing in the teaching of the existing inverter circuit and the characteristics of the inverter circuit technology, the invention provides an inverter power circuit with modularized output and building blocks.

The invention comprises a main circuit, an output filter circuit, a driving circuit, an SPWM generating circuit, a signal amplifying circuit and a main control circuit.

The main circuit comprises four NMOS tubes, four diodes, four resistors and five capacitors.

The drain electrode of the first NMOS tube M1, the anode of the first diode D1, one end of the first resistor R1, the drain electrode of the second NMOS tube M2, the anode of the second diode D2 and one end of the second resistor R2 are connected and then connected with one end of the voltage stabilizing capacitor C, and are connected with the anode of the direct current power supply through the fuse F; the cathode of the first diode D1 and the other end of the first resistor R1 are connected with one end of the first capacitor C1, and the cathode of the second diode D2 and the other end of the second resistor R2 are connected with one end of the second capacitor C2; the source electrode of the first NMOS tube M1, the drain electrode of the third NMOS tube M3, the other end of the first capacitor C1, the anode of the third diode D3 and one end of the third resistor R3 are connected and serve as the positive end of the SPWM signal; the source electrode of the second NMOS tube M2, the drain electrode of the fourth NMOS tube M4, the other end of the second capacitor C2, the anode of the fourth diode D4 and one end of the fourth resistor R4 are connected and serve as the negative terminal of the SPWM signal; the cathode of the third diode D3 and the other end of the third resistor R3 are connected with one end of the third capacitor C3, the cathode of the fourth diode D4 and the other end of the fourth resistor R4 are connected with one end of the fourth capacitor C4, the source electrode of the third NMOS tube M3, the other end of the third capacitor C3, the source electrode of the fourth NMOS tube M4 and the other end of the fourth capacitor C4 are connected with the other end of the voltage stabilizing capacitor C, and the negative electrode of the direct current power supply is connected in parallel.

The output filter circuit comprises an inductor, a capacitor, a current transformer, a voltage transformer and four resistors.

The SPWM signal positive end of the main circuit is connected with one end of an inductor L, the other end of the inductor L and one end of a fifth resistor R5 are connected with one end of a fifth capacitor C5, the other end of the fifth resistor R5 is connected with one end of a current transformer T1 input coil, the other end of the current transformer T1 input coil is connected with one end of a sixth resistor R6 and then is used as one end of an alternating current power supply output, the other end of the sixth resistor R6 is connected with one end of a voltage transformer T2 input coil, and the other end of the voltage transformer T2 input coil is connected with the other end of the fifth capacitor C5 and then is connected with the SPWM signal negative end of the main circuit and is used as the other end of the alternating current power supply output; the two ends of the output coil of the current transformer T1 are respectively connected with the two ends of the seventh resistor R7, and the two ends of the output coil of the voltage transformer T2 are respectively connected with the two ends of the eighth resistor R8.

The driving circuit comprises two driving chips, two diodes, four capacitors and ten resistors, wherein the two driving chips adopt IR2184 chips of IR company.

The SD pin of the first driving chip U1 is connected with the VCC pin through a ninth resistor R19 and then connected with the 12V power supply anode, and the COM pin of the first driving chip U1 is connected with the 12V power supply cathode; the HO pin of the first driving chip U1 is connected with one end of a tenth resistor R10, the VS pin of the first driving chip U1 is connected with one end of a seventh capacitor C7, one end of an eleventh resistor R11 and the source electrode of the first NMOS tube M1, and the other end of the tenth resistor R10 is connected with the other end of the eleventh resistor R11 and then connected with the grid electrode of the first NMOS tube M1; the LO pin of the first driving chip U1 is connected with one end of a twelfth resistor R12, and the other end of the twelfth resistor R12 is connected with one end of a thirteenth resistor R13 and then connected with the grid electrode of a third NMOS tube M3; the VB pin of the first driving chip U1 is connected with the other end of the seventh capacitor C7 and the cathode of the fifth diode D5, the anode of the fifth diode D5 is connected with one end of the sixth capacitor C6, the other end of the sixth capacitor C6 is connected with the COM pin of the first driving chip U1, and the other end of the thirteenth resistor R13 is connected with the source electrode of the third NMOS tube M3;

the SD pin of the second driving chip U2 is connected with the VCC pin through a fourteenth resistor R14 and then connected with the 12V power supply anode, and the COM pin of the second driving chip U2 is connected with the 12V power supply cathode; the HO pin of the second driving chip U2 is connected with one end of a fifteenth resistor R15, the VS pin of the second driving chip U2 is connected with one end of a ninth capacitor C9, one end of a sixteenth resistor R16 and the source electrode of a second NMOS tube M2, and the other end of the fifteenth resistor R15 is connected with the other end of the sixteenth resistor R16 and then connected with the grid electrode of the second NMOS tube M2; the LO pin of the second driving chip U2 is connected with one end of a seventeenth resistor R17, and the other end of the seventeenth resistor R17 is connected with one end of an eighteenth resistor R18 and then connected with the grid electrode of a fourth NMOS tube M4; the VB pin of the second driving chip U2 is connected with the other end of the ninth capacitor C9 and the cathode of the sixth diode D6, the anode of the sixth diode D6 is connected with one end of the eighth capacitor C8, the other end of the eighth capacitor C8 is connected with the COM pin of the second driving chip U2, and the other end of the eighth capacitor C8 is connected with the other end of the eighteenth resistor R18 and then connected with the source electrode of the fourth NMOS tube M4.

The SPWM generating circuit comprises four comparison amplifiers, two optocoupler isolators, four diodes, three voltage stabilizing tubes, eight capacitors and seventeen resistors.

The inverting input end of the first comparison amplifier U3 is connected with one end of a tenth capacitor C10 and one end of a nineteenth resistor R19, and the non-inverting input end of the first comparison amplifier U3, the inverting input end of the second comparison amplifier U4, one end of an eleventh capacitor C11, the anode of a seventh diode D7 and the cathode of an eighth diode D8 are grounded after being connected; the output end of the first comparison amplifier U3 is connected with the other end of the tenth capacitor C10, and one ends of a twenty-first resistor R20, a twenty-first resistor R21 and a twenty-second resistor R22, the positive power supply of the first comparison amplifier U3 is connected with a +15V power supply and is grounded through a twelfth capacitor C12, and the negative power supply of the first comparison amplifier U3 is connected with a-15V power supply and is grounded through a thirteenth capacitor C13; the other end of the twenty-fourth resistor R20 and one end of the twenty-third resistor R23 are connected with the non-inverting input end of the second comparison amplifier U4, the output end of the second comparison amplifier U4 is connected with one end of the twenty-fourth resistor R24 and one end of the twenty-fifth resistor R25, the positive power end of the second comparison amplifier U4 and the other end of the twenty-fourth resistor R24 are connected with a +15V power supply and grounded through a fourteenth capacitor C14; the negative power end of the second comparison amplifier U4 is connected with the other end of the eleventh capacitor C11 and then connected with a-15V power supply; the other ends of the nineteenth resistor R19, the twenty third resistor R23 and the twenty fifth resistor R25 are connected with the cathode of the ninth diode D9 and the anode of the twelfth diode D10, one end of the cathode of the twelfth diode D10, the cathode of the seventh diode D7 and one end of the fifteenth capacitor C15 are connected with the cathode of the first voltage stabilizing tube DW1, and the other ends of the anode of the ninth diode D9, the anode of the eighth diode D8 and the fifteenth capacitor C15 are connected with the anode of the first voltage stabilizing tube DW 1; the other end of the twenty-first resistor R21 is connected with one end of a twenty-sixth resistor R26 and then is connected with the inverting input end of the third comparison amplifier U5, the other end of the twenty-second resistor R22 is connected with one end of a twenty-seventh resistor R27 and then is connected with the inverting input end of the fourth comparison amplifier U6, the non-inverting input end of the third comparison amplifier U5 is grounded through a twenty-eighth resistor R28, and the non-inverting input end of the fourth comparison amplifier U6 is grounded through a twenty-ninth resistor R29; the A pin of the first optocoupler isolator U7 is connected with a +15V power supply through a thirty-first resistor R31, the K pin is connected with the output end of the third comparison amplifier U5, the V+ pin is connected with one end of a thirty-first resistor R32 and one end of a sixteenth capacitor C16, the other end of the thirty-second resistor R32 is connected with a +12V power supply, the other end of the thirty-first resistor R31 is connected with the O pin of the first optocoupler isolator U7 and then is connected with the IN pin of the first driving chip U1, and the anode of the second voltage stabilizing tube DW2 and the other end of the sixteenth capacitor C16 are connected with the V pin of the first optocoupler isolator U7 and then connected with 12V ground; the A pin of the second optocoupler isolator U8 is connected with a +15V power supply through a thirty-third resistor R33, the K pin is connected with the output end of the fourth comparison amplifier U6, the V+ pin is connected with one end of a thirty-fourth resistor R34, a thirty-fifth resistor R35 and a seventeenth capacitor C17, the other end of the thirty-fifth resistor R35 is connected with a +12V power supply, the other end of the thirty-fourth resistor R34 is connected with the O pin of the second optocoupler isolator U8 and then connected with the IN pin of the second driving chip U2, and the anode of the third voltage regulator DW3 and the other end of the seventeenth capacitor C17 are connected with the V pin of the second optocoupler isolator U8 and then connected with 12V ground.

The signal amplifying circuit 5 comprises two paths with the same structure, and each path of signal amplifying circuit comprises two operational amplifiers, seven resistors and a capacitor.

One end of a thirty-sixth resistor R36 and one end of a thirty-seventh resistor R37 are connected with the inverting input end of the first operational amplifier U9, the other end of the thirty-sixth resistor R36 is connected with one end of an eighteenth capacitor C18, the output end of the first operational amplifier U9 is connected with the other end of the thirty-seventh resistor R37 and one end of a thirty-eighth resistor R38, the other end of the thirty-eighth resistor R38 and one end of a thirty-ninth resistor R39 are connected with the inverting input end of the second operational amplifier U10, the other end of the thirty-ninth resistor R39 and one end of a forty-fourth resistor R40 are connected with the output end of the second operational amplifier U10, the non-inverting input end of the first operational amplifier U9 is connected with +5V ground through a fortieth resistor R41, and the non-inverting input end of the second operational amplifier U10 is connected with +5V ground through a fortieth resistor R42. The other end of the eighteenth capacitor C18 in the two signal amplifying circuits is respectively connected with two analog output pins of the main control chip U, and the other end of the forty resistor R40 in the two signal amplifying circuits is connected with the other ends of the twenty-sixth resistor R26 and the twenty-seventh resistor R27 in the SPWM generating circuit.

The master control circuit comprises a master control chip U, an optical coupler isolator and a resistor, wherein the master control chip U adopts an STC15W4K48S4 chip of STC company.

The anode end of the light emitting diode of the third optocoupler isolator U11 is connected with a +5V power supply through a forty-third resistor R43, the cathode end of the light emitting diode is connected with an output pin of the main control chip U, two ends of an output coil of a current transformer and a voltage transformer in the output filter circuit are connected with an AD input pin of the main control chip U, the emitting electrode of a triode of the third optocoupler isolator U11 is grounded, and the collecting electrode is connected with SD pins of a first driving chip U1 and a second driving chip U1 in the driving circuit.

The invention designs a modular inversion power supply circuit, which can be decomposed, accumulated and controlled flexibly, and realizes the functions of 24V output alternating voltage, 0-2A adjustable output current, 50Hz +/-0.2 Hz output signal frequency, less than 0.8% total harmonic distortion, closed-loop voltage and current adjustment, multiple driving methods, adjustable power and the like. The modular building blocks are built, signals are added layer by layer, flexibility and diversity of inverter circuit teaching are improved, and teaching efficiency is effectively improved. The invention greatly improves the teaching effect and excites the study and innovation spirit of students in teaching, and is beneficial to improving the innovation and practice of the students on the new method and new means of the inverter circuit.

Drawings

FIG. 1 is a schematic diagram of the structure of the present invention;

FIG. 2 is a circuit diagram of the main circuit of FIG. 1;

FIG. 3 is a circuit diagram of the output filter circuit of FIG. 1;

FIG. 4 is a circuit diagram of the driving circuit of FIG. 1;

FIG. 5 is a circuit diagram of the SPWM generating circuit of FIG. 1;

FIG. 6 is a circuit diagram of the signal amplifying circuit of FIG. 1;

fig. 7 is a circuit diagram of the master circuit of fig. 1.

Detailed Description

As shown in fig. 1, an inverter power supply circuit includes a main circuit 1, an output filter circuit 2, a driving circuit 3, an SPWM generating circuit 4, a signal amplifying circuit 5, and a main control circuit 6.

As shown in fig. 2, the main circuit 1 includes four NMOS transistors, four diodes, four resistors, and five capacitors.

As shown in fig. 3, the output filter circuit 2 includes an inductor, a capacitor, a current transformer, a voltage transformer, and four resistors.

The SPWM signal positive end of the main circuit 1 is connected with one end of an inductor L, the other end of the inductor L and one end of a fifth resistor R5 are connected with one end of a fifth capacitor C5, the other end of the fifth resistor R5 is connected with one end of an input coil of a current transformer T1, the other end of the input coil of the current transformer T1 is connected with one end of a sixth resistor R6 and then is used as one end of an alternating current power supply output, the other end of the sixth resistor R6 is connected with one end of an input coil of a voltage transformer T2, and the other end of the input coil of the voltage transformer T2 is connected with the other end of the fifth capacitor C5 and then is connected with the SPWM signal negative end of the main circuit 1 and is used as the other end of the alternating current power supply output; the two ends of the output coil of the current transformer T1 are respectively connected with the two ends of the seventh resistor R7, and the two ends of the output coil of the voltage transformer T2 are respectively connected with the two ends of the eighth resistor R8.

As shown in fig. 4, the driving circuit 3 includes two driving chips, two diodes, four capacitors, and ten resistors, and the two driving chips are IR2184 chips of IR corporation.

As shown in fig. 5, the SPWM generating circuit 4 includes four comparison amplifiers, two optocoupler isolators, four diodes, three voltage stabilizing tubes, eight capacitors, and seventeen resistors.

The signal amplifying circuit 5 includes two paths having the same structure, and as shown in fig. 6, each path of signal amplifying circuit includes two operational amplifiers, seven resistors and one capacitor.

As shown in fig. 7, the master control circuit 6 includes a master control chip U, an optocoupler isolator and a resistor, where the master control chip U uses STC15W4K48S4 chips of STC company.

Claims

1. The utility model provides an inverter circuit, includes main circuit (1), output filter circuit (2), drive circuit (3), SPWM generating circuit (4), signal amplification circuit (5), main control circuit (6), its characterized in that:

the main circuit (1) comprises four NMOS tubes, four diodes, four resistors and five capacitors;

the drain electrode of the first NMOS tube (M1), the anode of the first diode (D1), one end of the first resistor (R1), the drain electrode of the second NMOS tube (M2), the anode of the second diode (D2) and one end of the second resistor (R2) are connected and then connected with one end of the voltage stabilizing capacitor (C), and the positive electrode of the direct current power supply is connected through the fuse (F); the cathode of the first diode (D1) and the other end of the first resistor (R1) are connected with one end of the first capacitor (C1), and the cathode of the second diode (D2) and the other end of the second resistor (R2) are connected with one end of the second capacitor (C2); the source electrode of the first NMOS tube (M1), the drain electrode of the third NMOS tube (M3), the other end of the first capacitor (C1), the anode of the third diode (D3) and one end of the third resistor (R3) are connected to serve as the positive end of the SPWM signal; the source electrode of the second NMOS tube (M2), the drain electrode of the fourth NMOS tube (M4), the other end of the second capacitor (C2), the anode of the fourth diode (D4) and one end of the fourth resistor (R4) are connected to serve as the negative terminal of the SPWM signal; the cathode of the third diode (D3) and the other end of the third resistor (R3) are connected with one end of a third capacitor (C3), the cathode of the fourth diode (D4) and the other end of the fourth resistor (R4) are connected with one end of a fourth capacitor (C4), the source electrode of the third NMOS tube (M3), the other end of the third capacitor (C3), the source electrode of the fourth NMOS tube (M4) and the other end of the fourth capacitor (C4) are connected and then connected with the other end of a voltage stabilizing capacitor (C), and the negative electrode of a direct current power supply is connected in parallel;

the output filter circuit (2) comprises an inductor, a capacitor, a current transformer, a voltage transformer and four resistors;

the SPWM signal positive end of the main circuit (1) is connected with one end of an inductor (L), the other end of the inductor (L) and one end of a fifth resistor (R5) are connected with one end of a fifth capacitor (C5), the other end of the fifth resistor (R5) is connected with one end of a current transformer (T1) input coil, the other end of the current transformer (T1) input coil is connected with one end of a sixth resistor (R6) and then is used as one end of an alternating current power supply output, the other end of the sixth resistor (R6) is connected with one end of a voltage transformer (T2) input coil, and the other end of the voltage transformer (T2) input coil is connected with the other end of the fifth capacitor (C5) and then is connected with the SPWM signal negative end of the main circuit (1) and is used as the other end of the alternating current power supply output; the two ends of the output coil of the current transformer (T1) are respectively connected with the two ends of the seventh resistor (R7), and the two ends of the output coil of the voltage transformer (T2) are respectively connected with the two ends of the eighth resistor (R8);

the driving circuit (3) comprises two driving chips, two diodes, four capacitors and ten resistors;

the SD pin of the first driving chip (U1) is connected with the VCC pin through a ninth resistor (R9) and then connected with the 12V power supply anode, and the COM pin of the first driving chip (U1) is connected with the 12V power supply cathode; the HO pin of the first driving chip (U1) is connected with one end of a tenth resistor (R10), the VS pin of the first driving chip (U1) is connected with one end of a seventh capacitor (C7), one end of an eleventh resistor (R11) and the source electrode of the first NMOS tube (M1), and the other end of the tenth resistor (R10) is connected with the other end of the eleventh resistor (R11) and then connected with the grid electrode of the first NMOS tube (M1); the LO pin of the first driving chip (U1) is connected with one end of a twelfth resistor (R12), and the other end of the twelfth resistor (R12) is connected with one end of a thirteenth resistor (R13) and then connected with the grid electrode of a third NMOS tube (M3); the VB pin of the first driving chip (U1) is connected with the other end of the seventh capacitor (C7) and the cathode of the fifth diode (D5), the anode of the fifth diode (D5) is connected with one end of the sixth capacitor (C6), the other end of the sixth capacitor (C6) is connected with the COM pin of the first driving chip (U1), and the other end of the thirteenth resistor (R13) is connected with the source electrode of the third NMOS tube (M3);

the SD pin of the second driving chip (U2) is connected with the VCC pin through a fourteenth resistor (R14) and then connected with the 12V power supply anode, and the COM pin of the second driving chip (U2) is connected with the 12V power supply cathode; the HO pin of the second driving chip (U2) is connected with one end of a fifteenth resistor (R15), the VS pin of the second driving chip (U2) is connected with one end of a ninth capacitor (C9), one end of a sixteenth resistor (R16) and the source electrode of a second NMOS tube (M2), and the other end of the fifteenth resistor (R15) is connected with the other end of the sixteenth resistor (R16) and then connected with the grid electrode of the second NMOS tube (M2); the LO pin of the second driving chip (U2) is connected with one end of a seventeenth resistor (R17), and the other end of the seventeenth resistor (R17) is connected with one end of an eighteenth resistor (R18) and then connected with the grid electrode of a fourth NMOS tube (M4); the VB pin of the second driving chip (U2) is connected with the other end of the ninth capacitor (C9) and the cathode of the sixth diode (D6), the anode of the sixth diode (D6) is connected with one end of the eighth capacitor (C8), the other end of the eighth capacitor (C8) is connected with the COM pin of the second driving chip (U2), and the anode of the eighth capacitor (C8) is connected with the other end of the eighteenth resistor (R18) and then connected with the source electrode of the fourth NMOS tube (M4);

the SPWM generating circuit (4) comprises four comparison amplifiers, two optocoupler isolators, four diodes, three voltage stabilizing tubes, eight capacitors and seventeen resistors;

the inverting input end of the first comparison amplifier (U3) is connected with one end of a tenth capacitor (C10) and one end of a nineteenth resistor (R19), the non-inverting input end of the first comparison amplifier (U3), the inverting input end of the second comparison amplifier (U4), one end of an eleventh capacitor (C11), the anode of a seventh diode (D7) and the cathode of an eighth diode (D8) are connected and grounded; the output end of the first comparison amplifier (U3) is connected with the other end of the tenth capacitor (C10), and one end of the twentieth resistor (R20), the twenty-first resistor (R21) and the twenty-second resistor (R22), the positive power supply of the first comparison amplifier (U3) is connected with a +15V power supply and is grounded through the twelfth capacitor (C12), the negative power supply of the first comparison amplifier (U3) is connected with a-15V power supply and is grounded through the thirteenth capacitor (C13); the other end of the twenty-fourth resistor (R20) and one end of the twenty-third resistor (R23) are connected with the non-inverting input end of the second comparison amplifier (U4), the output end of the second comparison amplifier (U4) is connected with one end of the twenty-fourth resistor (R24) and one end of the twenty-fifth resistor (R25), the positive power end of the second comparison amplifier (U4) and the other end of the twenty-fourth resistor (R24) are connected with a +15V power supply and grounded through a fourteenth capacitor (C14); the negative power end of the second comparison amplifier (U4) is connected with the other end of the eleventh capacitor (C11) and then connected with a-15V power supply; the other ends of the nineteenth resistor (R19), the twenty third resistor (R23) and the twenty fifth resistor (R25) are connected with the cathode of the ninth diode (D9) and the anode of the twelfth diode (D10), the cathode of the seventh diode (D7) and one end of the fifteenth capacitor (C15) are connected with the cathode of the first voltage stabilizing tube (DW 1), and the anode of the ninth diode (D9), the anode of the eighth diode (D8) and the other end of the fifteenth capacitor (C15) are connected with the anode of the first voltage stabilizing tube (DW 1); the other end of the twenty-first resistor (R21) is connected with one end of the twenty-sixth resistor (R26) and then is connected with the inverting input end of the third comparison amplifier (U5), the other end of the twenty-second resistor (R22) is connected with one end of the twenty-seventh resistor (R27) and then is connected with the inverting input end of the fourth comparison amplifier (U6), the non-inverting input end of the third comparison amplifier (U5) is grounded through the twenty-eighth resistor (R28), and the non-inverting input end of the fourth comparison amplifier (U6) is grounded through the twenty-ninth resistor (R29); the A pin of the first optocoupler isolator (U7) is connected with a +15V power supply through a thirty-first resistor (R30), the K pin is connected with the output end of the third comparison amplifier (U5), the V+ pin is connected with one ends of a thirty-first resistor (R31), a thirty-second resistor (R32) and a sixteenth capacitor (C16), the other end of the thirty-second resistor (R32) is connected with a +12V power supply, the other end of the thirty-first resistor (R31) is connected with the O pin of the first optocoupler isolator (U7) and then connected with the IN pin of the first driving chip (U1), and the anode of the second voltage stabilizing tube (DW 2) and the other end of the sixteenth capacitor (C16) are connected with the V-pin of the first optocoupler isolator (U7) and then connected with 12V ground; the A pin of the second optocoupler isolator (U8) is connected with a +15V power supply through a thirty-third resistor (R33), the K pin is connected with the output end of a fourth comparison amplifier (U6), the V+ pin is connected with one end of a thirty-fourth resistor (R34), a thirty-fifth resistor (R35) and a seventeenth capacitor (C17), the other end of the thirty-fifth resistor (R35) is connected with a +12V power supply, the other end of the thirty-fourth resistor (R34) is connected with the O pin of the second optocoupler isolator (U8) and then connected with the IN pin of a second driving chip (U2), and the anode of the third voltage regulator tube (DW 3) and the other end of the seventeenth capacitor (C17) are connected with the V-pin of the second optocoupler isolator (U8) and then connected with 12V ground;

the signal amplifying circuit (5) comprises two paths with the same structure, and each path of signal amplifying circuit comprises two operational amplifiers, seven resistors and a capacitor;

one end of a thirty-sixth resistor (R36) and one end of a thirty-seventh resistor (R37) are connected with an inverting input end of a first operational amplifier (U9), the other end of the thirty-sixth resistor (R36) is connected with one end of an eighteenth capacitor (C18), the output end of the first operational amplifier (U9) is connected with the other end of the thirty-seventh resistor (R37) and one end of a thirty-eighth resistor (R38), the other end of the thirty-eighth resistor (R38) and one end of a thirty-ninth resistor (R39) are connected with an inverting input end of a second operational amplifier (U10), the other end of the thirty-ninth resistor (R39) and one end of a fortieth resistor (R40) are connected with an output end of the second operational amplifier (U10), the non-inverting input end of the first operational amplifier (U9) is connected with +5V ground through a fortieth resistor (R41), and the non-inverting input end of the second operational amplifier (U10) is connected with +5V ground through a fortieth resistor (R42); the other end of an eighteenth capacitor (C18) in the two paths of signal amplifying circuits is respectively connected with two analog output pins of a main control chip (U), and the other end of a fortieth resistor (R40) in the two paths of signal amplifying circuits is connected with the other ends of a twenty-sixth resistor (R26) and a twenty-seventh resistor (R27) in the SPWM generating circuit (4);

the main control circuit (6) comprises a main control chip (U), an optical coupler isolator and a resistor;

the anode end of a light emitting diode of the third optocoupler isolator (U11) is connected with a +5V power supply through a forty-three resistor (R43), the cathode end of the light emitting diode is connected with an output pin of the main control chip (U), two ends of an output coil of a current transformer and a voltage transformer in the output filter circuit (2) are connected with an AD input pin of the main control chip (U), the emitting electrode of a triode of the third optocoupler isolator (U11) is grounded, and the collecting electrode is connected with SD pins of a first driving chip (U1) and a second driving chip (U2) in the driving circuit (3).

2. An inverter power circuit as claimed in claim 1 wherein: the master control chip (U) adopts an STC15W4K48S4 chip of STC company; the first driving chip (U1) and the second driving chip (U2) adopt IR2184 chips of IR company.