CN107833586A - Primary particle inversion resistant FPGA triplication redundancies configuration memory cell circuit - Google Patents
Primary particle inversion resistant FPGA triplication redundancies configuration memory cell circuit Download PDFInfo
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- CN107833586A CN107833586A CN201711218764.8A CN201711218764A CN107833586A CN 107833586 A CN107833586 A CN 107833586A CN 201711218764 A CN201711218764 A CN 201711218764A CN 107833586 A CN107833586 A CN 107833586A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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Abstract
Present disclose provides a kind of primary particle inversion resistant FPGA triplication redundancies configuration memory cell circuit, including：Transmission unit, it is connected to input sel and input data；Unit is reset, is connected to input clr；Memory cell is interlocked, including：6 upper metal-oxide-semiconductors and 6 lower metal-oxide-semiconductors, wherein, described 6 upper metal-oxide-semiconductors and 6 lower metal-oxide-semiconductors form 6 grades of interlocking memory cell, are gradually connected in an identical manner per one-level, the 6th grade is connected to the 1st grade；The interlocking memory cell is connected to input sel and input data by the transmission unit, and input clr is connected to by the clearing unit；Include 1 upper metal-oxide-semiconductor and 1 lower metal-oxide-semiconductor, the drain D end connection of the 1 upper metal-oxide-semiconductor and 1 lower metal-oxide-semiconductor per one-level per one-level, and be connected to the grid G end of metal-oxide-semiconductor on next stage, and under upper level metal-oxide-semiconductor grid G end.
Description
Technical field
The invention belongs to technical field of integrated circuits, is related to a kind of triplication redundancy primary particle inversion resistant for FPGA and matches somebody with somebody
Put storage unit circuit.
Background technology
Since the 1970s, with the development of microelectric technique, there are various types of general programmables
Logical device PLD.Wherein, with the FPGA based on SRAM using relatively broad.User can be configured by software to device programming
Memory cell SRAM realizes required logic function, without making application-specific integrated circuit ASIC by oneself design and foundries
Chip.FPGA is a kind of highdensity complicated PLD.It is by many independent programmed logical modules, programmable interconnection and can compile
Journey input/output module forms.Programmable interconnection box is connected through between logic module and between input/output module
To realize.Programmable resource is controlled to realize required logic work(by the way that configuration bit stream to be downloaded to the configuration memory cell in chip
Energy.
FPGA is super large-scale integration VLSI technologies and the result of computer aided design cad technology development fusion.
Application circuit design based on FPGA is not required to again through flow, while the support of functional powerful eda software again.Therefore, with base
Design in asic chip and greatly shortened compared to the research and development of products cycle.And when the amount piece number of needs is little, answering based on FPGA
Also there is the low advantage of cost compared with asic chip designs with circuit design.FPGA these advantages cause it to be widely used in
Computer hardware, data processing, Industry Control, remote-control romote-sensing, intelligence instrument, radio and television, medicine equipment and Aero-Space etc.
Numerous areas.But in some application scenarios, the configuration memory cell SRAM positions state in FPGA is turned over after being easy to coverlet particle radiation
Turn.
In the prior art, the state upset of SRAM positions is caused to solve the problems, such as that above-mentioned single-particle radiates, it is proposed that Yi Zhongti
The method that SRAM single event upset resistant threshold values are configured in high FPGA.Pass through each input of cross coupled inverters pair in sram
The grid oxygen electric capacity that one metal-oxide-semiconductor of insertion is connected between the output end line of end and another reverser, extends and is overturned data through reverse
The time that device is fed back so that feedback time, which is more than, is overturned the data recovery time, so as to improve the upset of SRAM anti-single particles
Threshold value.Also technical staff is connected by each output end of cross coupled inverters pair in sram with another inverter input
A MOS transfer tube for being equivalent to resistance is inserted between line, to extend the time overturned data and fed back through reverser, so as to
Improve SRAM single event upset resistant threshold values.Another method is contracted by increasing metal-oxide-semiconductor grid oxygen electric capacity in SRAM memory nodes
The short method for being overturned the data recovery time, so as to improve SRAM single event upset resistant threshold values.Different from previously by extension quilt
Time that data feed back through reverser or shorten is overturned to be overturned recovery times of data and turn over to improve SRAM anti-single particles
Turn the method for threshold value, also technical staff proposes a kind of dual interlocked storage cell circuit, and it reads and writes equivalent to traditional both ends
Two mould redundant circuits of sram cell, read-write single-ended compared to configuration memory cell in PLD have used 2 MOS
Pipe.
By increasing, the data recovery time is overturned in sensitive node capacitance shortening to the above method or reverser is defeated in sram
Enter to increase on path resistance capacitance and extend to be overturned the time that data feed back through reverser and improve the upset of SRAM anti-single particles
Threshold value.And for the dual interlocked storage cell circuit of two mould redundancy sram cells, 12 metal-oxide-semiconductors of the circuit, need both ends difference to read
Write.Internal configuration storage need to be reset when electric on PLD, it is in the state of determination.Therefore, two mould
The configuration memory cell of redundancy just need to respectively increase by one in two nodes of storage equal state and reset pipe.There is shown herein for
FPGA band resets the triplication redundancy configuration memory cell circuit of the single-ended read-write of pipe, occupies less compared to both ends read-write memory cell
One times of wiring.All need to read and write with ' 1 ' different from memory cell ' 0 ' in document, when electric on the configuration memory cell clearly once
Zero, the dispensing unit that ' 1 ' need to be write when then configuring writes ' 1 ' again；It is also to give tacit consent to ' 1 ' during retaking of a year or grade configuration data, a retaking of a year or grade ' 0 '.
Disclosure
(1) technical problems to be solved
Present disclose provides a kind of primary particle inversion resistant FPGA triplication redundancies configuration memory cell circuit, with least partly
Solves technical problem set forth above.
(2) technical scheme
According to an aspect of this disclosure, there is provided a kind of primary particle inversion resistant FPGA triplication redundancies configuration memory cell
Circuit, including：Transmission unit, including：First transmission metal-oxide-semiconductor 113, second transmits metal-oxide-semiconductor 114 and the 3rd and transmits metal-oxide-semiconductor 115,
The first transmission metal-oxide-semiconductor 113, second, which transmits metal-oxide-semiconductor 114 and the 3rd, to be transmitted metal-oxide-semiconductor 115 and is connected to input sel, and described the
One transmission metal-oxide-semiconductor 113, second transmits the transmission metal-oxide-semiconductor 115 of metal-oxide-semiconductor 114 and the 3rd and is connected to the input data；Reset single
Member, including：First, which resets metal-oxide-semiconductor 116, second, resets the clearing metal-oxide-semiconductor 118 of metal-oxide-semiconductor 117 and the 3rd, and described first resets metal-oxide-semiconductor
116th, the second clearing metal-oxide-semiconductor 117 and the 3rd resets metal-oxide-semiconductor 118 and is connected to input clr；Memory cell is interlocked, including：First
On upper metal-oxide-semiconductor 101, second on metal-oxide-semiconductor the 103, the 3rd on metal-oxide-semiconductor the 105, the 4th on metal-oxide-semiconductor the 107, the 5th on metal-oxide-semiconductor the 109, the 6th
Metal-oxide-semiconductor 111, and first time metal-oxide-semiconductor 102, second time metal-oxide-semiconductor 104, the three times metal-oxide-semiconductors 106, the four times metal-oxide-semiconductors the 108, the 5th
Lower metal-oxide-semiconductor 110, the six times metal-oxide-semiconductors 112；Wherein, metal-oxide-semiconductor on metal-oxide-semiconductor the 103, the 3rd on metal-oxide-semiconductor 101, second on described first
105th, metal-oxide-semiconductor 111 and first time metal-oxide-semiconductor 102, second time metal-oxide-semiconductor on metal-oxide-semiconductor the 109, the 6th on metal-oxide-semiconductor the 107, the 5th on the 4th
104th, the three times metal-oxide-semiconductors 106, the four times metal-oxide-semiconductors 108, the five times metal-oxide-semiconductors 110, the six times metal-oxide-semiconductors 112 form 6 grades and mutually latched
Storage unit, gradually it is connected in an identical manner per one-level, the 6th grade is connected to the 1st grade；The interlocking memory cell passes through described
Transmission unit is connected to input sel and input data, and input clr is connected to by the clearing unit；Per one-level bag
1 upper metal-oxide-semiconductor and 1 lower metal-oxide-semiconductor, the drain D end connection of the 1 upper metal-oxide-semiconductor and 1 lower metal-oxide-semiconductor per one-level are included, and is connected
Be connected to the grid G end of metal-oxide-semiconductor on next stage, and under upper level metal-oxide-semiconductor grid G end.
In the disclosure some embodiments, the first transmission metal-oxide-semiconductor 113, second transmits metal-oxide-semiconductor 114 and the 3rd and transmitted
Metal-oxide-semiconductor 115 is NMOS tube.
In the disclosure some embodiments, in the transmission unit：Input sel connects the grid of the first transmission metal-oxide-semiconductor 113
The grid G end at G ends, the grid G end of the second transmission metal-oxide-semiconductor 114 and the 3rd transmission metal-oxide-semiconductor 115；Input data connects the first transmission
The source S end at the source S end of metal-oxide-semiconductor 113, the source S end of the second transmission metal-oxide-semiconductor 114 and the 3rd transmission metal-oxide-semiconductor 115.
In the disclosure some embodiments, in the transmission unit：In the drain D termination first of first transmission metal-oxide-semiconductor 113
The drain D end of metal-oxide-semiconductor 101 and the drain D end of first time metal-oxide-semiconductor 102, the grid G end and of metal-oxide-semiconductor 103 on second is connected to again
The grid G end of six times metal-oxide-semiconductors 112；The drain D end and the of metal-oxide-semiconductor 105 in the drain D termination the 3rd of second transmission metal-oxide-semiconductor 114
The drain D end of three times metal-oxide-semiconductors 106, the grid G end of metal-oxide-semiconductor 107 on the 4th and the grid G end of second time metal-oxide-semiconductor 104 are connected to again；
The drain D end of metal-oxide-semiconductor 109 and the drain D end of the five times metal-oxide-semiconductors 110 in the drain D termination the 5th of 3rd transmission metal-oxide-semiconductor 115,
The grid G end of metal-oxide-semiconductor 111 on the 6th and the grid G end of the four times metal-oxide-semiconductors 108 are connected to again.
In the disclosure some embodiments, described first, which resets metal-oxide-semiconductor 116, second, resets metal-oxide-semiconductor 117 and the 3rd and resets
Metal-oxide-semiconductor 118 is NMOS tube.
In the disclosure some embodiments, in the clearing unit, input clr connects the grid of the first clearing metal-oxide-semiconductor 116
G ends, second reset the grid G end of metal-oxide-semiconductor 117 and the 3rd and reset the grid G end of metal-oxide-semiconductor 118.
In the disclosure some embodiments, in the clearing unit, first resets in the drain D termination second of metal-oxide-semiconductor 116
The drain D end of metal-oxide-semiconductor 103 and the drain D end of second time metal-oxide-semiconductor 104, the grid G end and of metal-oxide-semiconductor 105 on the 3rd is connected to again
The grid G end of metal-oxide-semiconductor 102 once；Second resets the drain D end and the of metal-oxide-semiconductor 107 in the drain D termination the 4th of metal-oxide-semiconductor 117
The drain D end of four times metal-oxide-semiconductors 108, is connected to the grid G end of metal-oxide-semiconductor 109 on the 5th and the grid G end of the three times metal-oxide-semiconductors 106 again；
3rd resets the drain D end of metal-oxide-semiconductor 111 and the drain D end of the six times metal-oxide-semiconductors 112 in the drain D termination the 6th of metal-oxide-semiconductor 118,
The grid G end of metal-oxide-semiconductor 101 on first and the grid G end of the five times metal-oxide-semiconductors 110 are connected to again.
In the disclosure some embodiments, metal-oxide-semiconductor 103 on metal-oxide-semiconductor 101, second, metal-oxide-semiconductor 105, on the 3rd on first
Metal-oxide-semiconductor 111 is PMOS on metal-oxide-semiconductor the 109, the 6th on metal-oxide-semiconductor the 107, the 5th on four；First time metal-oxide-semiconductor 102, second time metal-oxide-semiconductor
104th, the three times metal-oxide-semiconductors 106, the four times metal-oxide-semiconductors 108, the five times metal-oxide-semiconductors 110, the six times metal-oxide-semiconductors 112 are NMOS tube.
In the disclosure some embodiments, in the interlocking memory cell：The source S end of metal-oxide-semiconductor 101, second on first
The source S end of upper metal-oxide-semiconductor 103, the source S end of metal-oxide-semiconductor 105 on the 3rd, the source S end of metal-oxide-semiconductor 107 on the 4th, MOS on the 5th
The source S end of metal-oxide-semiconductor 111 is connected to power supply VCC on the source S end of pipe 109 and the 6th；The source S end of first time metal-oxide-semiconductor 102,
The source S end of second time metal-oxide-semiconductor 104, the source S end of the three times metal-oxide-semiconductors 106, the source S end of the four times metal-oxide-semiconductors 108, the 5th
The source S end of lower metal-oxide-semiconductor 110, the source S end of the six times metal-oxide-semiconductors 112, first reset the source S end of metal-oxide-semiconductor 116, second clear
The source S end of zero metal-oxide-semiconductor 117 and the source S end of the 3rd clearing metal-oxide-semiconductor 118 are connected to ground VSS.
In the disclosure some embodiments, clear one time zero when electric on the FPGA triplication redundancy configuration memory cells, during configuration,
The dispensing unit that ' 1 ' need to be write writes ' 1 '；During retaking of a year or grade configuration data, bit line is defaulted as ' 1 ', by bit line when dispensing unit state is ' 0 '
Retaking of a year or grade is changed into ' 0 ', and bit line is constant when dispensing unit state is ' 1 ', is still ' 1 '.
(3) beneficial effect
It can be seen from the above technical proposal that the primary particle inversion resistant FPGA triplication redundancies configuration memory cell electricity of the disclosure
Road at least has the advantages that one of them：
(1) by triplication redundancy configuration memory cell circuit, realize that configuration will in FPGA using as far as possible few metal-oxide-semiconductor
Ask, PLD single event upset resistant threshold value can be improved；
(2) disclosure has occupied one times of wiring compared to both ends read-write memory cell less；Different from memory cell ' 0 ' with
' 1 ' all needs to read and write, and clear one time zero when electric on the configuration memory cell, the dispensing unit that ' 1 ' need to be write when then configuring writes ' 1 ' again；
It is also to give tacit consent to ' 1 ' during retaking of a year or grade configuration data, a retaking of a year or grade ' 0 '.
Brief description of the drawings
Fig. 1 is the schematic diagram of first embodiment of the present disclosure triplication redundancy configuration memory cell circuit.
【Embodiment of the present disclosure main element symbol description in accompanying drawing】
100th, FPGA triplication redundancies configuration memory cell
101st, metal-oxide-semiconductor on first；102nd, first time metal-oxide-semiconductor
103rd, metal-oxide-semiconductor on second；104th, second time metal-oxide-semiconductor
105th, metal-oxide-semiconductor on the 3rd；106th, the three times metal-oxide-semiconductors
107th, metal-oxide-semiconductor on the 4th；108th, the four times metal-oxide-semiconductors
109th, metal-oxide-semiconductor on the 5th；110th, the five times metal-oxide-semiconductors
111st, metal-oxide-semiconductor on the 6th；112nd, the six times metal-oxide-semiconductors
113rd, the first transmission metal-oxide-semiconductor；114th, the second transmission metal-oxide-semiconductor
115th, the 3rd transmission metal-oxide-semiconductor；116th, first metal-oxide-semiconductor is reset
117th, second metal-oxide-semiconductor is reset；118th, the 3rd metal-oxide-semiconductor is reset
Embodiment
Present disclose provides a kind of triplication redundancy configuration memory cell circuit reinforced for the upset of FPGA anti-single particles.Root
According to embodiment of the present invention, triplication redundancy configuration memory cell circuit of the invention includes 6 PMOSs and 6 NMOS tube groups
Into 6 grades interlocking memory cell, 3 transfer tubes, and 3 reset pipe.
For the purpose, technical scheme and advantage of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the disclosure is further described.
The some embodiments of the disclosure will be done with reference to appended accompanying drawing in rear and more comprehensively describe to property, some of but not complete
The embodiment in portion will be illustrated.In fact, the various embodiments of the disclosure can be realized in many different forms, and should not be construed
To be limited to this several illustrated embodiment；Relatively, there is provided these embodiments cause the disclosure to meet applicable legal requirement.
In first exemplary embodiment of the disclosure, there is provided a kind of primary particle inversion resistant FPGA triplication redundancies are matched somebody with somebody
Put storage unit circuit.Fig. 1 is the schematic diagram of first embodiment of the present disclosure triplication redundancy configuration memory cell circuit.Such as Fig. 1 institutes
Show, disclosure triplication redundancy configuration memory cell circuit includes：
Transmission unit, including 3 transfer tubes 113,114 and 115, the transfer tube are NMOS tube；Wherein,
Input sel connects the grid G end of the first transmission metal-oxide-semiconductor 113, the grid G end and the 3rd of the second transmission metal-oxide-semiconductor 114
Transmit the grid G end of metal-oxide-semiconductor 115.
Input data connects the source S end of the first transmission metal-oxide-semiconductor 113, the source S end and the 3rd of the second transmission metal-oxide-semiconductor 114
Transmit the source S end of metal-oxide-semiconductor 115.
The drain D end of metal-oxide-semiconductor 101 and first time metal-oxide-semiconductor 102 in the drain D termination first of first transmission metal-oxide-semiconductor 113
Drain D end, the grid G end of metal-oxide-semiconductor 103 on second and the grid G end of the six times metal-oxide-semiconductors 112 are connected to again.
The drain D end of metal-oxide-semiconductor 105 and the three times metal-oxide-semiconductors 106 in the drain D termination the 3rd of second transmission metal-oxide-semiconductor 114
Drain D end, the grid G end of metal-oxide-semiconductor 107 on the 4th and the grid G end of second time metal-oxide-semiconductor 104 are connected to again.
The drain D end of metal-oxide-semiconductor 109 and the five times metal-oxide-semiconductors 110 in the drain D termination the 5th of 3rd transmission metal-oxide-semiconductor 115
Drain D end, the grid G end of metal-oxide-semiconductor 111 on the 6th and the grid G end of the four times metal-oxide-semiconductors 108 are connected to again.
Unit, including 3 clearing pipes 116,117 and 118 are reset, the pipe that resets is NMOS tube.Wherein,
Input clr connects the grid G end of the first clearing metal-oxide-semiconductor 116, the grid G end and the 3rd of the second clearing metal-oxide-semiconductor 117
Reset the grid G end of metal-oxide-semiconductor 118.
First resets the drain D end of metal-oxide-semiconductor 103 and second time metal-oxide-semiconductor 104 in the drain D termination second of metal-oxide-semiconductor 116
Drain D end, the grid G end of metal-oxide-semiconductor 105 on the 3rd and the grid G end of first time metal-oxide-semiconductor 102 are connected to again.
Second resets the drain D end of metal-oxide-semiconductor 107 and the four times metal-oxide-semiconductors 108 in the drain D termination the 4th of metal-oxide-semiconductor 117
Drain D end, the grid G end of metal-oxide-semiconductor 109 on the 5th and the grid G end of the three times metal-oxide-semiconductors 106 are connected to again.
3rd resets the drain D end of metal-oxide-semiconductor 111 and the six times metal-oxide-semiconductors 112 in the drain D termination the 6th of metal-oxide-semiconductor 118
Drain D end, the grid G end of metal-oxide-semiconductor 101 on first and the grid G end of the five times metal-oxide-semiconductors 110 are connected to again.
Memory cell, including 6 upper metal-oxide-semiconductors and 6 lower metal-oxide-semiconductors are interlocked, form 6 grades of interlocking memory cell, wherein upper MOS
Manage as metal-oxide-semiconductor 101,103,105,107,109,111 on 6 first, lower metal-oxide-semiconductor be 6 first time metal-oxide-semiconductors 102,104,106,
108、110、112。
The source S end of metal-oxide-semiconductor 101 on first, the source S end of metal-oxide-semiconductor 103 on second, on the 3rd metal-oxide-semiconductor 105 source S
End, the source S end of metal-oxide-semiconductor 107 on the 4th, the source S end of metal-oxide-semiconductor 111 is equal on the source S end and the 6th of metal-oxide-semiconductor 109 on the 5th
It is connected to power supply VCC.The source S end of first time metal-oxide-semiconductor 102, the source S end of second time metal-oxide-semiconductor 104, the three times metal-oxide-semiconductors 106
Source S end, the source S end of the four times metal-oxide-semiconductors 108, the source S end of the five times metal-oxide-semiconductors 110, the source S of the six times metal-oxide-semiconductors 112
End, the source S end of the first clearing metal-oxide-semiconductor 116, second reset the source S end of metal-oxide-semiconductor 117 and the 3rd and reset the source of metal-oxide-semiconductor 118
Pole S ends are connected to ground VSS.
Clear one time zero when electric on the primary particle inversion resistant FPGA triplication redundancies configuration memory cell circuit, afterwards with
When putting, the dispensing unit that need to write ' 1 ' writes ' 1 ', need to write ' 0 ' dispensing unit and need not set；During retaking of a year or grade configuration data, bit line is write from memory
Think ' 1 ', bit line retaking of a year or grade be changed into ' 0 ' when dispensing unit state is ' 0 ', bit line is constant when dispensing unit state is ' 1 ', still for
‘1’。
The present invention not by the specific implementation method of circuit limited and circuit used by logical form limit, for example,
All bottom circuits can be the CMOS technology of standard or other techniques.
Certainly, according to being actually needed, the preparation method of disclosure display device also includes other techniques and step, due to
Innovation with the disclosure is unrelated, and here is omitted.
Certainly, those skilled in the art in the art can also add corresponding functional module, herein according to the needs of function
Do not repeat.
So far, the primary particle inversion resistant FPGA triplication redundancies configuration memory cell circuit of the first embodiment of the present disclosure has been introduced
Finish.
So far, the embodiment of the present disclosure is described in detail combined accompanying drawing.It should be noted that in accompanying drawing or say
In bright book text, the implementation that does not illustrate or describe is form known to a person of ordinary skill in the art in art, and
It is not described in detail.In addition, the above-mentioned definition to each element and method be not limited in mentioning in embodiment it is various specific
Structure, shape or mode, those of ordinary skill in the art simply can be changed or replaced to it.
It should also be noted that, the direction term mentioned in embodiment, for example, " on ", " under ", "front", "rear", " left side ",
" right side " etc., only it is the direction of refer to the attached drawing, is not used for limiting the protection domain of the disclosure.Through accompanying drawing, identical element by
Same or like reference represents.When understanding of this disclosure may be caused to cause to obscure, conventional structure will be omitted
Or construction.
And the shape and size of each part do not reflect actual size and ratio in figure, and only illustrate the embodiment of the present disclosure
Content.In addition, in the claims, any reference symbol between bracket should not be configured to the limit to claim
System.
Furthermore word "comprising" does not exclude the presence of element or step not listed in the claims.Before element
Word "a" or "an" does not exclude the presence of multiple such elements.
Specification and the word of ordinal number such as " first ", " second ", " the 3rd " etc. used in claim, with modification
Corresponding element, itself is not meant to that the element has any ordinal number, does not also represent the suitable of a certain element and another element
Order in sequence or manufacture method, the use of those ordinal numbers are only used for enabling the element with certain name and another tool
The element for having identical name can make clear differentiation.
In addition, unless specifically described or the step of must sequentially occur, the order of above-mentioned steps, which has no, is limited to above institute
Row, and can change or rearrange according to required design.And above-described embodiment can based on design and reliability consideration, that
This mix and match uses using or with other embodiment mix and match, i.e., the technical characteristic in different embodiments can be with independent assortment
Form more embodiments.
Those skilled in the art, which are appreciated that, to be carried out adaptively to the module in the equipment in embodiment
Change and they are arranged in one or more equipment different from the embodiment.Can be the module or list in embodiment
Member or component be combined into a module or unit or component, and can be divided into addition multiple submodule or subelement or
Sub-component.In addition at least some in such feature and/or process or unit exclude each other, it can use any
Combination is disclosed to all features disclosed in this specification (including adjoint claim, summary and accompanying drawing) and so to appoint
Where all processes or unit of method or equipment are combined.Unless expressly stated otherwise, this specification (including adjoint power
Profit requires, summary and accompanying drawing) disclosed in each feature can be by providing the alternative features of identical, equivalent or similar purpose come generation
Replace.Also, in if the unit claim of equipment for drying is listed, several in these devices can be by same hard
Part item embodies.
Similarly, it will be appreciated that in order to simplify the disclosure and help to understand one or more of each open aspect,
Above in the description to the exemplary embodiment of the disclosure, each feature of the disclosure is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention：I.e. required guarantor
The disclosure of shield requires features more more than the feature being expressly recited in each claim.It is more precisely, such as following
Claims reflect as, open aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following embodiment are expressly incorporated in the embodiment, wherein each claim is in itself
Separate embodiments all as the disclosure.
Particular embodiments described above, the purpose, technical scheme and beneficial effect of the disclosure are carried out further in detail
Describe in detail bright, should be understood that the specific embodiment that the foregoing is only the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution and improvements done etc., the guarantor of the disclosure should be included in
Within the scope of shield.
Claims (10)
1. a kind of primary particle inversion resistant FPGA triplication redundancies configuration memory cell circuit, including：
Transmission unit, including：
3 transfer tubes：First transmission metal-oxide-semiconductor (113), the second transmission metal-oxide-semiconductor (114) and the 3rd transmission metal-oxide-semiconductor (115), it is described
First transmission metal-oxide-semiconductor (113), the second transmission metal-oxide-semiconductor (114) and the 3rd transmission metal-oxide-semiconductor (115) are connected to input sel, described
First transmission metal-oxide-semiconductor (113), the second transmission metal-oxide-semiconductor (114) and the 3rd transmission metal-oxide-semiconductor (115) are connected to the input
data；
Unit is reset, including：
3 reset pipe：First resets metal-oxide-semiconductor (116), the second clearing metal-oxide-semiconductor (117) and the 3rd resets metal-oxide-semiconductor (118), described
First clearing metal-oxide-semiconductor (116), the second clearing metal-oxide-semiconductor (117) and the 3rd clearing metal-oxide-semiconductor (118) are connected to input clr；
Memory cell is interlocked, including：
6 upper metal-oxide-semiconductors：Metal-oxide-semiconductor (101) on first, metal-oxide-semiconductor (103) on second, metal-oxide-semiconductor (105) on the 3rd, metal-oxide-semiconductor on the 4th
(107), metal-oxide-semiconductor (109) on the 5th, metal-oxide-semiconductor (111) on the 6th, and
6 lower metal-oxide-semiconductors：First time metal-oxide-semiconductor (102), second time metal-oxide-semiconductor (104), the three times metal-oxide-semiconductors (106), the four times metal-oxide-semiconductors
(108), the five times metal-oxide-semiconductors (110), the six times metal-oxide-semiconductors (112)；
Wherein, metal-oxide-semiconductor (101) on described first, metal-oxide-semiconductor (103) on second, metal-oxide-semiconductor (105) on the 3rd, metal-oxide-semiconductor on the 4th
(107), metal-oxide-semiconductor (109) on the 5th, metal-oxide-semiconductor (111) and first time metal-oxide-semiconductor (102), second time metal-oxide-semiconductor (104), on the 6th
Three times metal-oxide-semiconductors (106), the four times metal-oxide-semiconductors (108), the five times metal-oxide-semiconductors (110), the six times metal-oxide-semiconductors (112) form 6 grades of interlockings
Memory cell, gradually it is connected in an identical manner per one-level, the 6th grade is connected to the 1st grade；The interlocking memory cell passes through institute
State transmission unit and be connected to input sel and input data, input clr is connected to by the clearing unit；Per one-level
Including 1 upper metal-oxide-semiconductor and 1 lower metal-oxide-semiconductor, the drain D end connection of the 1 upper metal-oxide-semiconductor and 1 lower metal-oxide-semiconductor per one-level, and
Be connected to the grid G end of metal-oxide-semiconductor on next stage, and under upper level metal-oxide-semiconductor grid G end.
2. FPGA triplication redundancies configuration memory cell circuit according to claim 1, wherein, the first transmission metal-oxide-semiconductor
(113), the second transmission metal-oxide-semiconductor (114) and the 3rd transmission metal-oxide-semiconductor (115) are NMOS tube.
3. FPGA triplication redundancies configuration memory cell circuit according to claim 2, in the transmission unit：
Input sel connects the grid G end of the first transmission metal-oxide-semiconductor (113), the grid G end and the 3rd of the second transmission metal-oxide-semiconductor (114)
Transmit the grid G end of metal-oxide-semiconductor (115)；
Input data connects the source S end of the first transmission metal-oxide-semiconductor (113), the source S end and the 3rd of the second transmission metal-oxide-semiconductor (114)
Transmit the source S end of metal-oxide-semiconductor (115).
4. FPGA triplication redundancies configuration memory cell circuit according to claim 3, in the transmission unit：
The drain D end of metal-oxide-semiconductor (101) and first time metal-oxide-semiconductor (102) in the drain D termination first of first transmission metal-oxide-semiconductor (113)
Drain D end, be connected to the grid G end of metal-oxide-semiconductor on second (103) and the grid G end of the six times metal-oxide-semiconductors (112) again；
The drain D end of metal-oxide-semiconductor (105) and the three times metal-oxide-semiconductors (106) in the drain D termination the 3rd of second transmission metal-oxide-semiconductor (114)
Drain D end, be connected to the grid G end of metal-oxide-semiconductor (107) and the grid G end of second time metal-oxide-semiconductor (104) on the 4th again；
The drain D end of metal-oxide-semiconductor (109) and the five times metal-oxide-semiconductors (110) in the drain D termination the 5th of 3rd transmission metal-oxide-semiconductor (115)
Drain D end, be connected to the grid G end of metal-oxide-semiconductor (111) and the grid G end of the four times metal-oxide-semiconductors (108) on the 6th again.
5. FPGA triplication redundancies configuration memory cell circuit according to claim 4, wherein, described first resets metal-oxide-semiconductor
(116), the second clearing metal-oxide-semiconductor (117) and the 3rd clearing metal-oxide-semiconductor (118) are NMOS tube.
6. FPGA triplication redundancies configuration memory cell circuit according to claim 5, described to reset in unit,
Input clr connects the grid G end of the first clearing metal-oxide-semiconductor (116), the grid G end and the 3rd of the second clearing metal-oxide-semiconductor (117)
Reset the grid G end of metal-oxide-semiconductor (118).
7. FPGA triplication redundancies configuration memory cell circuit according to claim 6, described to reset in unit,
First resets the drain D end of metal-oxide-semiconductor (103) and second time metal-oxide-semiconductor (104) in the drain D termination second of metal-oxide-semiconductor (116)
Drain D end, be connected to the grid G end of metal-oxide-semiconductor (105) and the grid G end of first time metal-oxide-semiconductor (102) on the 3rd again；
Second resets the drain D end of metal-oxide-semiconductor (107) and the four times metal-oxide-semiconductors (108) in the drain D termination the 4th of metal-oxide-semiconductor (117)
Drain D end, be connected to the grid G end of metal-oxide-semiconductor (109) and the grid G end of the three times metal-oxide-semiconductors (106) on the 5th again；
3rd resets the drain D end of metal-oxide-semiconductor (111) and the six times metal-oxide-semiconductors (112) in the drain D termination the 6th of metal-oxide-semiconductor (118)
Drain D end, be connected to the grid G end of metal-oxide-semiconductor on first (101) and the grid G end of the five times metal-oxide-semiconductors (110) again.
8. FPGA triplication redundancies configuration memory cell circuit according to claim 7, wherein, metal-oxide-semiconductor (101) on first,
Metal-oxide-semiconductor (103) on second, metal-oxide-semiconductor (105) on the 3rd, metal-oxide-semiconductor (107) on the 4th, metal-oxide-semiconductor (109) on the 5th, MOS on the 6th
It is PMOS to manage (111)；
First time metal-oxide-semiconductor (102), second time metal-oxide-semiconductor (104), the three times metal-oxide-semiconductors (106), the four times metal-oxide-semiconductors (108), five
Lower metal-oxide-semiconductor (110), the six times metal-oxide-semiconductors (112) are NMOS tube.
9. FPGA triplication redundancies configuration memory cell circuit according to claim 7, described to interlock in memory cell：
The source S end of metal-oxide-semiconductor (101) on first, the source S end of metal-oxide-semiconductor (103) on second, on the 3rd metal-oxide-semiconductor (105) source
Pole S ends, metal-oxide-semiconductor on the 4th (107 source S end, metal-oxide-semiconductor (111) on the source S end and the 6th of metal-oxide-semiconductor (109) on the 5th
Source S end is connected to power supply VCC；
The source S end of first time metal-oxide-semiconductor (102), the source S end of second time metal-oxide-semiconductor (104), the source of the three times metal-oxide-semiconductors (106)
Pole S ends, the source S end of the four times metal-oxide-semiconductors (108), the five times metal-oxide-semiconductors (110 source S end, the source of the six times metal-oxide-semiconductors (112)
Pole S ends, first reset the source S end of metal-oxide-semiconductor (116), the source S end of the second clearing metal-oxide-semiconductor (117) and the 3rd clearing metal-oxide-semiconductor
(118) source S end is connected to ground VSS.
10. FPGA triplication redundancies configuration memory cell circuit according to claim 9, FPGA triplication redundancies configuration storage
Clear one time zero when electric on unit, during configuration, the dispensing unit that need to write ' 1 ' writes ' 1 '；During retaking of a year or grade configuration data, bit line is defaulted as
' 1 ', bit line retaking of a year or grade is changed into ' 0 ' when dispensing unit state is ' 0 ', bit line is constant when dispensing unit state is ' 1 ', is still ' 1 '.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109979517A (en) * | 2019-03-07 | 2019-07-05 | 中科亿海微电子科技（苏州）有限公司 | N-modular redundancy configuration memory cell circuit for FPGA |
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| CN103632715A (en) * | 2013-05-08 | 2014-03-12 | 中国科学院电子学研究所 | Two-module redundancy configuration memory unit circuit used in programmable logic device |
| CN103870353A (en) * | 2014-03-18 | 2014-06-18 | 北京控制工程研究所 | Multicore-oriented reconfigurable fault tolerance system and multicore-oriented reconfigurable fault tolerance method |
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| US20010009029A1 (en) * | 1995-12-22 | 2001-07-19 | Farnworth Warren M. | Device and method for testing integrated circuit dice in an integrated circuit module |
| CN103632715A (en) * | 2013-05-08 | 2014-03-12 | 中国科学院电子学研究所 | Two-module redundancy configuration memory unit circuit used in programmable logic device |
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| CN109979517A (en) * | 2019-03-07 | 2019-07-05 | 中科亿海微电子科技（苏州）有限公司 | N-modular redundancy configuration memory cell circuit for FPGA |
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