CN107818071A - A kind of hardware thread implementation method based on FPGA - Google Patents
A kind of hardware thread implementation method based on FPGA Download PDFInfo
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- CN107818071A CN107818071A CN201710887368.8A CN201710887368A CN107818071A CN 107818071 A CN107818071 A CN 107818071A CN 201710887368 A CN201710887368 A CN 201710887368A CN 107818071 A CN107818071 A CN 107818071A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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Abstract
The invention discloses a kind of hardware thread implementation method based on FPGA, comprise the following steps：The first step, cutting application program：It is main thread and from thread by application program cutting；Second step, Hardware main thread；3rd step, Hardware are from thread；4th step, establish application program stream file：All hardware code, data and the configuration information of application program are established as application program stream file on the local computer；In 5th step, programming application program stream file to FPGA；6th step, dynamic creation and configuration sub-line journey.The present invention is configured to hardware thread after application program is carried out into cutting, the type for the software thread being syncopated as according to application program, hardware main thread and hardware sub-line journey are constructed respectively, then hardware thread is created on FPGA and configured and is come, and complete the execution of application program.The present invention makes full use of resource on FPGA plate, and application program is reconstructed into hardware thread, configures and runs on FPGA plates, so as to greatly improve the execution efficiency of application program.
Description
Technical field
The present invention relates to Reconfiguration Technologies field, more particularly to a kind of hardware thread implementation method based on FPGA.
Background technology
Reconfigurable Computation is considered as can be by the high degree of flexibility and ASIC of conventional processors（Application
Specific Integrated Circuit）The effective solution that possessed high treatment efficiency is combined.Due to that can weigh
Structure architecture has well adapting to property, can be by varigrained parallel come speed up processing for different application.
In restructural equipment, FPGA（Field-Programmable Gate Array）It is most widely used reconfigurable device.
Dynamically reconfigurable FPGA is the important foundation for realizing hardware-level multitask.Such FPGA processing region is commonly divided into
Different sub-blocks, configurable logic block（Configurable Logic Block, CLB）.In addition, it further comprises input/output block
（I/O blocks）And programmable interconnection network（Also known as line, Routing）.CLB is the elementary cell for realizing user function, generally row
An array is arranged into, spreads whole chip；I/O blocks are the interfaces of logical AND external package pins on piece, generally surround and are distributed in
CLB array surroundings；The line and some reconfigurable interconnections of programmable interconnection network including various length switch, they by CLB or
I/O blocks connect, and realize the circuit of specific function.
Hardware thread can be realized using FPGA restructural characteristic.In software/hardware threading model, OS to hardware and
Software task provides similar kernel interface, and software/hardware task can use OS system service, such as synchronization mechanism, system
Resource (including file system, standard input and output etc.).Therefore, application program can neatly use system service, so as to letter
The use of restructural resource is changed.The difference defined according to different system, the model are alternatively referred to as software/hardware process model.
The linux kernel of BORPH extension standards of the prior art is to support FPGA, the calculating using FPGA as standard
Resource, and propose hardware process（Hardware Process）Concept.BORPH defines new entitled BORPH objects text
Part（BOF）Binary format, encapsulate FPGA configuration, as the execution mirror image of hardware process, BOF execution will trigger
FPGA configuration process.In addition, BORPH provides two kinds of software/hardware communication parties based on ioreg interfaces and file I/O interface
Method, to provide consistent software/hardware process runtime environment.There is entitled HWTI hardware thread interface in addition, there is provided class
The related system of POSIX thread creation, communication is called, to support soft or hard multithreading.Based on eCos and design of Linux
RECONOS, identical operating system service is provided to software/hardware thread by hardware abstraction layer, but in ReconOS, institute
There is thread to share identical physical address space, therefore, be only suitable for the small-scale computing system such as embedded system.Domestic aspect,
A kind of server/execution stream model is proposed in SEF-OSHRS operating systems, providing unification to software and hardware task takes out
As；Software and hardware, which is employed, in real-time restructural operating system SHUM-UCOS unifies task model.
But current major design is all to open software and hardware thread cutting, there is must be separately between software and hardware thread
Communication mode is designed, and as a rule general processor part and FPGA portion are relatively independent, this allows for software and hardware line
The communication cost of journey and realize that cost is all larger.The present invention makes full use of resource on FPGA plate, and application program is reconstructed into firmly
Part thread, configure and run on FPGA plates, so as to greatly improve the execution efficiency of application program.
The content of the invention
The present invention proposes a kind of hardware thread implementation method based on FPGA.
The present invention is as follows to solve the technical scheme that its technical problem uses：A kind of hardware thread realization side based on FPGA
Method, comprise the following steps：
The first step, cutting application program：
It is main thread and from thread by application program cutting；
Second step, Hardware main thread：
Main thread is realized using hardware description language, constructs the main thread of Hardware；
3rd step, Hardware are from thread：
Using hardware description language to being realized from thread, construct Hardware from thread；
4th step, establish application program stream file：
All hardware code, data and the configuration information of application program are established as application flow text on the local computer
Part；
In 5th step, programming application program stream file to FPGA：
By in application program stream file programming to FPGA；
6th step, dynamic creation and configuration sub-line journey.
Further, the main thread be responsible in application program from starting until terminate all in the thread of execution from
The management of thread；It is described from thread be created in application program in special time period, the thread that exists and perform task.
Further, in the 5th step, in application program stream file programming to FPGA after, hardware main thread first by
Create and be configured on FPGA, then start to perform.
Further, the 6th step is specially：
In hardware main thread implementation procedure, specific task is completed from thread if necessary to a hardware, then hardware main line
Corresponding hardware is from thread part in journey reading application program stream file, and creates a hardware from thread；Hardware main thread from
FPGA apply a block space, by the hardware from thread configuration on this block space, then start the hardware holding from thread
OK, hardware performs calculating task since thread, and after the completion of calculating task, result of calculation is sent to hardware by hardware from thread
Main thread.
Further, in implementation procedure of the hardware from thread, if the execution of hardware main thread depends on hardware from line
The result of calculation of journey, then hardware main thread pause performs, when hardware main thread receives hardware after the result of calculation of thread
It is further continued for performing；If result of calculation of the execution of hardware main thread independent of hardware from thread, hardware main thread continues
Perform, the result of calculation from hardware from thread is reprocessed until receiving hardware after the result of calculation of thread.
Further, after the completion of the execution of hardware sub-line journey, this performs the FPGA shared by the hardware sub-line journey completed
Space is recovered.
The present invention has an advantageous effect in that compared with background technology：
(1) high efficiency.The present invention is dynamically generated the hardware thread of application program by FPGA Resources on Chip, passes through hardware
Thread execution efficiency is higher, while also higher to the utilization ratio of FPGA resource.
(2) it is easily achieved.The present invention takes full advantage of FPGA Resources on Chip, should to realize by FPGA own resources
With the hardware thread of program, it is not necessary to communicated with general processor, so that this method is more easily realized.
Brief description of the drawings
Fig. 1 is a kind of flow chart of hardware thread implementation method based on FPGA of the present invention.
Fig. 2 is the schematic diagram of the application program P cuttings of an embodiment in the present invention.
Fig. 3 is the schematic diagram of the application program P Hardwares of an embodiment in the present invention.
Fig. 4 is the schematic diagram performed after the application program P Hardwares of an embodiment in the present invention.
Embodiment
The present invention will be further described with reference to the accompanying drawings and detailed description, not to the limit of its protection domain
System.
A kind of hardware thread implementation method based on FPGA, it is as follows that it implements flow.
The first step, cutting application program：
It is main thread and from thread by application program cutting.Wherein main thread is until terminating all to exist in application program from beginning
The thread of execution, it is responsible for the management from thread；It is to be created in application program in special time period, exist and perform task from thread
Thread.At least one main thread of each application program.If from thread return result of calculation, main thread need wait from
The result of calculation that thread returns, now main thread pause performs, until receiving the result of calculation returned from thread.If from thread
Result of calculation is not returned to, then main thread withouts waiting for the result of calculation returned from thread, and now main thread continues executing with.
As shown in Fig. 2 in one embodiment, for application program P, by application program P cuttings be main thread PM and 5 from
Thread, this 5 are respectively from thread：From thread P1, from thread P2, from thread P3, from thread P4, from thread P5.From thread P1,
It is respectively completed from thread P2, from thread P3, from thread P4, from thread P5：
1）Calculating task C1 is completed from thread P1, and returns to result of calculation.Main thread PM needs to wait the meter returned from thread P1
Calculate result.
2）Calculating task C2 is completed from thread P2, and returns to result of calculation.Main thread PM needs to wait to be returned from thread P2
Result of calculation.
3）Calculating task C3 is completed from thread P3, does not return to result of calculation.Main thread PM withouts waiting for returning from thread P3
The result of calculation returned, is continued executing with.
4）Calculating task C4 is completed from thread P4, and returns to result of calculation.Main thread PM needs to wait to be returned from thread P4
Result of calculation.
5）Calculating task C5 is completed from thread P5, does not return to result of calculation.Main thread PM withouts waiting for returning from thread P5
The result of calculation returned, is continued executing with.
Second step, Hardware main thread：
Using hardware description language to being realized from thread, the main thread of Hardware is constructed.
As shown in figure 3, in one embodiment, for application program P, its main thread PM forms hardware master after carrying out Hardware
Thread PM '.
3rd step, Hardware are from thread：
Using hardware description language to being realized from thread, construct Hardware from thread.
As shown in figure 3, in one embodiment, for application program P, be syncopated as by application program P 5 from thread：From
Thread P1, from thread P2, from thread P3, from thread P4, from thread P5, after being realized using hardware description language respectively
For：Hardware is from thread P1 ', hardware from thread P2 ', hardware from thread P3 ', hardware from thread P4 ', hardware from thread P5 '.Then with
From thread P1, from thread P2, from thread P3, from thread P4, it is corresponding from thread P5, hardware from thread P1 ', hardware from thread P2 ',
Hardware is respectively completed from thread P3 ', hardware from thread P4 ', hardware from thread P5 '：
1）Hardware completes calculating task C1 from thread P1 '；
2）Hardware completes calculating task C2 from thread P2 '；
3）Hardware completes calculating task C3 from thread P3 '；
4）Hardware completes calculating task C4 from thread P4 '；
5）Hardware completes calculating task C5 from thread P5 '.
4th step, establish application program stream file：
All hardware code, data and the configuration information of application program are established as application flow text on the local computer
Part.
For application program P, by the hardware main thread PM ' after Hardware, hardware from thread P1 ', hardware from thread P2 ',
Hardware exists from thread P3 ', hardware from thread P4 ', hardware from the configuration information of thread P5 ', the data of application program, application program
Application program stream file SP is established as on local computer.
In 5th step, programming application program stream file to FPGA：
By in application program stream file programming to FPGA.After in application program stream file programming to FPGA, hardware main thread is first
First it is created and is configured on FPGA, then starts to perform.Because hardware main thread corresponds to main thread, therefore work as hardware master
When thread starts to perform, mean that application program starts to perform on FPGA.Because hardware main thread is real with hardware description language
Hardware module is configured to now and on FPGA, therefore hardware main thread realizes the main thread example, in hardware on FPGA.
In one embodiment, for application program P, by application program P stream file SP programmings to FPGA.Using journey
To after on FPGA, hardware main thread PM ' is created and is configured on FPGA first, then starts to hold for sequence stream file SP programmings
OK.
6th step, dynamic creation and configuration sub-line journey：
In hardware main thread implementation procedure, specific task is completed from thread if necessary to a hardware, then hardware main line
Corresponding hardware is from thread part in journey reading application program stream file, and creates a hardware from thread, is completed on FPGA
Configuration of this hardware from thread.Hardware main thread applies for a block space from FPGA, by hardware from thread configuration in this block space
On, then start execution of the hardware from thread.Hardware performs calculating task, after the completion of calculating task, hardware since thread
Hardware main thread is sent to from thread by result of calculation.In implementation procedure of the hardware from thread, if hardware main thread is held
Row depend on result of calculation of the hardware from thread, then hardware main thread pause execution, when hardware main thread receive hardware from
It is further continued for performing after the result of calculation of thread；If result of calculation of the execution of hardware main thread independent of hardware from thread,
Then hardware main thread is continued executing with, and the calculating from hardware from thread is reprocessed until receiving hardware after the result of calculation of thread
As a result.
After the completion of the execution of hardware sub-line journey, this FPGA space for performing shared by the hardware sub-line journey completed will be returned
Receive.
As shown in figure 4, in one embodiment, for application program P, hardware main thread PM ' has needed in the process of implementation
Into calculating task C1, hardware main thread PM ' needs hardware from thread P1 ' to complete calculating task C1.Then hardware main thread is read
Corresponding hardware is from thread P1 ' in application program stream file, and creates a hardware from thread P1 ', and hardware is completed on FPGA
From thread P1 ' configuration.Hardware main thread PM ' applies for a block space from FPGA, and hardware is configured in this block space from thread P1 '
On, then start execution of the hardware from thread P1 '.Hardware performs calculating task C1 since thread P1 ', complete in calculating task C1
Result of calculation is sent to hardware main thread PM ' by Cheng Hou, hardware from thread P1 '.In hardware from thread P1 ' implementation procedure,
Hardware main thread PM ' execution depends on result of calculation of the hardware from thread P1 ', then hardware main thread PM ' pauses perform, and wait until
Hardware main thread PM ' receives hardware and is further continued for performing after thread P1 ' result of calculation.Hardware from thread P2 ' and hardware from
The two hardware of thread P4 ' are required for returning to result of calculation upon execution from thread, therefore are performed in the two hardware from thread
When, hardware main thread stops performing, and is transferred to halted state.
Because hardware from thread P3 ' and hardware from thread P5 ' need not return to result of calculation upon execution, thus this two
Individual hardware from thread perform when, hardware main thread does not stop performing.
In hardware sub-line journey P1 ', hardware from thread P2 ', hardware from thread P3 ', hardware from thread P4 ', hardware from thread
After the completion of P5 ' is performed respectively, this five FPGA spaces performed shared by the hardware sub-line journey completed will perform in each of which
After the completion of be recovered.
In a word, the foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in the present invention
Spirit and principle within all any modification, equivalent and improvement made etc., should be included in protection scope of the present invention it
It is interior.
Claims (6)
1. a kind of hardware thread implementation method based on FPGA, it is characterised in that comprise the following steps：
The first step, cutting application program：
It is main thread and from thread by application program cutting；
Second step, Hardware main thread：
Main thread is realized using hardware description language, constructs the main thread of Hardware；
3rd step, Hardware are from thread：
Using hardware description language to being realized from thread, construct Hardware from thread；
4th step, establish application program stream file：
All hardware code, data and the configuration information of application program are established as application flow text on the local computer
Part；
In 5th step, programming application program stream file to FPGA：
By in application program stream file programming to FPGA；
6th step, dynamic creation and configuration sub-line journey.
A kind of 2. hardware thread implementation method based on FPGA according to claim 1, it is characterised in that：The main thread
It is all in the thread of execution, the responsible management from thread in application program from starting up to end；It is described from thread be application
The thread for creating in special time period in program, existing and performing task.
A kind of 3. hardware thread implementation method based on FPGA according to claim 1, it is characterised in that：5th step
In, in application program stream file programming to FPGA after, hardware main thread is created and is configured on FPGA first, Ran Houkai
Begin to perform.
A kind of 4. hardware thread implementation method based on FPGA according to claim 1, it is characterised in that：6th step
Specially：
In hardware main thread implementation procedure, specific task is completed from thread if necessary to a hardware, then hardware main line
Corresponding hardware is from thread part in journey reading application program stream file, and creates a hardware from thread；Hardware main thread from
FPGA apply a block space, by the hardware from thread configuration on this block space, then start the hardware holding from thread
OK, hardware performs calculating task since thread, and after the completion of calculating task, result of calculation is sent to hardware by hardware from thread
Main thread.
A kind of 5. hardware thread implementation method based on FPGA according to claim 4, it is characterised in that：In hardware from line
In the implementation procedure of journey, if the execution of hardware main thread depends on result of calculation of the hardware from thread, hardware main thread is temporary
Stop performing, be further continued for performing when hardware main thread receives hardware after the result of calculation of thread；If hardware main thread
The result of calculation independent of hardware from thread is performed, then hardware main thread continues executing with, until receiving meter of the hardware from thread
Result of calculation of the reprocessing from hardware from thread after calculation result.
A kind of 6. hardware thread implementation method based on FPGA according to claim 5, it is characterised in that：In hardware sub-line
After the completion of Cheng Zhihang, this FPGA space for performing shared by the hardware sub-line journey completed is recovered.
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| CN111225153A (en) * | 2020-01-21 | 2020-06-02 | Oppo广东移动通信有限公司 | Image data processing method, image data processing device and mobile terminal |
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| US8402409B1 (en) * | 2006-03-10 | 2013-03-19 | Xilinx, Inc. | Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit |
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Effective date of registration: 20211214 Address after: 210000 Gaoxin Park, No. 1009, Tianyuan East Road, Jiangning District, Nanjing City, Jiangsu Province Patentee after: Nanjing hangrui measurement and Control Technology Co.,Ltd. Address before: 100089 Beijing Haidian District 2 Huayuan Road peony Venture Building 4 floor 1424 room Patentee before: Beijing Zhonglian Technology Service Co.,Ltd. Effective date of registration: 20211214 Address after: 100089 Beijing Haidian District 2 Huayuan Road peony Venture Building 4 floor 1424 room Patentee after: Beijing Zhonglian Technology Service Co.,Ltd. Address before: 430081 Heping Avenue 947, Wuhan City, Hubei Province Patentee before: WUHAN University OF SCIENCE AND TECHNOLOGY |