CN107817953A - A kind of method and device of dual control storage device access hard disk - Google Patents
A kind of method and device of dual control storage device access hard disk Download PDFInfo
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- CN107817953A CN107817953A CN201711160024.3A CN201711160024A CN107817953A CN 107817953 A CN107817953 A CN 107817953A CN 201711160024 A CN201711160024 A CN 201711160024A CN 107817953 A CN107817953 A CN 107817953A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0626—Reducing size or complexity of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
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Abstract
The application provides a kind of method and device of dual control storage device access hard disk, applied to storage device, the backboard of the storage device inserts multiple dual-port NVMe hard disks and two controllers being oppositely arranged be present, and each connector of each controller is connected with each hard disk on backboard based on nearby principle；The pre-configured two link maps tables of each controller, this method include：The CPU of controller receives I/O request；Wherein, I/O request carries the disk position information of target hard disk；CPU is by specifying link maps table of the level signal selection on pin corresponding to the level signal；Wherein, the value of the level signal on the specified pin of different controllers is different；The link maps table that disk position information searchings of the CPU in I/O request is chosen, it is determined that the mark of the physical link corresponding to disk position information, and high-speed PCI e signals are sent to target hard disk by physical link.The application reduces physical link length, reduces backboard cost of manufacture, also improves the reliability and stability of storage system.
Description
Technical field
The application is related to computer realm, more particularly to a kind of method and device of dual control storage device access hard disk.
Background technology
NVMe (Non-Volatile Memory express, nonvolatile memory standard) hard disk is to use PCIe
SSD (the Solid State Drives, solid-state of (peripheral component interconnect express) passage
Hard disk) a kind of specification.NVMe hard disks are used for data storage, its power consumption compared to SAS (Serial Attached SCSI, serially
Connecting SCSI) hard disk is lower, and reduces access delay, and performance is higher.
In the storage system having high requirements to stability, generally use dual controller redundancy structure, when a control
When device breaks down, another controller can take over its business, lift the reliability of storage system.In addition, other portions
Part, such as power supply, battery, fan are Redundancy Design, and system ensures the data safety of user without Single Point of Faliure.
NVMe hard disks for dual controller redundancy structure are dual-port NVMe hard disks, and the dual controller of storage system is distinguished
Communicated by one of port with hard disk.
Participate in Fig. 1, be the application shown in a kind of storage device backboard structural representation, as shown in figure 1, on backboard
Dotted box portion is two controllers, and the part that alphabetical A and letter b are indicated is the main body of controller, including controller
CPU (Central Processing Unit, central processing unit), CPLD (Complex Programmable Logic
Device, CPLD) and BMC (Baseboard Management Controller, substrate management control
Device) etc. device；The other parts of controller are connector.Between two dotted line frames is the connector of hard disk, backboard it is another
50 dual-port NVMe hard disks are inserted in face.
Be the schematic diagram of device inserting on a kind of backboard shown in the application referring to Fig. 2, as shown in Fig. 2 when upper plate (on
The controller in face) by with lower plate (following controller) equally in the way of with DIP (dual inline-pin package, it is double
Row inline package) technology inserting on backboard when, because the connector of upper plate can penetrate backboard, this can cause the connection of upper plate
The connector of device and 1-25 hard disks is interfered, and referring to dotted line frame inside points, the connector in turn resulting in upper plate can not be fully-inserted
Backboard so that the device height of storage device is increased, and lifts cost.
It is the schematic diagram that device inserts on another backboard shown in the application, such as to solve the above problems, referring to Fig. 3
Shown in Fig. 3, upper plate inserts after 180 degree is overturn and arrives backboard so that upper plate square controller can avoid the connection of 1-25 hard disks
Device.After this mode inserts, the structure as shown in Fig. 1, the controller main body of upper plate is in the rightmost side, and the controller master of lower plate
Body is oppositely arranged in the leftmost side, two controllers on backboard.
Controller is communicated by the link between each connector and each hard disk with each hard disk；Wherein, link includes thing
Link and logical links are managed, what physical link referred to is exactly the physical connection of passive point-to-point, and logical links is exactly data link,
It is that physical link adds necessary communication control procedure.
Lower plate can be communicated by the link between the connector of each hard disk nearby and each hard disk with each hard disk, example
Such as, by taking Fig. 1 as an example, lower plate is communicated by connector 17 with No. 24, No. 25, No. 49 and No. 50 hard disks of the rightmost side, is passed through
Connector 1 is communicated with No. 1, No. 2, No. 26 and No. 27 hard disk of the leftmost side.And upper plate is inserted after upset into after backboard, on
The position of the connector of plate all changes, if upper plate is communicated still according to link before this with each hard disk, the thing used
Reason link can intersect.In this case, if to allow physical link not intersect, the physical link on backboard needs to divide
Layer printing, backboard cost of manufacture is added, and the machinability of backboard is reduced.In addition, upper plate according to link before this with
Each hard disk is communicated, and physical link is long, in actual applications, easily by environmental externality factor disturb, cause reliability and
Stability deficiency.
The content of the invention
In view of this, the application provides a kind of method and device of dual control storage device access hard disk, to reduce physics
Linkage length, avoid physical link from intersecting, so as to reduce backboard cost of manufacture, improve the reliability and stability of storage system.
Specifically, the application is achieved by the following technical solution：
A kind of method of dual control storage device access hard disk, applied to storage device, the backboard insertion of the storage device
Two controllers that multiple dual-port NVMe hard disks and presence are oppositely arranged, each connector and the backboard of each controller
Upper each hard disk is connected based on nearby principle；The pre-configured two link maps tables of each controller, wherein, the link maps table bag
The mapping relations of the mark of logical links and physical link are included, the logical links includes the disk position information of each hard disk；The side
Method includes：
The CPU of the controller receives I/O request；Wherein, the I/O request carries the disk position information of target hard disk；
The CPU of the controller is by specifying the link of the level signal selection on pin corresponding to the level signal
Mapping table；Wherein, the value of the level signal on the specified pin of different controllers is different；
The link maps table that disk position information searchings of the CPU of the controller in the I/O request is chosen, really
Surely correspond to the mark of the physical link of disk position information, and sent at a high speed to the target hard disk by the physical link
PCIe signals.
In the method for the dual control storage device access hard disk, methods described also includes：
The CPLD of the controller receives the target hard disk and inserts after the backboard signal in place sent；
Institutes of the CPLD of the controller by the level signal selection on the specified pin corresponding to the level signal
State link maps table；
The chain that identifier lookups of the CPLD of the controller based on the physical link for receiving the signal in place is chosen
Road mapping table, it is determined that the disk position information of the mark corresponding to the physical link；
The CPLD of the controller by the CPU of the signal in place and disk position information reporting to the controller, with
Determine that the target hard disk inserts the backboard by the CPU of the controller.
In the method for the dual control storage device access hard disk, methods described also includes：
The CPU of the controller receives the signal in place and disk position information of the target hard disk, to described
Electricity instruction in the CPLD transmissions of controller；Wherein, the upper electricity instruction carries the disk position information of the target hard disk；
The CPLD of the controller receives the upper electricity instruction, by specifying the level signal selection on pin to correspond to
The link maps table of the level signal；
The link that disk position information searchings of the CPLD of the controller in the upper electricity instruction is chosen reflects
Firing table, it is determined that the mark of the physical link corresponding to disk position information, and by the physical link to the target hard disk
Send power on signal.
In the method for the dual control storage device access hard disk, methods described also includes：
The CPU of the controller is after sending electricity instruction on described and reaching default interval duration, to the controller
CPLD sends release reset instruction；Wherein, the release reset instruction carries the disk position information of the target hard disk；
The CPLD of the controller receives the release reset instruction, by specifying the level signal selection pair on pin
Should be in the link maps table of the level signal；
The chain that the CPLD of the controller is chosen by the disk position information searching in the release reset instruction
Road mapping table, it is determined that the mark of the physical link corresponding to disk position information, and by the physical link to the target
Hard disk sends release reset signal.
In the method for the dual control storage device access hard disk, the CPU of the controller passes through LPC interfaces and the control
The CPLD of device processed is connected.
A kind of device of dual control storage device access hard disk, applied to storage device, the backboard insertion of the storage device
Two controllers that multiple dual-port NVMe hard disks and presence are oppositely arranged, each connector and the backboard of each controller
Upper each hard disk is connected based on nearby principle；The pre-configured two link maps tables of each controller, wherein, the link maps table bag
The mapping relations of the mark of logical links and physical link are included, the logical links includes the disk position information of each hard disk；The dress
Put including：
First receiving unit, for receiving I/O request；Wherein, the I/O request carries the disk position information of target hard disk；
First choice unit, for by specifying the chain of the level signal selection on pin corresponding to the level signal
Road mapping table；Wherein, the value of the level signal on the specified pin of different controllers is different；
First searching unit, the link maps table chosen for the disk position information searching in the I/O request,
It is determined that the mark of the physical link corresponding to disk position information, and height is sent to the target hard disk by the physical link
Fast PCIe signals.
In the device of the dual control storage device access hard disk, described device also includes：
Second receiving unit, the signal in place sent is inserted after the backboard for receiving the target hard disk；
Second selecting unit, for the institute by the level signal selection on the specified pin corresponding to the level signal
State link maps table；
Second searching unit, the chain chosen for the identifier lookup based on the physical link for receiving the signal in place
Road mapping table, it is determined that the disk position information of the mark corresponding to the physical link；
Reporting unit, for by the CPU of the signal in place and disk position information reporting to the controller, with by institute
The CPU for stating controller determines that the target hard disk inserts the backboard.
In the device of the dual control storage device access hard disk, described device also includes：
First receiving unit, it is further used for receiving the signal in place of the target hard disk and the disk position
Information, to the CPLD transmissions of the controller on electricity instruction；Wherein, the upper electricity instruction carries the disk position letter of the target hard disk
Breath；
Second receiving unit, it is further used for receiving the upper electricity instruction, by specifying the level on pin to believe
Number selection corresponding to the level signal the link maps table；
Second searching unit, it is further used for what the disk position information searching in the upper electricity instruction was chosen
The link maps table, it is determined that the mark of the physical link corresponding to disk position information, and by the physical link to institute
State target hard disk and send power on signal.
In the device of the dual control storage device access hard disk, described device also includes：
First receiving unit, it is further used for after sending electricity instruction on described and reaching default interval duration, to
The CPLD of the controller sends release reset instruction；Wherein, the release reset instruction carries the disk position of the target hard disk
Information；
Second receiving unit, it is further used for receiving the release reset instruction, by specifying the electricity on pin
Flat signal behavior corresponds to the link maps table of the level signal；
Second searching unit, it is further used for selecting by the disk position information searching in the release reset instruction
In the link maps table, it is determined that the mark of the physical link corresponding to disk position information, and pass through the physical link
Release reset signal is sent to the target hard disk.
In the device of the dual control storage device access hard disk, the CPU of the controller passes through LPC interfaces and the control
The CPLD of device processed is connected.
In technical scheme, on each connector and the backboard of two controllers on the backboard of storage device
Each hard disk connects nearby, the pre-configured two link maps tables of two controllers, wherein, the link maps table includes logical links
With the mapping relations of physical link, the logical links includes the disk position information of each hard disk；The CPU of the controller receives IO
Request, the I/O request carry the disk position information of target hard disk, and the CPU of the controller can be by specifying the level on pin to believe
Number selection corresponding to the level signal the link maps table, then the disk position information searching in above-mentioned I/O request is chosen
Above-mentioned link maps table, it is determined that the mark of the physical link corresponding to the disk position information, and by the physical link to above-mentioned mesh
Mark hard disk and send high-speed PCI e signals；
Because each connector of two controllers is connected with each hard disk based on nearby principle, the chain of the CPU selections of controller
Physical link corresponding with the disk position information of target hard disk is the most short thing that controller connects the target hard disk in the mapping table of road
Manage link；Be not in the physical link of intersection on backboard, physical link prints without layering, so as to reduce the thing of backboard
Linkage length is managed, reduces backboard cost of manufacture, also improves the reliability and stability of storage system.
Brief description of the drawings
Fig. 1 is a kind of structural representation of the backboard of storage device shown in the application；
Fig. 2 is the schematic diagram of device inserting on a kind of backboard shown in the application；
Fig. 3 is the schematic diagram of device inserting on another backboard shown in the application；
Fig. 4 is the connection diagram of device on a kind of backboard of storage device shown in the application；
Fig. 5 is a kind of flow chart of the method for dual control storage device access hard disk shown in the application；
Fig. 6 is a kind of embodiment block diagram of the device of dual control storage device access hard disk shown in the application.
Embodiment
In order that those skilled in the art more fully understand the technical scheme in the embodiment of the present invention, and make of the invention real
Apply the above-mentioned purpose of example, feature and advantage can be more obvious understandable, below in conjunction with the accompanying drawings to prior art and the present invention
Technical scheme in embodiment is described in further detail.
The upper plate of the backboard of storage device through 180 degree upset inserting on backboard, with lower plate on backboard in being oppositely arranged.
Lower plate can be communicated by the link between the connector of each hard disk nearby and each hard disk with each hard disk.Upper plate is through upset
Afterwards, the position of connector has changed, if communicated still according to original link with each hard disk, each connector with it is each hard
Physical link between disk can intersect.Still by taking Fig. 1 as an example, if upper plate is according to original link and No. 1 hard disk and No. 25
Hard disk is communicated, then is connected by connector 17 with No. 25 hard disks of the rightmost side, hard by No. 1 of connector 1 and the leftmost side
Disk connects, and now, two physical links can intersect.
If allowing physical link not intersect, the physical link on backboard needs to be layered printing, adds backboard making
Cost, and reduce the machinability of backboard.
In addition, upper plate is communicated according to original link with each hard disk, the physical link mistake between controller and hard disk
It is long, in actual applications, easily disturbed by environmental externality factor, cause the reliability and stability deficiency of storage system.
In view of this, the application provides a kind of method of dual control storage device access hard disk, each connector of controller with
Each hard disk is connected based on nearby principle on backboard, pre-configured two link maps tables on controller, wherein, above-mentioned link maps table
The mapping relations of mark including logical links and physical link, logical links include the disk position information of each hard disk；Controller can
With by specify pin on level signal selection corresponding to link maps table, then by the above-mentioned link maps table of selection
Physical link corresponding with the disk position information of target hard disk, signal is sent to above-mentioned target hard disk.
Be the connection diagram of device on a kind of backboard of storage device shown in the application referring to Fig. 4, wherein, CPU and
CPLD belongs to controller, and CPU is connected by LPC (low pin count) interface with CPLD；Dual-port NVMe hard disks include two
Individual port (A mouths and B mouths i.e. in figure), wherein, the two ports can be the SFF-8639 ports of standard.Two controllers point
It is not connected by two ports with dual-port NVMe hard disks.Each connector of controller is based on nearby principle with each hard disk on backboard
After connection, CPU the and CPLD cans of controller are connected nearby with each hard disk respectively；Wherein, CPU high-speed PCI e links are exactly
The physical link of CPU to connector adds connector to the physical link of hard disk, and CPLD low speed signal link is exactly that CPLD is arrived
Physical link of the physical link of connector plus connector to hard disk.
Continuing with referring to Fig. 5, for a kind of method of dual control storage device access hard disk shown in the application, methods described should
For the controller of storage device, multiple dual-port NVMe hard disks are inserted on the backboard of the memory and have what is be oppositely arranged
Two controllers, each connector of each controller are connected with each hard disk on backboard based on nearby principle；Each controller is prewired
Two link maps tables are put, wherein, above-mentioned link maps table includes the mapping relations of the mark of logical links and physical link, on
Stating logical links includes the disk position information of each hard disk；It the described method comprises the following steps：
Step 501：The CPU of the controller receives I/O request；Wherein, the I/O request carries the disk position of target hard disk
Information.
Step 502：The CPU of the controller is by specifying the level signal selection on pin corresponding to the level signal
The link maps table；Wherein, the value of the level signal on the specified pin of different controllers is different.
Step 503：The link that disk position information searchings of the CPU of the controller in the I/O request is chosen reflects
Firing table, it is determined that the mark of the physical link corresponding to disk position information, and by the physical link to the target hard disk
Send high-speed PCI e signals.
Wherein, above-mentioned nearby principle can be default length range (such as：5 centimetres), if the connector of controller
Distance with the connector of hard disk then can be connected two connectors with physical link within 5 centimetres.In practical application
In, corresponding adjustment can also be done according to the device position of backboard, flexibly with nearby principle.
Still illustrated by taking Fig. 1 as an example, the connector of the connector of each controller and each hard disk is carried out based on nearby principle
After connection, the connector 17 of upper plate can connect No. 1 hard disk and No. 26 hard disks, connector 16 can connect No. 2, No. 3, No. 27 and
No. 28 hard disks, connector 15 can connect No. 4 and No. 29 hard disks, and by that analogy, connector 2 connects No. 22, No. 23, No. 47 and 48
Number hard disk, connector 1 connect No. 24, No. 25, No. 49 and No. 50 hard disks；
The connector 1 of lower plate can connect No. 1, No. 2, No. 26 and No. 27 hard disk, connector 2 can connect No. 3, No. 4,28
Number and No. 29 hard disks, by that analogy, connector 16 connect No. 23, No. 24, No. 48 and No. 49 hard disks, connector 17 connect No. 25 and
No. 50 hard disks.
Two controllers distinguish pre-configured two link maps tables, and two link maps tables correspond to upper plate and lower plate respectively,
Link maps table includes the mapping relations of the logical links of each hard disk and the mark of physical link；Wherein, logical links includes
The disk position information of hard disk and other necessary communication control procedures, the disk position information may indicate that position of the hard disk on backboard.Control
Device can correctly identify the mark of physical link, so as to select corresponding physical link.
Still by taking Fig. 1 as an example, the mark of physical link can be 1 to 50 sequence number, correspond to controller connection hard disk respectively
50 physical links.It is pointed out that because upper plate is different with the connected mode of lower plate, in two link maps tables, together
Physical link corresponding to the disk position information of one hard disk is different, such as, No. 1 hard disk is in link maps table corresponding with upper plate
In the mark of corresponding physical link be 50, and the mark of corresponding physical link is in link maps table corresponding with lower plate
1。
Backboard can be respectively to the specified pin transmission level signal of two controllers, and the level signal of upper plate and lower plate is not
Together.Such as：Upper plate is high level, and lower plate is low level.Can be with pre-configured link maps table and level signal on controller
Mapping relations, subsequent controllers can be based on link maps tables corresponding to the level signal selection read.
In the embodiment of the present application, after dual-port NVMe hard disks are inserted on backboard, can be sent respectively to two controllers
Signal in place.The CPLD of controller receives above-mentioned signal in place, then can be according to the physics chain for receiving above-mentioned signal in place
The mark on road, searched in pre-configured above-mentioned link maps table.
Specifically, CPLD is firstly the need of the level signal for reading specified pin, then according to the level signal choosing read
The link maps table corresponding to the level signal is selected, and the mark for the physical link for receiving above-mentioned signal in place is reflected in the link
Searched in firing table, it is determined that the disk position information of the mark corresponding to the physical link.
CPLD can be by the CPU of the disk position information found and above-mentioned signal reporting in place to controller.CPU is received
After stating disk position information and above-mentioned signal in place, it may be determined that have target hard disk insertion in the disk position of above-mentioned disk position information instruction.
In the embodiment of the present application, CPU can enter after above-mentioned signal in place is received to the target hard disk for inserting backboard
It is electric on row.CPU can be instructed by LPC interfaces to electricity in CPLD transmissions；Wherein, electricity instruction carries above-mentioned target hard disk on this
Disk position information.
CPLD receives above-mentioned upper electricity instruction, the level signal for specifying pin is read first, then according to the electricity read
Link maps table corresponding to flat signal behavior, and the disk position information in above-mentioned upper electricity instruction is searched in the link maps table,
It is determined that the mark of the physical link corresponding to above-mentioned disk position information.CPLD can determine physical link based on the mark found,
And power on signal is sent to above-mentioned target hard disk by the physical link.
Illustrated by taking Fig. 1 as an example, on the one hand, if the CPU of upper plate receives the disk position information of No. 1 hard disk and letter in place
Breath, the upper electricity instruction for carrying the disk position information can be sent to the CPLD of upper plate by LPC interfaces.CPLD receives electricity on this and referred to
Order, the link maps table corresponding to upper plate can be selected according to the level signal of specified pin, then according to the disk position of No. 1 hard disk
The information searching link maps table, it is determined that the mark of corresponding physical link is 50, then CPLD can by be identified as 50 thing
Manage No. 1 hard disk of chain road direction and send power on signal.
On the other hand, if the CPU of lower plate receives the disk position information of No. 1 hard disk and information in place, can be connect by LPC
Mouth sends the upper electricity instruction for carrying the disk position information to the CPLD of lower plate.CPLD receives electricity instruction on this, can be according to specified
The level information selection of pin corresponding to lower plate link maps table, then according to the disk position information searching of No. 1 hard disk link
Mapping table, it is determined that the mark of corresponding physical link is 1, then CPLD can be sent out by being identified as 1 physical link to No. 1 hard disk
Serve electric signal.
Above-mentioned target hard disk receives power on signal, and successfully after upper electricity, acquiescence is in reset state, if controller is follow-up
Further to above-mentioned target hard disk to be operated, then above-mentioned target hard disk can be discharged and resetted.
In the embodiment of the present application, can be with predetermined interval duration on the CPU of controller noted above, the interval duration characterizes above-mentioned
The time waited is needed in the CPU transmissions of controller after electricity instruction.It is pre-configured that practical situations progress can be based on, such as,
The interval duration is set to 500 milliseconds., can be with after the CPU of controller noted above sends the upper electricity instruction for above-mentioned target hard disk
Timing is carried out, and after default above-mentioned interval duration is reached, release reset instruction is sent to CPLD by LPC interfaces；Wherein,
The release reset instruction carries the disk position information of above-mentioned target hard disk.
CPLD receives above-mentioned release reset instruction, reads the level signal for specifying pin first, and then basis is read
Level signal selection corresponding to link maps table, and by the disk position information in above-mentioned release reset instruction in the link maps table
Middle lookup, it is determined that the mark of the physical link corresponding to above-mentioned disk position information.CPLD can determine thing based on the mark found
Link is managed, and release reset signal is sent to above-mentioned target hard disk by the physical link, target hard disk is released so as to realize
Put reset processing.
After controller carries out release reset to above-mentioned target hard disk, the IO that can subsequently handle for above-mentioned target hard disk is asked
Ask.
In the embodiment of the present application, can be with when the upper layer software (applications) of storage device stores to target hard disk or obtains data
I/O request is sent to controller；Wherein, above-mentioned I/O request carries the disk position information of target hard disk.The CPU of controller noted above is received
To above-mentioned I/O request.
In the embodiment of the present application, after the CPU of controller noted above receives I/O request, controller noted above can be read first
Specified pin level signal, the controller that the level signal for being then based on reading determines residing for itself be upper plate or under
Plate, and then the link maps table according to the level signal selection read corresponding to the level signal.Due to prewired on controller
Level signal and the mapping relations of link maps table are put, CPU can choose link maps table corresponding to affiliated controller.
In the embodiment of the present application, the CPU of controller noted above can be according to the disk position information searching choosing in above-mentioned I/O request
In above-mentioned link maps table, it is determined that the mark of the physical link corresponding to above-mentioned disk position information.CPU can be according to finding
Physical link sends PCIe high speed signals to target.Wherein, the PCIe high speed signals can be data-signal.
Still illustrated by taking Fig. 1 as an example, on the one hand, can if the CPU of upper plate receives the I/O request for No. 1 hard disk
, then should according to the disk position information searching of No. 1 hard disk with the link maps table according to corresponding to the level signal selection for specifying pin
Link maps table, it is determined that the mark of corresponding physical link is 50, then the CPU of upper plate can by be identified as 50 physical link
PCIe high speed signals are sent to No. 1 hard disk.
On the other hand, can be according to the electricity of specified pin if the CPU of lower plate receives the I/O request for No. 1 hard disk
Link maps table corresponding to flat signal behavior, then according to the disk position information searching of No. 1 hard disk link maps table, it is determined that corresponding
The mark of physical link be 1, then the CPU of lower plate can send PCIe at a high speed by being identified as 1 physical link to No. 1 hard disk
Signal.
In summary, in technical scheme, the backboard of storage device inserts multiple dual-port NVMe hard disks, backboard
Upper two controllers being oppositely arranged to be present, each connector of each controller is connected with each hard disk on backboard based on nearby principle
Connect；The pre-configured two link maps tables of each controller, two link maps tables correspond to the upper plate (control above of backboard respectively
Device) and lower plate (following controller), the mapping relations of mark of each link maps table including logical links and physical link；
The CPU of controller receives I/O request, and above-mentioned I/O request carries the disk position information of target hard disk, controller noted above
The link maps table that CPU can correspond to the level signal by specifying the level signal on pin to select, wherein, different controls
The value of level signal on the above-mentioned specified pin of device processed is different；The CPU of controller noted above can be according in above-mentioned I/O request
The selection of disk position information searching above-mentioned link maps table, it is determined that the mark of the physical link corresponding to the disk position information, and lead to
Cross above-mentioned physical link and send high-speed PCI e signals to above-mentioned target hard disk；
Because each connector of two controllers is connected with each hard disk based on nearby principle, the link maps that controller is chosen
Physical link corresponding with the disk position information of target hard disk is the most short physical link that controller connects the target hard disk in table；
In addition, the CPLD of controller receives upper the electricity instruction or release reset instruction of CPU transmissions, again may be by referring to
Level signal selection on fixed tube pin corresponds to the link maps table of the level signal, and is instructed according to upper electricity or discharge reset and referred to
The disk position information searching of the carrying link maps table is made, so as to select corresponding physical link to be communicated with target hard disk；
Because the upper plate of backboard and each connector of lower plate are connected with each hard disk based on nearby principle, be not on backboard
The physical link of intersection, physical link print without layering, so as to reduce the length of physical link, and reduce backboard
Cost of manufacture, also improve the reliability and stability of storage system.
Corresponding with the embodiment of the method for foregoing dual control storage device access hard disk, present invention also provides dual control storage
The embodiment of the device of equipment access hard disk.
Fig. 6 is refer to, should for a kind of embodiment block diagram of the device of dual control storage device access hard disk shown in the application
The device 60 of dual control storage device access hard disk includes：
First receiving unit 610, for receiving I/O request；Wherein, the I/O request carries the disk position letter of target hard disk
Breath.
First choice unit 620, for by specifying institute of the level signal selection on pin corresponding to the level signal
State link maps table；Wherein, the value of the level signal on the specified pin of different controllers is different.
First searching unit 630, the link maps chosen for the disk position information searching in the I/O request
Table, it is determined that the mark of the physical link corresponding to disk position information, and sent out by the physical link to the target hard disk
Send high-speed PCI e signals.
In this example, described device also includes：
The (not shown) of second receiving unit 640, sent for receiving after the target hard disk inserts the backboard
Signal in place.
The (not shown) of second selecting unit 650, it is corresponding for being selected by the level signal on the specified pin
In the link maps table of the level signal.
The (not shown) of second searching unit 660, for the mark based on the physical link for receiving the signal in place
The link maps table chosen is searched, it is determined that the disk position information of the mark corresponding to the physical link.
The (not shown) of reporting unit 670, for by the signal in place and disk position information reporting to the control
The CPU of device processed, determine that the target hard disk inserts the backboard with the CPU by the controller.
In this example, described device also includes：
First receiving unit 610, it is further used for receiving the signal in place of the target hard disk and described
Disk position information, to the CPLD transmissions of the controller on electricity instruction；Wherein, the upper electricity instruction carries the disk of the target hard disk
Position information.
The (not shown) of second receiving unit 640, it is further used for receiving the upper electricity instruction, by specifying
Level signal selection on pin corresponds to the link maps table of the level signal.
The (not shown) of second searching unit 660, the disk being further used in the upper electricity instruction
The link maps table that position information searching is chosen, it is determined that the mark of the physical link corresponding to disk position information, and pass through
The physical link sends power on signal to the target hard disk.
In this example, described device also includes：
First receiving unit 610, it is further used for after sending electricity instruction on described and reaching default interval duration,
Release reset instruction is sent to the CPLD of the controller；Wherein, the release reset instruction carries the disk of the target hard disk
Position information；
The (not shown) of second receiving unit 640, it is further used for receiving the release reset instruction, passes through
Specify the link maps table of the level signal selection on pin corresponding to the level signal；
The (not shown) of second searching unit 660, it is further used for by the institute in the release reset instruction
The link maps table that disk position information searching is chosen is stated, it is determined that the mark of the physical link corresponding to disk position information, and
Release reset signal is sent to the target hard disk by the physical link.
In this example, the CPU of the controller is connected by LPC interfaces with the CPLD of the controller.
The function of unit and the implementation process of effect specifically refer to and step are corresponded in the above method in said apparatus
Implementation process, it will not be repeated here.
For device embodiment, because it corresponds essentially to embodiment of the method, so related part is real referring to method
Apply the part explanation of example.Device embodiment described above is only schematical, wherein described be used as separating component
The unit of explanation can be or may not be physically separate, can be as the part that unit is shown or can also
It is not physical location, you can with positioned at a place, or can also be distributed on multiple NEs.Can be according to reality
Need to select some or all of module therein to realize the purpose of application scheme.Those of ordinary skill in the art are not paying
In the case of going out creative work, you can to understand and implement.
The preferred embodiment of the application is the foregoing is only, not limiting the application, all essences in the application
God any modification, equivalent substitution and improvements done etc., should be included within the scope of the application protection with principle.
Claims (10)
- A kind of 1. method of dual control storage device access hard disk, applied to storage device, it is characterised in that the storage device Backboard inserts multiple dual-port NVMe hard disks and two controllers being oppositely arranged be present, each connector of each controller with Each hard disk is connected based on nearby principle on the backboard；The pre-configured two link maps tables of each controller, wherein, the link Mapping table includes the mapping relations of the mark of logical links and physical link, and the disk position that the logical links includes each hard disk is believed Breath；Methods described includes：The CPU of the controller receives I/O request；Wherein, the I/O request carries the disk position information of target hard disk；The CPU of the controller is by specifying the link maps of the level signal selection on pin corresponding to the level signal Table；Wherein, the value of the level signal on the specified pin of different controllers is different；The link maps table that disk position information searchings of the CPU of the controller in the I/O request is chosen, it is determined that pair The mark of the physical link of disk position information described in Ying Yu, and high-speed PCI e is sent to the target hard disk by the physical link Signal.
- 2. according to the method for claim 1, it is characterised in that methods described also includes：The CPLD of the controller receives the target hard disk and inserts after the backboard signal in place sent；The chains of the CPLD of the controller by the level signal selection on the specified pin corresponding to the level signal Road mapping table；The link that identifier lookups of the CPLD of the controller based on the physical link for receiving the signal in place is chosen reflects Firing table, it is determined that the disk position information of the mark corresponding to the physical link；The CPLD of the controller is by the CPU of the signal in place and disk position information reporting to the controller, with by institute The CPU for stating controller determines that the target hard disk inserts the backboard.
- 3. according to the method for claim 2, it is characterised in that methods described also includes：The CPU of the controller receives the signal in place and disk position information of the target hard disk, to the control Electricity instruction in the CPLD transmissions of device；Wherein, the upper electricity instruction carries the disk position information of the target hard disk；The CPLD of the controller receives the upper electricity instruction, by specifying the level signal selection on pin to correspond to the electricity The link maps table of ordinary mail number；The link maps table that disk position information searchings of the CPLD of the controller in the upper electricity instruction is chosen, It is determined that the mark of the physical link corresponding to disk position information, and sent by the physical link to the target hard disk Electric signal.
- 4. according to the method for claim 3, it is characterised in that methods described also includes：The CPU of the controller is after sending electricity instruction on described and reaching default interval duration, to the CPLD of the controller Send release reset instruction；Wherein, the release reset instruction carries the disk position information of the target hard disk；The CPLD of the controller receives the release reset instruction, by specifying the level signal selection on pin to correspond to The link maps table of the level signal；The link that the CPLD of the controller is chosen by the disk position information searching in the release reset instruction reflects Firing table, it is determined that the mark of the physical link corresponding to disk position information, and by the physical link to the target hard disk Send release reset signal.
- 5. according to the method for claim 4, it is characterised in that the CPU of the controller by low pin count LPC interfaces with The CPLD of the controller is connected.
- A kind of 6. device of dual control storage device access hard disk, applied to storage device, it is characterised in that the storage device Backboard inserts multiple dual-port NVMe hard disks and two controllers being oppositely arranged be present, each connector of each controller with Each hard disk is connected based on nearby principle on the backboard；The pre-configured two link maps tables of each controller, wherein, the link Mapping table includes the mapping relations of the mark of logical links and physical link, and the disk position that the logical links includes each hard disk is believed Breath；Described device includes：First receiving unit, for receiving I/O request；Wherein, the I/O request carries the disk position information of target hard disk；First choice unit, for by specifying the level signal selection on pin to be reflected corresponding to the link of the level signal Firing table；Wherein, the value of the level signal on the specified pin of different controllers is different；First searching unit, the link maps table chosen for the disk position information searching in the I/O request, it is determined that Sent at a high speed to the target hard disk corresponding to the mark of the physical link of disk position information, and by the physical link PCIe signals.
- 7. device according to claim 6, it is characterised in that described device also includes：Second receiving unit, the signal in place sent is inserted after the backboard for receiving the target hard disk；Second selecting unit, for the chain by the level signal selection on the specified pin corresponding to the level signal Road mapping table；Second searching unit, the link chosen for the identifier lookup based on the physical link for receiving the signal in place reflect Firing table, it is determined that the disk position information of the mark corresponding to the physical link；Reporting unit, for by the CPU of the signal in place and disk position information reporting to the controller, with by the control The CPU of device processed determines that the target hard disk inserts the backboard.
- 8. device according to claim 7, it is characterised in that described device also includes：First receiving unit, it is further used for receiving the signal in place and disk position letter of the target hard disk Breath, it is upper electric to CPLD transmission of the controller to instruct；Wherein, the upper electricity instruction carries the disk position letter of the target hard disk Breath；Second receiving unit, it is further used for receiving the upper electricity instruction, by specifying the level signal on pin to select Select the link maps table corresponding to the level signal；Second searching unit, be further used for according to it is described it is upper electricity instruction in disk position information searching choose described in Link maps table, it is determined that the mark of the physical link corresponding to disk position information, and by the physical link to the mesh Mark hard disk and send power on signal.
- 9. device according to claim 8, it is characterised in that described device also includes：First receiving unit, it is further used for after sending electricity instruction on described and reaching default interval duration, to described The CPLD of controller sends release reset instruction；Wherein, the release reset instruction carries the disk position information of the target hard disk；Second receiving unit, it is further used for receiving the release reset instruction, by specifying the level on pin to believe Number selection corresponding to the level signal the link maps table；Second searching unit, it is further used for what is chosen by the disk position information searching in the release reset instruction The link maps table, it is determined that the mark of the physical link corresponding to disk position information, and by the physical link to institute State target hard disk and send release reset signal.
- 10. device according to claim 9, it is characterised in that the CPU of the controller passes through LPC interfaces and the control The CPLD of device processed is connected.
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| CN201711160024.3A CN107817953B (en) | 2017-11-20 | 2017-11-20 | Method and device for accessing hard disk by double-control storage equipment |
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| CN201711160024.3A CN107817953B (en) | 2017-11-20 | 2017-11-20 | Method and device for accessing hard disk by double-control storage equipment |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109032851A (en) * | 2018-06-26 | 2018-12-18 | 华为技术有限公司 | A kind of link failure determines method and apparatus |
| CN109407998A (en) * | 2018-11-09 | 2019-03-01 | 郑州云海信息技术有限公司 | IO stream synchronous method, system and associated component in a kind of caching |
| CN110389918A (en) * | 2018-04-18 | 2019-10-29 | 纬颖科技服务股份有限公司 | Hot plug recognition methods and server with hot plug identification function |
| CN110806989A (en) * | 2018-08-06 | 2020-02-18 | 浙江宇视科技有限公司 | Storage server |
| CN112162706A (en) * | 2020-09-30 | 2021-01-01 | 新华三云计算技术有限公司 | Hard disk management method, device, equipment and machine readable storage medium |
| CN112306409A (en) * | 2018-06-27 | 2021-02-02 | 华为技术有限公司 | Storage system and disk |
| CN113688084A (en) * | 2021-07-22 | 2021-11-23 | 苏州浪潮智能科技有限公司 | Circuit, method and storage medium for realizing automatic allocation of PCIE (peripheral component interface express) resources |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719051A (en) * | 2009-11-09 | 2010-06-02 | 中兴通讯股份有限公司 | Multi-control disk array and implementation method thereof |
| CN101833522A (en) * | 2010-03-31 | 2010-09-15 | 杭州华三通信技术有限公司 | Communication method and equipment of SAS (Serial Attached SCSI) link |
| CN104011691A (en) * | 2011-12-29 | 2014-08-27 | 英特尔公司 | Non-volatile ram disk |
| US20140337540A1 (en) * | 2013-05-08 | 2014-11-13 | Lsi Corporation | METHOD AND SYSTEM FOR I/O FLOW MANAGEMENT FOR PCIe DEVICES |
| CN104426814A (en) * | 2013-08-30 | 2015-03-18 | 英特尔公司 | Numa node peripheral switch |
| CN106326171A (en) * | 2016-08-24 | 2017-01-11 | 联想(北京)有限公司 | Method and device for recognizing hard disk type of hard disk back plate |
| CN106326154A (en) * | 2016-08-09 | 2017-01-11 | 杭州宏杉科技有限公司 | Control circuit and control method of hard disk address |
| CN106919531A (en) * | 2015-12-25 | 2017-07-04 | 华为技术有限公司 | Exchange method and equipment based on non-volatile memories bus protocol |
-
2017
- 2017-11-20 CN CN201711160024.3A patent/CN107817953B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719051A (en) * | 2009-11-09 | 2010-06-02 | 中兴通讯股份有限公司 | Multi-control disk array and implementation method thereof |
| CN101833522A (en) * | 2010-03-31 | 2010-09-15 | 杭州华三通信技术有限公司 | Communication method and equipment of SAS (Serial Attached SCSI) link |
| CN104011691A (en) * | 2011-12-29 | 2014-08-27 | 英特尔公司 | Non-volatile ram disk |
| US20140337540A1 (en) * | 2013-05-08 | 2014-11-13 | Lsi Corporation | METHOD AND SYSTEM FOR I/O FLOW MANAGEMENT FOR PCIe DEVICES |
| CN104426814A (en) * | 2013-08-30 | 2015-03-18 | 英特尔公司 | Numa node peripheral switch |
| CN106919531A (en) * | 2015-12-25 | 2017-07-04 | 华为技术有限公司 | Exchange method and equipment based on non-volatile memories bus protocol |
| CN106326154A (en) * | 2016-08-09 | 2017-01-11 | 杭州宏杉科技有限公司 | Control circuit and control method of hard disk address |
| CN106326171A (en) * | 2016-08-24 | 2017-01-11 | 联想(北京)有限公司 | Method and device for recognizing hard disk type of hard disk back plate |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110389918A (en) * | 2018-04-18 | 2019-10-29 | 纬颖科技服务股份有限公司 | Hot plug recognition methods and server with hot plug identification function |
| CN110389918B (en) * | 2018-04-18 | 2021-03-12 | 纬颖科技服务股份有限公司 | Hot plug identification method and server with hot plug identification function |
| CN109032851A (en) * | 2018-06-26 | 2018-12-18 | 华为技术有限公司 | A kind of link failure determines method and apparatus |
| CN109032851B (en) * | 2018-06-26 | 2021-01-12 | 华为技术有限公司 | Link fault determination method and device |
| US11275699B2 (en) | 2018-06-27 | 2022-03-15 | Huawei Technologies Co., Ltd. | Storage system and method for switching working mode of storage system |
| US11550739B2 (en) | 2018-06-27 | 2023-01-10 | Huawei Technologies Co., Ltd. | Storage system and method for switching working mode of storage system |
| CN112306409B (en) * | 2018-06-27 | 2022-09-09 | 华为技术有限公司 | Storage system and disk |
| CN112306409A (en) * | 2018-06-27 | 2021-02-02 | 华为技术有限公司 | Storage system and disk |
| CN110806989A (en) * | 2018-08-06 | 2020-02-18 | 浙江宇视科技有限公司 | Storage server |
| CN109407998B (en) * | 2018-11-09 | 2022-02-18 | 郑州云海信息技术有限公司 | Method, system and related assembly for IO stream synchronization in cache |
| CN109407998A (en) * | 2018-11-09 | 2019-03-01 | 郑州云海信息技术有限公司 | IO stream synchronous method, system and associated component in a kind of caching |
| CN112162706A (en) * | 2020-09-30 | 2021-01-01 | 新华三云计算技术有限公司 | Hard disk management method, device, equipment and machine readable storage medium |
| CN113688084A (en) * | 2021-07-22 | 2021-11-23 | 苏州浪潮智能科技有限公司 | Circuit, method and storage medium for realizing automatic allocation of PCIE (peripheral component interface express) resources |
| CN113688084B (en) * | 2021-07-22 | 2023-08-22 | 苏州浪潮智能科技有限公司 | Circuit, method and storage medium for realizing PCIE resource automatic allocation |
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