CN107817870A - Clock signal transfer method and device, Clock Tree, chip, electronic equipment - Google Patents
Clock signal transfer method and device, Clock Tree, chip, electronic equipment Download PDFInfo
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- CN107817870A CN107817870A CN201710961866.2A CN201710961866A CN107817870A CN 107817870 A CN107817870 A CN 107817870A CN 201710961866 A CN201710961866 A CN 201710961866A CN 107817870 A CN107817870 A CN 107817870A
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- clock
- clock signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- Theoretical Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
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Abstract
The embodiment of the invention discloses a kind of clock signal transfer method and device, Clock Tree, chip, electronic equipment, wherein, method includes：Clock signal caused by clock source is transferred at least one buffer respectively；Clock signal transmission is given to corresponding sub-clock tree by buffer, realizes the sequential inspection of core calculations unit in chip.The clock signal transfer method and device, Clock Tree, chip, electronic equipment provided based on the above embodiment of the present invention, by the way that clock signal caused by clock source is transferred at least one buffer respectively, clock signal transmission is given to corresponding sub-clock tree by buffer, realizes the sequential inspection of core calculations unit in chip；Due to having simplified the quantity of buffer, and by buffer control sub-clock tree, being uniformly controlled for sequential inspection is realized, makes the non-publicly-owned clock path between core calculations unit all very short, it is suppressed that the consumption on Clock Tree.
Description
Technical field
The present invention relates to data processing technique, especially a kind of clock signal transfer method and device, Clock Tree, chip,
Electronic equipment.
Background technology
At present, industry has many chips all comprising substantial amounts of multiplexing core, especially for display chip, artificial intelligence core
Piece and digital cash dig ore deposit chip.Between multiple multiplexing cores of such chip, generally require to synchronize sequential inspection.
During the present invention is realized, inventor has found, prior art at least has problems with：
For some complicated applications, a core generally requires to carry out sequential inspection with other all cores of surrounding.
This requires all cores to be on a synchronised clock tree, and the non-publicly-owned clock path between any pair of core is all
Must be very short, otherwise the loss on Clock Tree is excessive, and sequential can not meet.
The content of the invention
A technical problem to be solved of the embodiment of the present invention is：A kind of clock signal Transfer Technology is provided.
A kind of clock signal transfer method provided in an embodiment of the present invention, including：
Clock signal caused by clock source is transferred at least one buffer respectively；Each buffer control one
Sub-clock tree, each buffer correspond to a multiplexing core in chip；The multiplexing core includes at least one core
Computing unit；
Clock signal transmission is given to corresponding sub-clock tree by the buffer, realizes core calculations unit in chip
Sequential inspection.
In another embodiment based on the above method of the present invention, each chip includes at least one multiplexing core
The heart, each corresponding sub-clock tree of multiplexing core.
It is described to pass clock signal caused by clock source respectively in another embodiment based on the above method of the present invention
It is defeated by least one buffer, including：
Clock signal caused by clock source is transferred at least one buffer by Clock grid, by being transferred to buffering
Multiplexing core corresponding to clock signal driving in area, the Clock grid include at least one buffer.
In another embodiment based on the above method of the present invention, the Clock grid is formed using metal wire.
In another embodiment based on the above method of the present invention, the Clock grid be arranged on two layers power grid it
Between.
In another embodiment based on the above method of the present invention, the Clock grid sets thickness in the chips
More than or equal to the metal level of preset value.
Other side according to embodiments of the present invention, there is provided a kind of clock signal transfer device, including：
Signal generation unit, for clock signal caused by clock source to be transferred at least one buffer respectively；Each
Described one sub- Clock Tree of buffer control, each buffer correspond to a multiplexing core in chip；The multiplexing core
Pericardium includes at least one core calculations unit；
Sequential inspection unit, for giving clock signal transmission to corresponding sub-clock tree by the buffer, realize core
The sequential inspection of core calculations unit in piece.
In another embodiment based on said apparatus of the present invention, each chip includes at least one multiplexing core
The heart, each corresponding sub-clock tree of multiplexing core.
In another embodiment based on said apparatus of the present invention, the signal generation unit, specifically for by clock
Clock signal caused by source is transferred at least one buffer by Clock grid, passes through the clock signal being transferred in buffering area
Multiplexing core, the Clock grid include at least one buffer corresponding to driving.
In another embodiment based on said apparatus of the present invention, the Clock grid is formed using metal wire.
In another embodiment based on said apparatus of the present invention, the Clock grid be arranged on two layers power grid it
Between.
In another embodiment based on said apparatus of the present invention, the Clock grid sets thickness in the chips
More than or equal to the metal level of preset value.
Other side according to embodiments of the present invention, there is provided a kind of Clock Tree, including：
Clock source, for producing clock signal；
Clock grid, pass through Buffer transfer to all sub-clocks for receiving clock signal, and by the clock signal
Tree；
At least one sub-clock tree, for receiving clock signal, and the core to being multiplexed corresponding to sub- Clock Tree in core
Computing unit carries out sequential inspection.
In another embodiment based on the above-mentioned Clock Tree of the present invention, the Clock grid includes at least one buffering
Device.
Other side according to embodiments of the present invention, there is provided a kind of chip, including：Multiple layer metal line；The multilayer
Metal wire includes at least one layer of upper strata metal wire and at least one layer of lower metal line；
Also include：
Power grid, it is arranged in the upper strata metal wire of chip, for transmitting current signal；
Signal wire winding, it is arranged in the lower metal line of chip, for transmitting information signal；
Clock Tree as described above, the Clock grid in the Clock Tree is arranged between two layers of power grid.
Other side according to embodiments of the present invention, there is provided a kind of electronic equipment, including：Clock letter as described above
Number transfer device or chip as described above.
Other side according to embodiments of the present invention, there is provided a kind of electronic equipment, including：Memory, for storing
Executable instruction；
And processor, it is as described above so as to complete for performing the executable instruction with the memory communication
The operation of clock signal transfer method.
The clock signal transfer method and device, Clock Tree, chip, electronics provided based on the above embodiment of the present invention is set
It is standby, by the way that clock signal caused by clock source is transferred at least one buffer respectively, clock signal is passed by buffer
Sub-clock tree, realizes the sequential inspection of core calculations unit in chip corresponding to being defeated by；Due to having simplified the quantity of buffer, and
And by buffer control sub-clock tree, being uniformly controlled for sequential inspection is realized, when making non-publicly-owned between core calculations unit
Clock path is all very short, it is suppressed that the consumption on Clock Tree.
Below by drawings and examples, technical scheme is described in further detail.
Brief description of the drawings
The accompanying drawing of a part for constitution instruction describes embodiments of the invention, and is used to explain together with description
The principle of the present invention.
Referring to the drawings, according to following detailed description, the present invention can be more clearly understood, wherein：
Fig. 1 is the flow chart of clock signal transfer method one embodiment of the present invention.
Fig. 2 is the cross-sectional view of part real chip.
Fig. 3 is the structural representation of clock signal transfer device one embodiment of the present invention.
Embodiment
The various exemplary embodiments of the present invention are described in detail now with reference to accompanying drawing.It should be noted that：Unless have in addition
Body illustrates that the unlimited system of part and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The scope of invention.
Simultaneously, it should be appreciated that for the ease of description, the size of the various pieces shown in accompanying drawing is not according to reality
Proportionate relationship draw.
The description only actually at least one exemplary embodiment is illustrative to be never used as to the present invention below
And its application or any restrictions that use.
It may be not discussed in detail for technology, method and apparatus known to person of ordinary skill in the relevant, but suitable
In the case of, the technology, method and apparatus should be considered as part for specification.
It should be noted that：Similar label and letter represents similar terms in following accompanying drawing, therefore, once a certain Xiang Yi
It is defined, then it need not be further discussed in subsequent accompanying drawing in individual accompanying drawing.
The embodiment of the present invention can apply to computer system/server, and it can be with numerous other universal or special calculating
System environments or configuration operate together.Suitable for be used together with computer system/server well-known computing system, ring
The example of border and/or configuration includes but is not limited to：Personal computer system, server computer system, thin client, thick client
Machine, hand-held or laptop devices, the system based on microprocessor, set top box, programmable consumer electronics, NetPC Network PC,
Minicomputer system, large computer system and distributed cloud computing technology environment including any of the above described system, etc..
Computer system/server can be in computer system executable instruction (such as journey performed by computer system
Sequence module) general linguistic context under describe.Generally, program module can include routine, program, target program, component, logic, number
According to structure etc., they perform specific task or realize specific abstract data type.Computer system/server can be with
Implement in distributed cloud computing environment, in distributed cloud computing environment, task is by by the long-range of communication network links
Manage what equipment performed.In distributed cloud computing environment, program module can be located at the Local or Remote meter for including storage device
In calculation system storage medium.
The Clock grid proposed in the prior art, since clock source, buffer and sequential operation unit are connected, fallen
Insertion one is thrown the net lattice after the arithmetic element of the number second level.This lattice of throwing the net is made up of metal wire, and is connected between metal wire.Work as clock
Signal transmits, and by the caching of one-level one-level, drives this lattice of throwing the net jointly, finally, has thousands of individual sequential operation units to connect
It is connected on small grid.
First, Clock grid is made up of metal wire, and metal wire initially has two work in the chips, and one is power net
Lattice, it is connected on each unit.On the other hand signal wire is acted as.Because metal wire has certain limitation in dense degree,
So metal wire resource is used for meeting power grid and signal wire winding substantially, the space of very little is only stayed to be used for realizing other work(
Energy.
Secondly, the metal on Clock grid has a parasitic capacitance, Clock Tree will ceaselessly charge and discharge, intensive Clock grid
Substantial amounts of parasitic capacitance is brought, power consumption is significantly increased.
Again, after chip adds power grid, original timing analysis tool failure, method network structure can only be carried
Take out, with emulation mode, be computed correctly sequential quality.
Fig. 1 is the flow chart of clock signal transfer method one embodiment of the present invention.As shown in figure 1, the embodiment method
Including：
Step 101, clock signal caused by clock source is transferred at least one buffer respectively.
Wherein, each one sub- Clock Tree of buffer control, each buffer correspond to a multiplexing core in chip；It is multiple
Include at least one core calculations unit with core.
Step 102, give clock signal transmission to corresponding sub-clock tree by buffer, realize core calculations list in chip
The sequential inspection of member.
The clock signal transfer method provided based on the above embodiment of the present invention, by by clock signal caused by clock source
At least one buffer is transferred to respectively, is given clock signal transmission to corresponding sub-clock tree by buffer, is realized in chip
The sequential inspection of core calculations unit；Due to having simplified the quantity of buffer, and by buffer control sub-clock tree, realize
Sequential inspection is uniformly controlled, and makes the non-publicly-owned clock path between core calculations unit all very short, it is suppressed that on Clock Tree
Consumption.
In one specific example of clock signal transfer method the various embodiments described above of the present invention, each chip includes at least one
Individual multiplexing core, it is each to be multiplexed the corresponding sub- Clock Tree of core.
Specifically, carry out the transmission between signal by setting wire mesh grid, by chip internal be divided into it is multiple (such as：
100) multiplexing core, each to be multiplexed core one buffer of distribution, buffer sets some Clock Trees in multiplexing core, will
In original technology thousands of individual buffers simplify it is multiple (such as：100), carry out unified control.
Another embodiment of clock signal transfer method of the present invention, on the basis of the various embodiments described above, the bag of operation 101
Include：
Clock signal caused by clock source is transferred at least one buffer by Clock grid, by being transferred to buffering
Multiplexing core corresponding to clock signal driving in area, Clock grid include at least one buffer.
In the present embodiment, current signal can be deteriorated with the propagation of metal wire, current signal by buffer, distortion
Current signal will be repaired, and spread out of high-quality signal；Realized by Clock grid and all sub-clock trees are uniformly controlled, pressed down
The consumption on Clock Tree is made.
In the prior art, register all inside Clock grid meeting driving chip, quantity are relatively more.So clock network
The width and density of lattice are all bigger, could so produce bigger driving force.Thus occupy substantial amounts of metal money
Source.
In the above embodiment of the present invention, it is each be multiplexed core be only used as a node driven by Clock grid, it is necessary to by
The object of driving, tens up to a hundred being reduced to from millions of, the pressure of Clock grid mitigates significantly, and what can be done is narrow, than
It is sparse.Then substantial amounts of metals resources just can be saved, and can effectively reduces the power consumption of chip.
In one specific example of clock signal transfer method the various embodiments described above of the present invention, Clock grid uses metal wire
Form.
In one specific example of clock signal transfer method the various embodiments described above of the present invention, Clock grid is arranged on two layers
Between power grid.
Traditional Clock grid disadvantage is it in the chips, and the signal wire of surrounding can have crosstalk effect to it.One
It can be accused each other between individual Clock grid and a signal wire, when Clock grid transmits low level, and signal wire transmits high level,
There is parasitic capacitance between them.At this moment signal wire meeting attack clock grid, uprises the level on Clock grid, is influenceing chip just
Often use.The present embodiment is by the way that Clock grid is arranged between power grid, it is suppressed that Clock grid and other signal wires it
Between crosstalk effect, make Time-Series analysis more accurate.
In one specific example of clock signal transfer method the various embodiments described above of the present invention, Clock grid is arranged on chip
Middle thickness is more than or equal to the metal level of preset value.
Fig. 2 is the cross-sectional view of part real chip.As shown in Fig. 2 chip divides multiple layer metal line, it is more top
Metal level it is more thick thicker, dead resistance is smaller.Wherein, the embodiment of the present invention can using the 9th layer and the tenth layer to make when
Clock grid, the benefit so done have：
1st, nine, ten layers more thick thick, dead resistance is small.
2nd, signal wire winding can only be relatively low several layers of in chip design basic skills, and power grid can be with higher several
Layer.It is only possible to be power line around when making Clock grid, without signal wire, so crosstalk effect is not present.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above method embodiment can pass through
Programmed instruction related hardware is completed, and foregoing program can be stored in a computer read/write memory medium, the program
Upon execution, the step of execution includes above method embodiment；And foregoing storage medium includes：ROM, RAM, magnetic disc or light
Disk etc. is various can be with the medium of store program codes.
Fig. 3 is the structural representation of clock signal transfer device one embodiment of the present invention.The device of the embodiment can use
In the above-mentioned each method embodiment of the realization present invention.As shown in figure 3, the device of the embodiment includes：
Signal generation unit 31, for clock signal caused by clock source to be transferred at least one buffer respectively.
Wherein, each one sub- Clock Tree of buffer control, each buffer correspond to a multiplexing core in chip；It is multiple
Include at least one core calculations unit with core.
Sequential inspection unit 32, for giving clock signal transmission to corresponding sub-clock tree by buffer, realize chip
The sequential inspection of middle core calculations unit.
The clock signal transfer device provided based on the above embodiment of the present invention, by by clock signal caused by clock source
At least one buffer is transferred to respectively, is given clock signal transmission to corresponding sub-clock tree by buffer, is realized in chip
The sequential inspection of core calculations unit；Due to having simplified the quantity of buffer, and by buffer control sub-clock tree, realize
Sequential inspection is uniformly controlled, and makes the non-publicly-owned clock path between core calculations unit all very short, it is suppressed that on Clock Tree
Consumption.
In one specific example of clock signal transfer device the various embodiments described above of the present invention, each chip includes at least one
Individual multiplexing core, it is each to be multiplexed the corresponding sub-clock tree of core.
Another embodiment of clock signal transfer method of the present invention, on the basis of the various embodiments described above, signal produces
Unit 31, specifically for clock signal caused by clock source is transferred at least one buffer by Clock grid, pass through biography
Multiplexing core corresponding to the defeated clock signal driving in buffering area, Clock grid include at least one buffer.
In the present embodiment, current signal can be deteriorated with the propagation of metal wire, current signal by buffer, distortion
Current signal will be repaired, and spread out of high-quality signal；Realized by Clock grid and all sub-clock trees are uniformly controlled, pressed down
The consumption on Clock Tree is made.
In one specific example of clock signal transfer device the various embodiments described above of the present invention, Clock grid uses metal wire
Form.
In one specific example of clock signal transfer device the various embodiments described above of the present invention, Clock grid is arranged on two layers
Between power grid.
In one specific example of clock signal transfer device the various embodiments described above of the present invention, Clock grid is arranged on chip
Middle thickness is more than or equal to the metal level of preset value.
The other side of the embodiment of the present invention, there is provided a kind of one embodiment of Clock Tree, including：
Clock source, for producing clock signal；
Clock grid, pass through Buffer transfer to all sub-clock trees for receiving clock signal, and by clock signal；
At least one sub-clock tree, for receiving clock signal, and the core to being multiplexed corresponding to sub- Clock Tree in core
Computing unit carries out sequential inspection.
A kind of Clock Tree that the present embodiment provides, all sub-clock trees is uniformly controlled by Clock grid, when realizing
Sequence inspection is uniformly controlled, and makes the non-publicly-owned clock path between core calculations unit all very short, it is suppressed that disappearing on Clock Tree
Consumption.
In one specific example of Clock Tree above-described embodiment of the present invention, Clock grid includes at least one buffer.
The other side of the embodiment of the present invention, there is provided a kind of one embodiment of chip, including：
Including：Multiple layer metal line；Characterized in that, multiple layer metal line includes at least one layer of upper strata metal wire and at least one layer
Lower metal line；
Also include：
Power grid, it is arranged in the upper strata metal wire of chip, for transmitting current signal；
Signal wire winding, it is arranged in the lower metal line of chip, for transmitting information signal；
Clock Tree described in any of the above-described embodiment, by the Clock grid in Clock Tree be arranged on two layers power grid it
Between.
A kind of chip that the present embodiment provides, by by the Clock grid in Clock Tree be arranged on two layers power grid it
Between, it is suppressed that the crosstalk effect between Clock grid and other signal wires, make Time-Series analysis more accurate.Traditional Clock grid is most
Big shortcoming is it in the chips, and the signal wire of surrounding can have crosstalk effect to it.One Clock grid and signal wire it
Between can accuse each other, when Clock grid transmits low level, and signal wire transmits high level, have parasitic capacitance between them.At this moment
Signal wire meeting attack clock grid, uprises the level on Clock grid, influences chip normal use.
The other side of the embodiment of the present invention, there is provided one embodiment of a kind of electronic equipment, including：
Any one of clock signal transfer device the various embodiments described above of the present invention or power chip the various embodiments described above of the present invention
Any one of.
The other side of the embodiment of the present invention, there is provided one embodiment of a kind of electronic equipment, including：
Memory, for storing executable instruction；
And processor, for completing clock signal transmission of the present invention with memory communication to perform executable instruction
The operation of any one of method the various embodiments described above.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be and its
The difference of its embodiment, same or analogous part cross-reference between each embodiment.For system embodiment
For, because it is substantially corresponding with embodiment of the method, so description is fairly simple, referring to the portion of embodiment of the method in place of correlation
Defend oneself bright.
Methods and apparatus of the present invention may be achieved in many ways.For example, can by software, hardware, firmware or
Software, hardware, any combinations of firmware realize methods and apparatus of the present invention.The said sequence of the step of for methods described
Order described in detail above is not limited to merely to illustrate, the step of method of the invention, it is special unless otherwise
Do not mentionlet alone bright.In addition, in certain embodiments, the present invention can be also embodied as recording program in the recording medium, these programs
Including the machine readable instructions for realizing the method according to the invention.Thus, the present invention also covering storage is used to perform basis
The recording medium of the program of the method for the present invention.Description of the invention provides for the sake of example and description, and not
It is exhaustively or limits the invention to disclosed form.Many modifications and variations are for one of ordinary skill in the art
For be obvious.Selection and description embodiment are to more preferably illustrate the principle and practical application of the present invention, and make ability
The those of ordinary skill in domain it will be appreciated that the present invention so as to designing the various embodiments with various modifications suitable for special-purpose.
Claims (10)
- A kind of 1. clock signal transfer method, it is characterised in that including：Clock signal caused by clock source is transferred at least one buffer respectively；Each described one period of the day from 11 p.m. to 1 a.m of buffer control Zhong Shu, each buffer correspond to a multiplexing core in chip；The multiplexing core includes at least one core calculations Unit；Clock signal transmission is given to corresponding sub-clock tree by the buffer, realizes the sequential of core calculations unit in chip Check.
- 2. according to the method for claim 1, it is characterised in that each chip includes at least one multiplexing core, often The individual corresponding sub-clock tree of multiplexing core.
- 3. method according to claim 1 or 2, it is characterised in that described to pass clock signal caused by clock source respectively It is defeated by least one buffer, including：Clock signal caused by clock source is transferred at least one buffer by Clock grid, by being transferred in buffering area Clock signal driving corresponding to multiplexing core, the Clock grid includes at least one buffer.
- 4. according to the method for claim 3, it is characterised in that the Clock grid is formed using metal wire.
- 5. the method according to claim 3 or 4, it is characterised in that the Clock grid be arranged on two layers power grid it Between.
- A kind of 6. clock signal transfer device, it is characterised in that including：Signal generation unit, for clock signal caused by clock source to be transferred at least one buffer respectively；It is each described One sub- Clock Tree of buffer control, each buffer correspond to a multiplexing core in chip；The multiplexing core bag Include at least one core calculations unit；Sequential inspection unit, for giving clock signal transmission to corresponding sub-clock tree by the buffer, realize in chip The sequential inspection of core calculations unit.
- A kind of 7. Clock Tree, it is characterised in that including：Clock source, for producing clock signal；Clock grid, pass through Buffer transfer to all sub-clock trees for receiving clock signal, and by the clock signal；At least one sub-clock tree, for receiving clock signal, and the core calculations to being multiplexed corresponding to sub- Clock Tree in core Unit carries out sequential inspection.
- 8. a kind of chip, including：Multiple layer metal line；Characterized in that, the multiple layer metal line includes at least one layer of upper strata metal Line and at least one layer of lower metal line；Also include：Power grid, it is arranged in the upper strata metal wire of chip, for transmitting current signal；Signal wire winding, it is arranged in the lower metal line of chip, for transmitting information signal；Clock Tree as claimed in claim 7, the Clock grid in the Clock Tree is arranged between two layers of power grid.
- 9. a kind of electronic equipment, it is characterised in that including：Clock signal transfer device or claim 8 described in claim 6 Described chip.
- 10. a kind of electronic equipment, it is characterised in that including：Memory, for storing executable instruction；And processor, for performing the executable instruction with the memory communication so as to completing claim 1 to 5 times The operation of clock signal transfer method described in meaning one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710961866.2A CN107817870A (en) | 2017-10-16 | 2017-10-16 | Clock signal transfer method and device, Clock Tree, chip, electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710961866.2A CN107817870A (en) | 2017-10-16 | 2017-10-16 | Clock signal transfer method and device, Clock Tree, chip, electronic equipment |
Publications (1)
| Publication Number | Publication Date |
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| CN107817870A true CN107817870A (en) | 2018-03-20 |
Family
ID=61608000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710961866.2A Pending CN107817870A (en) | 2017-10-16 | 2017-10-16 | Clock signal transfer method and device, Clock Tree, chip, electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021190203A1 (en) * | 2020-03-23 | 2021-09-30 | 华为技术有限公司 | Processor clock system, child node circuit in clock system, and electronic device |
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| CN101351886A (en) * | 2005-12-29 | 2009-01-21 | 莫塞德技术股份有限公司 | ASIC design using clock and power grid standard cell |
| CN105359149A (en) * | 2013-03-21 | 2016-02-24 | 美商新思科技有限公司 | Dual-structure clock tree synthesis (cts) |
| CN105930591A (en) * | 2016-04-26 | 2016-09-07 | 东南大学 | Realization method for register clustering in clock tree synthesis |
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2017
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| US20030034815A1 (en) * | 2001-08-03 | 2003-02-20 | Feng Lin | Method to improve the efficiency of synchronous mirror delays and delay locked loops |
| CN101351886A (en) * | 2005-12-29 | 2009-01-21 | 莫塞德技术股份有限公司 | ASIC design using clock and power grid standard cell |
| CN105359149A (en) * | 2013-03-21 | 2016-02-24 | 美商新思科技有限公司 | Dual-structure clock tree synthesis (cts) |
| CN105930591A (en) * | 2016-04-26 | 2016-09-07 | 东南大学 | Realization method for register clustering in clock tree synthesis |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021190203A1 (en) * | 2020-03-23 | 2021-09-30 | 华为技术有限公司 | Processor clock system, child node circuit in clock system, and electronic device |
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