CN107817512A

CN107817512A - A kind of hardware circuit design method of digital multichannel pulse scope-analyzer

Info

Publication number: CN107817512A
Application number: CN201710206742.3A
Authority: CN
Inventors: 刘召贵; 李胜辉; 黄冲
Original assignee: Jiangsu Skyray Instrument Co Ltd
Current assignee: Jiangsu Skyray Instrument Co Ltd
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-03-20

Abstract

The invention provides a kind of hardware circuit design method of digital multichannel pulse scope-analyzer, comprise the following steps：Core pulse analog signal after front-end processing, which is sent in the A/D converter of high-speed cruising, to be changed, data signal after analog-to-digital conversion is sent to FPGA by A/D converter under FPGA control, it is sent into inside the SDRAM that FPGA is extended out and is cached after pre-processing after filtering, then it is re-fed into dsp system and core pulse peak value is obtained to digitlization core pulse signal progress pole-zero cancellation, trapezoidal shaping and peak detection process, finally the USB interface that the core pulse peak value of taking-up is carried by dsp system is sent on computer and does spectrum analyzing and processing.

Description

A kind of hardware circuit design method of digital multichannel pulse scope-analyzer

Technical field

The invention belongs to hardware circuit design field, is related to a kind of hardware circuit of digital multichannel pulse scope-analyzer and sets Meter method.

Background technology

MCA generally uses in traditional online nuclear spectrometer are sunykatuib analysis technologies.Its whole realization method is first Detector output signal is intended to amplify as charge integration, remakes Linear Amplifer, the AD conversion of slower speed is sent into after peak value broadening Device is analyzed and record.Its antijamming capability and flexibility are all poor, it is difficult to adapt to industry spot rugged environment and realize particle The functions such as signal differentiates, accumulation signal recovers.

ADC speed, logic control, igh-speed wire-rod production line are always MCA digitized " bottleneck ".Now, high-speed ADC, The new device such as DSP, FPGA, the development of new technology are closely ripe, are fully able to solve " bottleneck " problem set forth above.Pulse is believed Number amplification after, no longer by threshold value discriminator circuit and peak detection circuit stretched pulse peak value, but adopted in real time by high-speed ADC Sample, accurate digital peak is obtained after DSP and FPGA processing.Therefore, precision is high, and the good DMCA of performance can be obtained widely Using.

The content of the invention

It is contemplated that at least solves one of technical problem present in prior art.

Therefore, it is an object of the invention to propose a kind of hardware circuit design side of digital multichannel pulse scope-analyzer Method, solve the problems, such as that MCA runs on ADC speed, logic control and igh-speed wire-rod production line, so that precision is high, performance is good DMCA be widely used.

A kind of hardware circuit design method of digital multichannel pulse scope-analyzer includes：AFE(analog front end), A/D converter, Fpga chip, EMIF interfaces, dsp system, SDRAM, serial ports, FLASH, USB, USB interface and computer, step are as follows：

Core pulse analog signal after front-end processing is sent to high-speed ADC and carries out analog-to-digital conversion, controls of the ADC in the FPGA The data signal after analog-to-digital conversion is sent to the FPGA under system, the institute that the FPGA is extended out is sent into after pre-processing after filtering State and be cached inside SDRAM, be then re-fed into the dsp system and pole-zero cancellation, trapezoidal is carried out to digitlization core pulse signal Shaping and peak detection process obtain core pulse peak value, finally carry the core pulse peak value of taking-up by the dsp system The USB interface, which is sent on computer, does spectrum analyzing and processing.

AFE(analog front end) and part of data acquisition are sent into after preliminary enhanced processing from the signal of detector output.Signal passes through OPA642 described in feeding low noise is amplified to signal after crossing pole-zero cancellation circuit, is sent into the A/D chips ADS807E and is completed Analog-to-digital conversion, the ADS807E carry out A/D conversions under the control of the FPGA.

The fpga chip mainly completes the collection of data, digital filtering processing, data buffering and with the DSP's Data communicate.

The data of the fpga chip output are sent into the hicap SDRAM that the DSP is extended out in a manner of DMA and deposited In reservoir, the DSP main programs complete data algorithm.

The algorithm data completed in the DSP is sent in PC by USB interface further to be located to data Reason.

Further, the A/D chips are ADS807E.

Further, the fpga chip is EP1C3TC144.

Further, the dsp system is the core of the instrument, using TMS320VC5509A.

Further, the EMIF is external storage interface.

Brief description of the drawings：

The above-mentioned and/or additional aspect and advantage of the present invention will be apparent from the following description of the accompanying drawings of embodiments Be readily appreciated that, wherein：

Fig. 1 is overall system design figure.

Embodiment

Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not construed as limiting the claims.

First as shown in figure 1, a kind of hardware circuit design method of digital multichannel pulse scope-analyzer includes：Before simulation End, OPA642, A/D chip, fpga chip, EMIF interfaces, dsp system, SDRAM, serial ports, FLASH, USB, USB interface and meter 12 parts, its operating procedure are as follows altogether for calculation machine：

Core pulse analog signal after front-end processing is sent to high-speed ADC and changed, and ADC is under FPGA control by mould Data signal after number conversion is sent to FPGA, is sent into inside the SDRAM that FPGA is extended out and is cached after pre-processing after filtering, Then it is re-fed into dsp system and core is obtained to digitlization core pulse signal progress pole-zero cancellation, trapezoidal shaping and peak detection process Peak value of pulse, finally the USB interface that the core pulse peak value of taking-up is carried by dsp system is sent on computer and done at spectrum analysis Reason.

Signal is to be sent into OPA642 after pole-zero cancellation circuit to be amplified signal, is then fed into A/D chips Analog-to-digital conversion is completed in ADS807E, ADS807E carries out A/D conversions under the control of fpga chip.

The fpga chip that we use is EP1C3TC144, and this chip is to apply SOPC technologies, collection dense logic, is deposited Reservoir and embeded processor realize the perfect adaptation of speed and program capability on single programmable logic device.FPGA The collection, digital filtering processing, data buffering of data are mainly completed in systems.The collection of data is completed using fpga chip With part number processing primarily to data are buffered and shared with DSP part work, when DSP is had enough Between complete the processing of real-time data-signal.

Dsp system is the core of the instrument, using TMS320VC5509A.TMS320VC5509A connects with EMIF Mouthful, the seamless connection between multiple memorizers can be achieved.Because the data volume sent from FPGA is bigger, between FPGA and DSP Data communication rates require it is higher, typically the number between FPGA can be realized using the multiple tracks buffered serial port that DSP is carried According to transmission, and the transmission rate of serial ports does not reach the transmission speed of our requirements, thus using EMIF interfaces come realize FPGA with The high-speed transfer of data between DSP.

EMIF is external storage interface, can be by memory expanding to 128Mbit by EMIF（SDRAM）.Loading When EMIF be that default configuration completes asynchronous SRAM interface in space, and wheel worst condition is taken in sequential Set, fully ensured that argin so that program code is successfully loaded into DSP internal memory.

Some algorithm is completed in dsp.In order to reserve time enough to DSP, to complete algorithm, we use what is interrupted Mode completes the data transfer between FPGA to DSP.Data acquisition in FPGA has been arrived after enough data and has sent one to DSP Individual interrupt signal, then DSP enter external interrupt program, interrupt routine starts DMA transfer.The data that FPGA is sent are with DMA Mode is sent in the mass storage that DSP is extended out, and it is that will use these numbers that corresponding algorithm is completed in DSP main programs According to.Interrupt service routine only need to be performed the arrangement of the data storage location of corresponding DMA startups and DMA transfer, then To return to DSP main programs, save and take turns the substantial amounts of clock cycle, reserve wheel time enough to DSP to complete algorithm.

In the description of the invention, it is to be understood that term " on ", " under ", " bottom ", " top ", "front", "rear", The orientation or position relationship of the instruction such as " interior ", " outer ", " horizontal stroke ", " perpendicular " are based on orientation shown in the drawings or position relationship, are only Described for the ease of description is of the invention with simplified, rather than the device or element of instruction or hint meaning must be with specifically sides Position, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.

In the description of the invention, it is necessary to which explanation, unless otherwise clearly defined and limited, term " connection ", " connects It is logical ", " connected ", " connection ", " cooperation " should be interpreted broadly, for example, it may be fixedly connected, be integrally connected or It is detachably connected；It can be the connection of two element internals；Can be joined directly together, the indirect phase of intermediary can also be passed through Even；" cooperation " can be the cooperation in face and face or the cooperation in point and face or line and face, and the also cooperation including hole axle is right For one of ordinary skill in the art, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.

Claims

A kind of 1. hardware circuit design method of digital multichannel pulse scope-analyzer, it is characterised in that including：AFE(analog front end), A/D converter, fpga chip, EMIF interfaces, dsp system, SDRAM, serial ports, FLASH, USB, USB interface and computer, step It is as follows：

Core pulse analog signal after front-end processing is sent to the high speed A/D converter and changed, the A/D conversions Data signal after analog-to-digital conversion is sent to the FPGA by device under the control of the FPGA, is sent into after pre-processing after filtering It is cached inside the SDRAM that the FPGA is extended out, is then re-fed into the dsp system and digitlization core pulse signal is entered Row pole-zero cancellation, trapezoidal shaping and peak detection process obtain core pulse peak value, and the core pulse peak value of taking-up finally is passed through into institute State the USB interface that dsp system carries be sent on computer do spectrum analyzing and processing.
2. a kind of hardware circuit design method of digital multichannel pulse scope-analyzer according to claim 1, its feature It is, the AFE(analog front end) and part of data acquisition is sent into after preliminary enhanced processing from the signal of detector output.
3. signal is sent into OPA642 described in low noise after pole-zero cancellation circuit and signal is amplified, the A/D chips are sent into Analog-to-digital conversion is completed in the ADS807E, the ADS807E carries out A/D conversions under FPGA control.
4. a kind of hardware circuit design method of digital multichannel pulse scope-analyzer according to claim 1, its feature Be, the fpga chip is the EP1C3TC144, the main collection for completing data, digital filtering processing, data buffering, with And communicated with the data of the DSP.
5. a kind of hardware circuit design method of digital multichannel pulse scope-analyzer according to claim 1, its feature It is, the data of the fpga chip output are sent into SDRAM described in the hicap that the DSP is extended out in a manner of DMA In memory, the DSP main programs complete data algorithm.
6. a kind of hardware circuit design method of digital multichannel pulse scope-analyzer according to claim 1, its feature It is, the algorithm data completed in the DSP is sent in PC by USB interface and data are further processed.