CN107807882A - Timing alorithm block method of testing and device based on MPU operations - Google Patents
Timing alorithm block method of testing and device based on MPU operations Download PDFInfo
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Abstract
The invention belongs to the technical field of nuclear power industry main control device performance test, in order to solve in the testing scheme of the timing alorithm block for MPU operations in the prior art, special value can not being inputted in specific period, can not obtaining the technical problem of specific period output valve, the present invention provides a kind of timing alorithm block method of testing and device based on MPU operations；Methods described includes：S1, when the count value of counter is equal to and specifies periodic quantity, input the input parameter value specified to the timing alorithm block based on MPU operations；S2, when the count value of counter is equal to and specifies periodic quantity, the actual operation result of the output timing alorithm block based on MPU operations.
Description
Technical field
The present invention relates to the technical field of nuclear power industry main control device performance test, more particularly to main control device algorithmic block are black
The technical field of box test, more particularly, to a kind of timing alorithm block method of testing and device based on MPU operations.
Background technology
Safety problem is most important in nuclear power field, is embodied in timing alorithm block software test, particularly clearly, to sequential
For algorithmic block test, method of testing generally comprises two kinds of white-box testing, Black-box Testing, in white-box testing, it is necessary to sequential
Each individual path of algorithm block code is covered, it is necessary to reach MC/DC (modification condition/judgement covering) covering 100%.
, it is necessary to confirm to the value in each cycle of timing alorithm block in Black-box Testing, to ensure the correctness of algorithm operation.
For example, Chinese Patent Application No. number is in CN201611217349.6 patent application, a kind of algorithms library is disclosed
Simulation and verification platform implementation method, including：The first step, according to the requirement of nuclear power station security level control system, all calculations
The basic FPGA of method block is realized, all algorithmic blocks in algorithms library are arranged into unified interface；Second step, produce each algorithm
The simulation excitation vector of block；3rd step, if necessary to add algorithmic block, it is only necessary to increase algorithmic block content on the verification platform
With corresponding artificial vector, configuration file is then changed；4th step：The simulation result of emulation tool output is generated with emulator
As a result it is compared.
For the test of the timing alorithm block run based on MPU, according to design similar in the prior art, it will usually expect
Design cycle is designed to include：Configuration algorithm, lower dress MPU, reset operation, to input variable particular value, check output result.
But inventor has found during the present invention is realized：Because MPU clock frequencies are higher, cycle time most I
Up to 10ms, 100 cycles can be run within 1 second, manual operation can not be accurate to ms ranks, timing alorithm block running
In, output result is closely related with the clock cycle, may there is within 1 second 100 different output results.Therefore exist in testing
Following two difficult points：
A), particular value can not be inputted in specific period, such as inputs the first particular value, the 2nd cycle to algorithmic block in the 1st cycle
The second particular value is inputted to algorithmic block.
B) it is difficult, to obtain the output result of specific period, such as obtains the output valve in the 100th cycle.
And inventor is further discovered that：For more than a) article in the difficult point that refers to, prior art does not have related
Solution method, for b) article in the difficult point that refers to, it is a kind of it is conceivable that way be that output result is connected by hardwire
Onto oscillograph, output result is amplified, by recognition cycle number, checks corresponding output result；But even if use oscillography
Device, can also there are many deficiencies：For example, obtaining the output result of timing alorithm block using oscillograph, it is slow speed to be present, efficiency
It is low, it is necessary to consume substantial amounts of human cost when testing multiple timing alorithm blocks；And oscillograph cycle and numerical value are manually read,
Numerical error may be brought, influences test result.
The content of the invention
In order to solve in the testing scheme of the timing alorithm block for MPU operations in the prior art, it is impossible in specific period
Input special value, the technical problem that specific period output valve can not be obtained, transported it is an object of the invention to provide one kind based on MPU
It capable timing alorithm block method of testing and device, can simply, quickly set algorithmic block to specify the input value in cycle, and can obtain
Algorithmic block is taken to specify the output valve in cycle.
To achieve these goals, technical scheme provided by the invention includes：
On the one hand, there is provided a kind of timing alorithm block method of testing based on MPU operations, it is characterised in that including：
S1, when counter count value be equal to specify periodic quantity when, input the input parameter value specified and be based on MPU to described
The timing alorithm block of operation；
S2, when the count value of counter is equal to and specifies periodic quantity, the output timing alorithm block based on MPU operations
Actual operation result.
The embodiment of the present invention preferably, in the step S1, is equal to by the count value of the comparator counter
Specify periodic quantity；When the two is equal, the selector that is connected with the timing alorithm block is defeated by the input parameter value specified
Enter to the timing alorithm block；When the two is unequal, real-time parameter value is inputted to the timing alorithm block.
Preferably, in the step S2, the timing alorithm block output end is provided with sequential and followed the embodiment of the present invention
Module, and specified periodic quantity is equal to by the count value of the comparator counter；When the two is equal, by described
Sequential follows module to export the actual operation result of the timing alorithm block；When the two is unequal, the sequential is followed
Timing values output in module.
Preferably, when the cycle is 1, the sequential follows the output default value 0 of module to the embodiment of the present invention, big when the cycle
When 1, the sequential follows module to export upper periodical input value, and is added with numerical value 1, the output as the counter.
Preferably, it is an algorithm in algorithm configuration software REDACE that the sequential follows module to the embodiment of the present invention
Block, for realizing the latch function of variate-value.
On the other hand the embodiment of the present invention provides a kind of timing alorithm block test device based on MPU operations, its feature exists
In, including：
The counter being connected with the timing alorithm block, when the count value of counter, which is equal to, specifies periodic quantity, input refers to
Fixed input parameter value to it is described based on MPU operation timing alorithm block；And
When the count value of counter, which is equal to, specifies periodic quantity, the reality of the output timing alorithm block based on MPU operations
Border operation result.
Preferably, described device also includes the comparator being connected with the counter to the embodiment of the present invention, passes through the ratio
Count value compared with the device counter is equal to specified periodic quantity；When the two is equal, it is connected with the timing alorithm block
Selector, the input parameter value specified is inputted to the timing alorithm block；When the two is unequal, by real-time parameter value
Input to the timing alorithm block.
The embodiment of the present invention preferably, described device also include with the timing alorithm block output end be provided with sequential with
It is equal to specified periodic quantity with module, and by the count value of the comparator counter；When the two is equal, pass through institute
Stating sequential follows module to export the actual operation result of the timing alorithm block；When the two is unequal, by the sequential with
Exported with the timing values in module.
Preferably, when the cycle is 1, the sequential follows the output default value 0 of module to the embodiment of the present invention, big when the cycle
When 1, the sequential follows module to export upper periodical input value, and is added with numerical value 1, the output as the counter.
Preferably, it is an algorithm in algorithm configuration software REDACE that the sequential follows module to the embodiment of the present invention
Block, for realizing the latch function of variate-value.
Using above-mentioned technical proposal provided by the invention, at least one of following beneficial effect can be obtained：
1st, can be in specified periodical input special value by the comparison with counter, solving in the prior art can not be real
The problem of current sequence algorithm block specifies periodical input particular value.
2nd, by the comparison with counter, output result can also be obtained in the specified cycle, there is provided obtain and specify the cycle
The settling mode of output valve, read numerical value simpler, numerical precision is high, improves testing efficiency.
3rd, the operation to timing values is realized counter and by way of latching combination so that output result is more stable can
Lean on.
The further feature and advantage of invention will illustrate in the following description, also, partly become aobvious from specification
And be clear to, or understood by implementing technical scheme.The purpose of the present invention and other advantages can be by illustrating
Specifically noted structure and/or flow are realized and obtained in book, claims and accompanying drawing.
Brief description of the drawings
Fig. 1 provides a kind of timing alorithm block testing process block diagram based on MPU operations for the embodiment of the present invention.
Fig. 2 provides a kind of flow chart of the timing alorithm block method of testing based on MPU operations for the embodiment of the present invention.
Fig. 3 for the embodiment of the present invention provide it is a kind of based on MPU operation timing alorithm block method of testing in input it is specific
The flow chart of periodical input particular value.
Fig. 4 is that input specific period corresponding with Fig. 3 inputs the schematic diagram that specific value-based algorithm is realized.
Fig. 5 provides output end in a kind of timing alorithm block method of testing based on MPU operations for the embodiment of the present invention and obtained
The flow chart of specific period output result.
Fig. 6 is that output end corresponding with Fig. 5 obtains the schematic diagram that specific period output result algorithm is realized.
Fig. 7 provides sequential in a kind of timing alorithm block method of testing based on MPU operations for the embodiment of the present invention and follows mould
The flow chart of block algorithm output.
Fig. 8 provides a kind of timing alorithm block method of testing Counter module based on MPU operations for the embodiment of the present invention
The flow of algorithm output.
Fig. 9 is the schematic diagram that counter algorithm corresponding with Fig. 8 is realized.
Figure 10 provides a kind of Black-box Testing system block diagram of the timing alorithm block based on MPU operations for the embodiment of the present invention.
Embodiment
Embodiments of the present invention are described in detail below with reference to drawings and Examples, and how the present invention is applied whereby
Technological means solves technical problem, and the implementation process for reaching technique effect can fully understand and implement according to this.Need to illustrate
, these specific descriptions are to allow those of ordinary skill in the art to be more prone to, clearly understand the present invention, rather than to this hair
Bright limited explanation；And if conflict is not formed, each embodiment in the present invention and each spy in each embodiment
Sign can be combined with each other, and the technical scheme formed is within protection scope of the present invention.
In addition, can be in the control system of a such as group controller executable instruction the flow of accompanying drawing illustrates the step of
Middle execution, although also, show logical order in flow charts, in some cases, can be with different from herein
Order performs shown or described step.
Below by the drawings and specific embodiments, technical scheme is described in detail：
Embodiment
As shown in figure 1, the present embodiment, which provides, is based on MPU (English full name Main Processing Unit, main process task list
Member) operation timing alorithm block Black-box Testing (with the angle of user, from the corresponding relation of input data and output data
The method tested) it is typically being attached under the good algorithm of configuration in MPU, by being specifically worth to input variable, during acquisition
The output of sequence algorithm block, output result and the uniformity of expected results are checked, to judge the correct of timing alorithm block operation result
Property.
As shown in Fig. 2 the present embodiment provides a kind of timing alorithm block method of testing based on MPU operations, this method includes：
S1, when the count value of counter is equal to and specifies periodic quantity, input the input parameter value specified and run to based on MPU
Timing alorithm block；I.e. when needing to check that some specifies the computing situation in cycle, counter is set equal to specify the cycle
Cycle value, then input signal is reached after this specifies cycle, by corresponding input parameter, input value is based on MPU operations
Timing alorithm block, wait timing alorithm block according to predetermined configuration logical relation carry out logical operation；
S2, when counter count value be equal to specify periodic quantity when, export based on MPU operation timing alorithm block reality
Operation result；I.e. when needing to check that some specifies the operation result in cycle, counter is set equal to specify to the week in cycle
Issue value, after input signal then is reached into the specified cycle, obtain output valve corresponding to the cycle, it is possible to obtain specifying week
The operation result of phase.
Preferably, in step S1, the count value that counter is compared by comparator is equal to specified periodic quantity to the present embodiment；When
When the two is equal, the selector that is connected with timing alorithm block inputs specified input parameter value to timing alorithm block；When the two
When unequal, real-time parameter value is inputted to timing alorithm block.
Therefore, by above-mentioned method of testing, can obtain exactly in the timing alorithm block test process based on MPU operations
Specify periodical input parameter and the output parameter in specified cycle, thus can be by specified periodical input parameter and specified cycle it is defeated
Go out parameter, contrasted with predetermined parameter, so as to for specifying whether the test result in cycle meets to require, carry out accurate
Judge.
Preferably, in step S2, timing alorithm block output end is provided with sequential and follows module (abbreviation FBY the present embodiment
Module), and the count value of counter is compared equal to specified periodic quantity by comparator；When the two is equal, by sequential with
The actual operation result of timing alorithm block is exported with module；When the two is unequal, sequential is followed to the timing values in module
Output.
Preferably, when the cycle is 1, sequential follows the output default value 0 of module to the present embodiment, when being more than 1 in the cycle, when
Sequence follows module to export upper periodical input value, and is added with numerical value 1, inputs to counter.
Preferably, it is an algorithmic block in algorithm configuration software REDACE that sequential follows module to the present embodiment, for reality
The latch function of existing variate-value.
On the other hand the present embodiment provides a kind of timing alorithm block test device based on MPU operations, the device includes：
The counter being connected with timing alorithm block, when the count value of counter, which is equal to, specifies periodic quantity, input what is specified
Timing alorithm block of the input parameter value extremely based on MPU operations；I.e. when needing to check that some specifies the computing situation in cycle, it will count
Number device is set equal to specify the cycle value in cycle, after input signal then is reached into the specified cycle, by corresponding input
Parameter, the timing alorithm block that input value is run based on MPU, timing alorithm block is waited to be patrolled according to the logical relation of predetermined configuration
Collect computing；And
When the count value of counter, which is equal to, specifies periodic quantity, the actual fortune of the timing alorithm block based on MPU operations is exported
Calculate result；I.e. when needing to check that some specifies the operation result in cycle, counter is set equal to specify to the cycle in cycle
Numerical value, after input signal then is reached into the specified cycle, obtain output valve corresponding to the cycle, it is possible to obtain specifying the cycle
Operation result.
Preferably, device also includes the comparator being connected with counter to the present embodiment, compares counter by comparator
Count value, which is equal to, specifies periodic quantity；When the two is equal, the selector that is connected with timing alorithm block, by specified input parameter value
Input to timing alorithm block；When the two is unequal, real-time parameter value is inputted to timing alorithm block.
Preferably, device also follows module to the present embodiment including being provided with sequential with timing alorithm block output end, and
The count value for comparing counter by comparator is equal to specified periodic quantity；When the two is equal, by sequential follow module by when
The actual operation result output of sequence algorithm block；When the two is unequal, sequential is followed the timing values in module export.
Preferably, when the cycle is 1, sequential follows the output default value 0 of module to the present embodiment, when being more than 1 in the cycle, when
Sequence follows module to export upper periodical input value, and is added with numerical value 1, the output as above-mentioned counter.
Preferably, it is an algorithmic block in algorithm configuration software REDACE that sequential follows module to the present embodiment, for reality
The latch function of existing variate-value.
Detailed explanation is carried out to above-mentioned method of testing and test device, it is necessary under being of explanation with reference to Fig. 3-Fig. 9
State what way of example was realized based on algorithm configuration, it is same for the similar test object of same timing alorithm block, the technical program
It is applicable, the present embodiment location in whole application process is interpreted in Fig. 1, in order to which those skilled in the art are more clear
Chu's the present embodiment, obtain specific period output result, counting from input specific period input particular value, output end separately below
Device module, further spreads out explanation.
As shown in figure 3, input specific period input particular value technical scheme, mainly solve specific period to when
The specific input value of sequence algorithm block, makes input content controllable, and the program circuit of this part includes：
S101, beginning, start testing process.
S103, rolling counters forward；Wherein, the counting cycle of counter is equal to the clock week of timing alorithm block in MPU operations
Phase, the mode of rolling counters forward is the numerical value cumulative 1 of counter after each clock cycle.
S105, judge whether the count value of counter is equal to the periodic quantity of settingWherein, the periodic quantity of setting, that is, need
Which the clock cycle specified input value or operation result of timing alorithm block are checked, just specifies the cycle to be referred to as what is set this
Periodic quantity, or claim specific period；Such as 10, mean that the 10th clock cycle；When the two is equal, S107 is performed；When two
When person is unequal, S109 is performed.
S107, input particular value, i.e., input particular value into timing alorithm block.
S109, the real-time input value of input, real-time input value that will be predetermined are inputted into timing alorithm block.
More specifically, as shown in Figure 4：Hereinafter Value_input represents instantaneous value _ input, and Cycle_input represents week
Time value _ input, Value_output represent instantaneous value _ output, and Default_as represents default value, and Cycle represents periodicity；Meter
Number device provides cycle count, and parametric variable " Cycle " is the input interface of specific period.
It is specific input value for different types of numerical quantities " Cycle_input ", variable " Value_input " is real-time
Input value, " Value_output " are output result.
Counter (Counter modules) with periodic duty export n, n=1,2,3 ... ..., when counter output valve and cycle
When setting variable " Cycle " value is equal, comparison module ("=") output is "true", then passes through following selecting module output variable
" Cycle_input ", i.e. Value_output=Cycle_input.When counter output valve and cycle set variable " Cycle "
When being worth unequal, comparison module ("=") output is "false", then passes through following selecting module output variable " Value_
Input ", i.e. Value_output=Value_input.
, can be by adjusting Cycle_input, Value_ if desired for input real type numerical value for different types of numerical value
Input, Value_output value type are that real realizes that other types are by that analogy.
As shown in figure 5, output end obtains the technical scheme of specific period output result, it is defeated mainly to solve timing alorithm block
Go out end and obtain specific period output result, result is latched after obtaining particular result, the program flow diagram of this part includes：
S201, beginning, start testing process.
S203, rolling counters forward；Wherein, the counting cycle of counter is equal to the clock week of timing alorithm block in MPU operations
Phase, the mode of rolling counters forward is the numerical value cumulative 1 of counter after each clock cycle.
S205, judge whether the count value of counter is equal to the periodic quantity of settingWherein, the periodic quantity of setting, that is, need
Which the clock cycle specified input value or operation result of timing alorithm block are checked, just specifies the cycle to be referred to as what is set this
Periodic quantity, or claim specific period；Such as 10, mean that the 10th clock cycle；When the two is equal, S207 is performed；When two
When person is unequal, S209 is performed.
S207, output timing algorithmic block actual value, i.e., using the real output value of timing alorithm block as last computing knot
Fruit exports.
S209, output timing follow module sequential, i.e., follow module timing values to export as a result sequential.
More specifically, as shown in fig. 6, counter provides cycle count, parametric variable " Cycle " is the input of specific period
Interface, variable " Value_input " are timing alorithm block output valve, and variable " Default_as " is that sequential follows module sequential to write from memory
Recognize value, " Value_output " is output result.
Counter (Counter modules) with periodic duty export n, n=1,2,3 ... ..., when counter output valve and cycle
When setting variable " Cycle " value is equal, comparison module ("=") output is "true", then passes through following selecting module output variable
" Value_input ", i.e. Value_output=Value_input.When counter output valve and cycle set variable " Cycle "
When being worth unequal, comparison module ("=") output is "false", then follows module sequential by following selecting module output timing
Value.
For different types of numerical value, if desired for obtaining real type numerical results, can by adjust Value_input,
Default_as, Value_output value type are that real realizes that other types are by that analogy.
It is a rudimentary algorithm block in algorithm configuration software REDACE that the sequential that the present embodiment provides, which follows module, and it is calculated
Method logic is as shown in Figure 7, it is assumed that input parameter X is followed successively by 1,2,3,4 from the 1st cycle to the 4th cycle, then passes through FBY modules
Output afterwards was followed successively by for the 0,1,2,3, the 5th cycle as 4 from the 1st cycle to the 4th cycle；Assuming that input parameter X is from the 1st cycle to
4 cycles were followed successively by 5,4,2,1, then are followed successively by 0,5,4,2 from the 1st cycle to the 4th cycle by the output after FBY modules；Its
1st cycle 0 of middle output is default value, exports and is clapped than inputting slow 1.Sequential follows module mainly to realize the latch work(of variate-value
Energy；Idiographic flow includes：
S301, beginning, start testing process.
S303, input parameter (X) initialization.
S305, judge whether the periodicity of current system operation is more than 1If it is, performing step S307, otherwise, perform
Step S309.
S307, output Xn-1, Xn-1 are a upper periodic quantity for input parameter (X).
S309, output default value, i.e. sequential follow the default value 0 of module.
Because system operation is than very fast, the output result change of timing alorithm block is also fast, chooses the defeated of timing alorithm block
Go out after result it is necessary to the result of current period is saved, that is, latch.
The function (function that mainly performance period counts) of counter is explained in detail with reference to Fig. 8, such as
Shown in Fig. 8, the handling process being related to of counter includes：
S401, beginning, start testing process.
S403, judge whether the periodicity of system operation is more than 1If it is, performing step S405, otherwise, step is performed
S409。
S405, sequential follow module output to be equal to Countn-1；Tied the count value of counter cumulative calculation as output
Fruit sequential follows the output of module；Then S407 is performed.
S407, by Countn-1Count, the current count value as counter are assigned after+1.Specifically, such assignment
It is to realize from 1 tally function is added, is such as initially 0, adds 1 on the basis of original every time, be formed 1,2,3 ...；And
And FBY modules and addition realize tally function, it is exactly counter module to be combined；
S409, sequential follow module to export default value 0 (default value), then perform S411.
S411, Count will be assigned after 0+1, the current count value as counter.
More specifically, as shown in figure 9, the algorithm implementation of counter includes：When the cycle is 1, sequential follows module
Export default value 0, when being more than 1 in the cycle, sequential follows module to export upper periodical input value countn-1, and with the phase of numerical value 1
Add, be output to count.
As shown in Figure 10, there is ON to be delayed with the timing alorithm block in FirmSys system development projects, being related to below,
OFF delays, position type PID, first-order lag scheduling algorithm block, apply and illustrate in the Black-box Testing to the algorithm above block
It is bright.
In the Black-box Testing of timing alorithm block, algorithm implementation in Fig. 4, Fig. 6, Fig. 9 is generally encapsulated as a calculation
Method block uses, below by taking LAG (first-order lag algorithmic block) as an example, Black-box Testing of the below figure to timing alorithm block LAG,
During 3 cycle, the 1st pin inputs particular value 5000.0, and the 2nd pin inputs particular value 1.0, and the 3rd pin inputs particular value
25, in addition to the 3rd cycle, 3 of tested algorithmic block input the checking aspect for corresponding to output result respectively, obtain 1,2,3 respectively
The output result in cycle, is respectively present LAG_Y_1, LAG_Y_2, LAG_Y_3.
Using above-mentioned technical proposal provided by the invention, at least one of following beneficial effect can be obtained：
1st, can be in specified periodical input special value by the comparison with counter, solving in the prior art can not be real
The problem of current sequence algorithm block specifies periodical input particular value.
2nd, by the comparison with counter, output result can also be obtained in the specified cycle, there is provided obtain and specify the cycle
The settling mode of output valve, read numerical value simpler, numerical precision is high, improves testing efficiency.
3rd, the operation to timing values is realized counter and by way of latching combination so that output result is more stable can
Lean on.
Finally it should be noted that described above is only highly preferred embodiment of the present invention, not the present invention is appointed
What formal limitation.Any those skilled in the art, it is without departing from the scope of the present invention, all available
The way and technology contents of the disclosure above make many possible variations and simple replacement etc. to technical solution of the present invention, these
Belong to the scope of technical solution of the present invention protection.
Claims (10)
- A kind of 1. timing alorithm block method of testing based on MPU operations, it is characterised in that including：S1, when the count value of counter is equal to and specifies periodic quantity, input the input parameter value specified and run to described based on MPU Timing alorithm block；S2, when the count value of counter is equal to and specifies periodic quantity, the reality of the output timing alorithm block based on MPU operations Operation result.
- 2. according to the method for claim 1, it is characterised in that in the step S1, pass through the comparator counting The count value of device, which is equal to, specifies periodic quantity；When the two is equal, the selector that is connected with the timing alorithm block, described will specify Input parameter value input to the timing alorithm block；When the two is unequal, real-time parameter value is inputted to the sequential and calculated Method block.
- 3. according to the method for claim 1, it is characterised in that in the step S2, the timing alorithm block output end It is provided with sequential and follows module, and specified periodic quantity is equal to by the count value of the comparator counter；When the two When equal, module is followed to export the actual operation result of the timing alorithm block by the sequential；When the two is unequal, The sequential is followed the timing values in module export.
- 4. according to the method for claim 3, it is characterised in that when the cycle is 1, the sequential follows the output of module to write from memory Recognize value 0, when being more than 1 in the cycle, the sequential follows module to export upper periodical input value, and is added with numerical value 1, as described The output of counter.
- 5. the method according to claim 3 or 4, it is characterised in that it is algorithm configuration software that the sequential, which follows module, An algorithmic block in REDACE, for realizing the latch function of variate-value.
- A kind of 6. timing alorithm block test device based on MPU operations, it is characterised in that including：The counter being connected with the timing alorithm block, when the count value of counter, which is equal to, specifies periodic quantity, input what is specified Input parameter value to it is described based on MPU operation timing alorithm block；AndWhen the count value of counter, which is equal to, specifies periodic quantity, the actual fortune of the output timing alorithm block based on MPU operations Calculate result.
- 7. device according to claim 6, it is characterised in that described device also includes the comparison being connected with the counter Device, it is equal to by the count value of the comparator counter and specifies periodic quantity；When the two is equal, with the sequential The selector of algorithmic block connection, the input parameter value specified is inputted to the timing alorithm block；When the two is unequal, Real-time parameter value is inputted to the timing alorithm block.
- 8. device according to claim 6, it is characterised in that described device also includes and the timing alorithm block output end Side is provided with sequential and follows module, and is equal to specified periodic quantity by the count value of the comparator counter；When two When person is equal, module is followed to export the actual operation result of the timing alorithm block by the sequential；When the two is unequal When, the sequential is followed the timing values in module export.
- 9. device according to claim 6, it is characterised in that when the cycle is 1, the sequential follows the output of module to write from memory Recognize value 0, when being more than 1 in the cycle, the sequential follows module to export upper periodical input value, and is added with numerical value 1, as described The output of counter.
- 10. device according to claim 8 or claim 9, it is characterised in that it is algorithm configuration software that the sequential, which follows module, An algorithmic block in REDACE, for realizing the latch function of variate-value.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711015299.8A CN107807882B (en) | 2017-10-26 | 2017-10-26 | Sequential algorithm block testing method and device based on MPU operation |
Applications Claiming Priority (1)
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| CN201711015299.8A CN107807882B (en) | 2017-10-26 | 2017-10-26 | Sequential algorithm block testing method and device based on MPU operation |
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| Publication Number | Publication Date |
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| CN103995742A (en) * | 2014-05-20 | 2014-08-20 | 万向钱潮股份有限公司 | Embedded type real-time scheduling control device and method based on MCU |
| US20150057766A1 (en) * | 2013-08-22 | 2015-02-26 | Fujitsu Limited | Communication device, control system, and communication method |
| CN105912467A (en) * | 2016-04-08 | 2016-08-31 | 腾讯科技（深圳）有限公司 | Performance test method and device |
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| US20150057766A1 (en) * | 2013-08-22 | 2015-02-26 | Fujitsu Limited | Communication device, control system, and communication method |
| CN103995742A (en) * | 2014-05-20 | 2014-08-20 | 万向钱潮股份有限公司 | Embedded type real-time scheduling control device and method based on MCU |
| CN105912467A (en) * | 2016-04-08 | 2016-08-31 | 腾讯科技（深圳）有限公司 | Performance test method and device |
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