CN107770565A - The apparatus and method of low latency Video coding - Google Patents
The apparatus and method of low latency Video coding Download PDFInfo
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- CN107770565A CN107770565A CN201710680674.4A CN201710680674A CN107770565A CN 107770565 A CN107770565 A CN 107770565A CN 201710680674 A CN201710680674 A CN 201710680674A CN 107770565 A CN107770565 A CN 107770565A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
- H04N21/23608—Remultiplexing multiplex streams, e.g. involving modifying time stamps or remapping the packet identifiers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/43—Hardware specially adapted for motion estimation or compensation
- H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
- H04N21/4341—Demultiplexing of audio and video streams
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
- H04N21/4342—Demultiplexing isochronously with video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
Abstract
A kind of apparatus and method of the Video coding with low latency.It is compressed video data that the device carrys out coding input video data comprising a video encoding module, one or more processing modules handle the video data of the compression from the video encoding module to provide the inputting video data to the video encoding module or further, and a data storage related to each processing module, to store or provide the data shared between the video encoding module and each processing module.The coding module is arranged to manage the data access of a data storage by coordinating the video encoding module with a processing module with each processing module, after being ready in another the target shared data in video encoding module and processing module in the data storage, the target shared data is received from the data storage.Video coding system provided by the invention, reduce the delay in the video link of recording/transmission end, broadcasting/receiving terminal or both ends.
Description
Prioity claim
The application advocate the U.S. Provisional Patent Application filed an application on the 15th of August in 2016 the 62/374,966th with
The right of the U.S. Patent Application No. filed an application on July 6th, 2017 15/642,586, and above-mentioned U.S. Patent application is to draw
It is incorporated herein with mode.
Technical field
The present invention is related to Video coding.Specifically, the present invention is on by managing between multiple processing modules
Data access and the very low latency of processing time (low-latency) Video coding.
Background technology
Video data needs larger memory space to store or need wider bandwidth to transmit.With high-resolution
With the development of higher frame per second, if video data is stored and transmitted in the form of uncompressed, it is stored will with demand of transmission
It is reluctant.Therefore, video data typically uses video coding technique in compressed form to store and transmit.Pass through
Using newer video compression format, for example, H.264/AVC, VP8, VP9 and enhancing HEVC (High Efficiency Video
Coding) standard, code efficiency are significantly improved.In order to keep accessible complexity, image is conventionally divided into multiple areas
Block, such as macro zone block (MB, macroblock) or LCU/CU apply Video coding.Video encoding standard is typically based on block
To be applied to interframe/infra-frame prediction (Inter/Intra prediction).
In video coding system, involved coding usually requires largely to calculate with decoding process.Those are calculated may
Cause some delays in encoder-side and decoder end.Apply, such as broadcast live in real time for some, would not want to grow
Delay.For interactive application, such as remote processing (tele-presence), long delay is offensive and will caused poor
Consumer's Experience.Therefore, it is necessary to design a kind of video coding system with very low latency.
Fig. 1 is for example, containing the Video coding in source from a video link of a source a to receiving terminal
With the video decoding in receiving terminal.Video link source can be corresponded to a video record or Transmission system, to produce compression
Video data, to record or transmit.Video receiver can correspond to video player or reception system to produce regarding for decoding
Frequency plays according to this.For recording application either via the transmission application of Wi-Fi, internet or other transmission environments, compression
Video can be stored in multi storage.In Fig. 1, the corresponding recording of system 110 or Transmission system, and system 120
Corresponding broadcasting or reception system.In recording or Transmission system 110, the video source is compiled using video encoder 112
Code, to produce the video of compression.Generally, the system is also comprising related voice data.Video/audio (Audio/Video, A/
V) signal is combined using A/V multiplexers (A/V MUX) 114.The audio ＆ video data of the multiplexing can be recorded or transmitted.
In Fig. 1, it is shown that the audio ＆ video data of multiplexing are transmitted using Wi-Fi MAC 116.In broadcasting or reception system
In 120, video bit stream is decoded using Video Decoder 122, comes in display driving 124 to show to produce the video of decoding
Show.A/V demultiplexing (A/V DEMUX) 126 can be used to demultiplex for related voice data.In Fig. 1, it is shown that use Wi-
Fi MAC 128 receive the example of the audio ＆ video data of multiplexing.
The video data is typically to be produced and played with a predetermined frame per second.For example, the video can have frame per second
120fps (frame is per second, frames per second).In this case, each frame period it is corresponding 8.33 milliseconds (ms,
millisecond).For processing in real time, each frame is needed to be encoded in 8.33ms interior decoding.Fig. 2A is to record
Video record path in system is regarded with producing for example, wherein the video source is encoded using video encoder 210
Frequency bit stream.The video bit stream is then together multiplexed by MUX212 with voice data, to produce compression volume A/V data,
To store or transmit.Video encoder 210 and MUX212 will need the time to carry out processing data.Enter from the block of video data
Start to stop at the time of leaving MUX212 to corresponding compressed data at the time of video encoder 210, during which there is processing delay.Should
Delay be referred to as record or transmission delay.Fig. 2 B are in the display system video playback paths for example, wherein should
The A/V data of compression are demultiplexed by demultiplexer (DEMUX) 220, and to extract video bit stream, it is supplied to video solution
Code device 222 produces reconstruction frames, there is provided to display 224.Demultiplexer 220, Video Decoder and display 224 will need the time
Processing data.Exist at the time of the A/V data related to the block of video data enter DEMUX 220 to corresponding reconstruction data
At the time of display in display 224, processing delay be present.The delay is referred to as playing or receives delay.In a video link,
End to end delay (namely (recording delay+playout-delay) or (transmission delay+reception delay)) has in some Video Applications
There is consequence, such as application in real time.The design object of the present invention is that end to the end minimized in a video link is prolonged
Late.For example, the delay can be measured in units of the frame period.Therefore, it is an object of the present invention to minimize the delay, yes
The delay is less than the N frame periods.In another example, the delay is measured in units of millisecond.Therefore, target of the invention
It is to minimize the delay, the delay for being is less than x milliseconds.
Fig. 3 is the citing of adaptability interframe/intraframe video coding system with reference to loop processed (loop processing)
Explanation.Source images buffer 311 stores inputting video data.For inter prediction, estimation (ME)/motion compensation (MC)
312 be for providing prediction data based on the video data from other images or other multiple images.The selection of switch 314
Infra-frame prediction 310 or inter prediction data, and the prediction data selected is to provide to adder 316, is missed to form prediction
Difference, also referred to as remaining (residues).The prediction error is then transformed and (Transform, is abbreviated as T) 318 and follow-up amount
Change (Quantization, being abbreviated as Q) 320 to handle.The conversion is available to rate-distortion optimization (Rate with the remnants of quantization
Distortion Optimization, RDO)/mode decision unit (Mode Decision unit) 321 comes with rate and distortion
The related coding mode of angle estimation cost.The encoder then selects a pattern, and obtains with rate-distortion cost
The optimum performance of (rate-distortion cost) measurement.The conversion is then coded by entropy device 322 with the remnants quantified and encoded,
With included in a video bit stream of the video data to that should compress.Should with conversion coefficient related bits stream then by with side
Side information, such as motion, coding mode and other information related to image-region, together package.The avris information is also led to
Entropy code is crossed to compress, to reduce required bandwidth.When using an inter-frame forecast mode, a reference picture or multiple references
Image is also required to rebuild in decoder end.So as to which the remnants of, the conversion and quantization are by re-quantization (Inverse
Quantization, be abbreviated as IQ) 324 with inverse transformation (Inverse Transformation, be abbreviated as IT) 326 come handle with
Recover remaining.Using adder 328, the remnants are then added back to prediction data, to rebuild video data.The reconstruction video counts
According to being storable in reference picture buffers 334 and for the prediction of other frames.However, reconstruction from REC (reconstruction) 428
Video data can due to it is a series of processing and cause a variety of damages.Therefore, generally stored in reconstruction video data to reference
Before frame buffer 334, using loop filter 330 (such as deblocking (De-blocking)) to video data is rebuild, to carry
High video quality.For example, de-blocking filter (deblocking filter, DF) adaptively offsets (Sample with sample
Adaptive Offset, SAO) it is to make in high efficiency Video coding (High Efficiency Video Coding, HEVC)
With.The loop filter information is contained within the bit stream, so as to which a decoder can correctly recover required information.Cause
This, loop filter information is available to entropy coder 322 to be incorporated into the bit stream.In figure 3, (the example of loop filter 330
Such as de-blocking filter) it is to be applied before reconstruction sample is stored to reference picture buffers 334 to reconstruction video.In figure 3
System is the signal of the example arrangement of an exemplary video encoder.It can correspond to HEVC systems or H.264.
Fig. 4 is the systematic square frame schematic diagram of Video Decoder corresponding to encoder system in Fig. 3.This it is total solution code system be
It is divided into two parts：Syntax parsing 410 and back end decoders (post decoder) 420.Because the encoder also includes one
Local decoder rebuilds the video data, and some decoder components (except entropy decoder 412) use in the encoder.More
Further, only motion compensation 422 is needed for decoder end.The selection infra-frame prediction of switch 424 or inter prediction, and
The prediction data of the selection is to provide to reconstruction unit (REC) 428, is combined with the remnants of recovery.Except for the residual of compression
Remaining execution entropy decoding, entropy decoding 412 also are responsible for entropy decoding avris information and provide the avris information (such as frame mode information
With inter-frame mode information) to an other block.For example, motion vector is to decode and be stored in MV buffers 414.It is the plurality of
MV is then provided to motion compensation 422 to position reference block.The remnants are by IQ324, IT326 and follow-up reconstruction journey
Sequence is handled, to rebuild the video data.Again, the video data experience such as Fig. 4 of the reconstruction from reconstruction unit REC428
A series of shown processing (including IQ324 and IT326), and it is projected to coding artifact.The video data of the reconstruction is further
Handled by loop filter 330.
In video coding system, a frame is conventionally divided into multiple sections (slice) to provide the ability of parallel processing.And
And the piece cutting structure can limit data dependence in each section.It is wide in various video coding standard to be somebody's turn to do " section " noun
General use, for example, in MPEG2/4, H.264, HEVC, RM, AVS/AVS2 etc..Further, the basic coding unit is in video
Used in standard.For example, macro zone block (Macroblock, MB) is used in AVC, MPEG4 etc..Superzone block (Super
Block, SB) it is to be used in VP9 standards.Code tree unit (Coding Tree Unit, CTU) is used in HEVC.More
Further, using a coding structure, CTU rows, SB rows and MB rows.In order to promote video compression ratio, georeferencing data and time
Reference data is for predicting.Fig. 5 is the schematic diagram of space and time prediction, and wherein frame 510 is handled before frame 520.Often
One frame is to be divided into multiple tiles (tile), and each tile is to be divided into multiple PU.For frame 510, PU_A (pu_x=0,
Pu_y=y it) can be used as PU_B (pu_x=0, pu_y=y+1) georeferencing data (namely upper adjacent).Also, PU_A can use
Make PU_C (pu_x=0, pu_y=y) time reference data (position identical data).
For entropy code, it has diversified forms.Variable length code (Variable length coding) is that entropy is compiled
A kind of form of code, and it is widely used in source code.Generally, variable-length codes (VLC) table is to be used for variable length code
With decoding.Arithmetic coding (such as based on context adaptability binary arithmetic coding (context-based adaptive
Binary arithmetic coding, CABAC)) it is a newer entropy coding, it can use " context " and utilize bar
Part possibility.Further, arithmetic coding can be simply adapted to source statistics, and compared to variable length code provide compared with
High compression efficiency.Arithmetic coding is an efficient entropy coding instrument, and is widely used in advanced video coding system, arithmetic
The operation of coding is more complicated than variable length code.The two types of entropy coding method are relatively time consuming.Accordingly, entropy code/
Decoding usually becomes the bottleneck of system.
As it is known in the art, higher bit rate will cause preferable video quality.At higher bit rate, back end decoders
Reason is relatively bit rate dependence.However, in higher bit rate, the non-zero quantised residual of entropy code will be needed with greater number of
It is remaining.Therefore, for higher bit rate, entropy code and the calculated load increase of decoding.Therefore, the calculated load of entropy decoding be for
Bit rate is sensitive, and entropy decoding turns into the efficiency bottleneck of video decoding, particularly in high bit rate.Accordingly, upper bit
Rate bit stream causes larger delay.Therefore, it is necessary to be designed using with the entropy decoding that the Maximum Bit Rate according to its ability limits.
When the bit stream of video bit stream is higher than a limitation, it is necessary to develop other solutions, and not use single entropy solution
Code design.
Fig. 6 is HEVC wavefront parallel processing (wavefront parallel processing, WPP) schematic diagram.It is each
Frame is divided into multiple sections, the corresponding CTU rows of each of which section.WPP reduce grammatical tagging between multiple CTU rows according to
Rely.CTU rows can the parallel processing by using WPP methods.In HEVC standard, when bit stream is according to WPP codings, grammer
" entropy_coding_sync_enabled_flag " is set as 1.According to WPP, it is processed in multiple blocks of a previous CTU
Afterwards, current CTU the first block can be processed.In the example shown in Fig. 6, in the 3rd CTU of a previous CTU rows area
After block (A0) is processed, the first CTU of current CTU rows the first block (such as B0) is processed.For in CTU rows 1
Current block 610, the block can use the adjacent block in the identical CTU rows for carrying out the comfortable post processing for handling the current block
Information.Also, the current block in CTU rows 1 can use the letter from the adjacent block 620 in previous CTU rows
Breath.
In order to reduce in recording/transmission end, the broadcasting/receiving terminal or the delay at both ends, there is provided a kind of system, it is assisted
Adjust the data access and processing time in different disposal module and/or each processing module.
The content of the invention
The device of Video coding with low latency is provided.The device carrys out coding input video comprising a video encoding module
Data for compression video data, one or more processing modules come provide the inputting video data to the video encoding module or
The further video data of compression of the processing from the video encoding module, and a data related to each processing module are deposited
Reservoir, to store or provide the data shared between the video encoding module and each processing module., should according to the present invention
Coding module is arranged to manage a data by coordinating the video encoding module with a processing module with each processing module
The data access of memory, to exist in another the target shared data in the video encoding module and a processing module
After being ready in the data storage, the target shared data is received from the data storage.
One or more processing modules include a front end processing block, and the data related to the front end processing block
The corresponding first memory of memory.In this case, the front end processing block provides the one first of a corresponding video section
First pixel data of coded data collection, to store to the first memory, and when the first coding data of the video section
One or more blocks of collection are when being ready in the first memory, and the video encoding module is received and encoded to should video area
Second pixel data of one or more blocks of the first coding data collection of block.The first coding data of the video block
Collection is to be encoded to one first bit stream by the video encoding module.In this case, the size limitation of first bit stream
For equal to or less than a full-size, and wherein the full-size is to encode the first coding data of the video section
Determined before collection.Further, the full-size is based on the decoder capabilities related to a target video decoder and a mesh
Mark the related recording ability of video recording device or the network related to being capable of an objective network of compressed video data processing
Ability determines.
In one embodiment, the corresponding image signal processing blocks of the front end processing block, the first memory corresponding one
Source buffer, and the corresponding block column of the first coding data collection of the video section, and wherein the picture signal is handled
Module provides first pixel data based on by-line, and the video encoding module the block column first pixel data all
Store to the first memory, start to encode one or multiple blocks of the first coding data collection of the video section.
The image signal processing blocks may be based on block district by district and provide first pixel data, and the video encoding module is in multiple areas
First pixel data of block is stored to the first memory, starts to encode the first coding data collection of the video section
A block.
The corresponding ring buffer of the first memory, the ring buffer have a fixed dimension, and the fixed dimension is less than one
Video section.Each frame of video includes one or more video sections.The first coding data collection of the video section includes multiple
Coding unit.The corresponding code tree cell row of the first coding data collection of the video section, a coding unit row, one independently cut
Piece or an attached section.
One or more processing modules are further comprising a back end processing module and related to the back end processing module
The corresponding second memory of the data storage.In this case, the video encoding module provides a corresponding video section
First bit stream of the package of the data of the compression of the first coding data collection, to be stored in the second memory, and should
Back end processing module handles the bit stream of package first after the bit stream of package first is ready in the second memory
To record or transmit.The corresponding Multiplexing module of the back end processing module, and the wherein Multiplexing module is by the first of the package
Bit stream is together multiplexed with the data of multiplexing with other data comprising voice data, to record or transmit.The Multiplexing module
Obtain a video channel index or to should video area section timestamp, with the data of the multiplexing.This second is deposited
The corresponding ring buffer of reservoir.The size of the second memory can gamble the source chi for two coding unit rows for winning a video section
It is very little.
In one embodiment, the end position for one first data cell for being written to a data storage is corresponded to
One write-in pointer or instruction, is transmitted to the video encoding module from the front end processing block signal, or from the Video coding mould
Block signal is transmitted to the back end processing module.Further, the corresponding number of one second in a data storage read
A reading pointer or instruction according to the end position of unit, are transmitted to the front-end processing mould from the video encoding module signal
Block, or transmitted from the back end processing module signal to the video encoding module.
In one embodiment, a handshake module be coupled to the video encoding module with this per one by one or multiple processing
Module.In one example, only the handshake module is directly accessed the data storage, in this case, by being coupled to
The video encoding module and the handshake module of the front end processing block, the front end processing block are write to the first memory simultaneously
And the video encoding module is read from the data storage, or the video encoding module is by being coupled to the Video coding mould
The handshake module of block and the back end processing module writes to the second memory and the back end processing module is by being coupled to
The video encoding module and the handshake module of the back end processing module are read from the second memory.In another example
In, the handshake module and the indirect access data storage, in this case, the front end processing block write direct this
One memory and the video encoding module are directly read from the first memory, or the video encoding module is write direct
Directly read to the second memory and the back end processing module from the second memory.In another example, only
The handshake module and the video encoding module are directly accessed the data storage with one or more processing module one of both,
In this case, one or more processing modules are related to the data storage, and the front end processing block writes direct
Should by be coupled to the video encoding module and the front end processing block to the first memory and the video encoding module
Handshake module is read from the first memory；Or the video encoding module is write direct to the second memory and this
End processing module is by being coupled to the handshake module of the video encoding module and the back end processing module from the second memory
Middle reading.In addition, wherein the front end processing block is held by coupling with this of the video encoding module and the front end processing block
Fingerprint block is write to the first memory, and the video encoding module is directly read from the first memory, or this is regarded
Frequency coding module is write to this by being coupled to the handshake module of the video encoding module and the back end processing module and second deposited
Reservoir, and the back end processing module is directly read from the second memory.
In another embodiment, the first handshake module is coupled to the video encoding module and one second handshake module
It is coupled to one or more processing modules.Further, only first handshake module is directly deposited with second handshake module
Take the first memory or the second memory.In this case, the front end processing block passes through second handshake module
Write-in is to the first memory, and the video encoding module is read by first handshake module from the first memory,
Or the video encoding module is write to the second memory by first handshake module, and the back end processing module passes through
Second handshake module is read from the second memory.
The present invention separately provides a kind of method for video coding, comprising：Video source is handled to driving into video counts using front-end module
According to, and store the inputting video data in the first memory；The of the inputting video data is received from the first memory
One input data, and using video encoding module encode the inputting video data to compress video data, wherein this first
The data access of memory is arranged to after first input data is write to the first memory by the front-end module,
So that the video encoding module reads first input data；The compression is provided from the video encoding module to second memory
Video data；And the video data of the first compression of the video data of the compression is received from the second memory, and use
Multiplexer handles the video data of the compression to record or transmit with other data-reusings comprising video data, wherein should
The data access of second memory is placed so that the multiplexer passes through the Video coding in the video data of first compression
Module is write to the second memory, reads the video data of first compression.
Video coding system provided by the invention, its data coordinated between multiple different disposal modules of the system are deposited
Take and processing time, reduce the delay in the video link of recording/transmission end, broadcasting/receiving terminal or both ends.
Brief description of the drawings
Fig. 1 be included in source Video coding and the decoding of receiving terminal video source to receiving terminal video link
Illustrate.
Fig. 2A is video record path for example, wherein the video source is to use Video coding in recording system
Device encodes, to produce video bit stream.
Fig. 2 B are video playback path for example, wherein the compression video/audio data is in play system
Demultiplexed by demultiplexer, to extract the video bit stream, it is supplied to Video Decoder to produce reconstruction frames to show.
Fig. 3 is the schematic diagram of the exemplary interframe of the adaptability comprising a loop processed/intraframe video coding system.
Fig. 4 is the system block diagram of the Video Decoder corresponding to encoder system shown in figure 3.
Fig. 5 is the schematic diagram of space and time prediction.
Fig. 6 is the schematic diagram of the illustration of HEVC wavefront parallel processings.
Fig. 7 A are the coded treatments for example, wherein the video is defeated of the video encoder according to embodiments of the invention
Enter is that the mode of by-line writes to holder and the CTU sizes and is assumed to be 32X32.
Fig. 7 B are the decoding process for example, wherein the video is defeated of the Video Decoder according to embodiments of the invention
Enter is to write to holder and the CTU sizes by CTU mode and be assumed to be 32X32.
Fig. 8 is using the output of the video encoder based on section of ring buffer and showing for the illustration of multiplexer input
It is intended to.
Fig. 9 is the schematic diagram that ring buffer is mapped to for 8 slice of datas for inputting section ring buffers.
Figure 10 is the exemplary coding system based on encoder shown in figure 3, and wherein the system is based on CTU comprising one
Source buffer and a schematic diagram based on section ring buffer.
Figure 11 is the schematic diagram for applying the present invention to a video coding system with wavefront parallel processing feature.
Figure 12 is included in ISP and the data sharing access of video encoder the first holder and included in video
The schematic diagram of the video coding system for the second holder that the data sharing of encoder and multiplexer accesses.
Figure 13 A are the schematic diagram of the handshake mechanism according to embodiments of the invention, the wherein primary module and the handshake module
Handshaking information with notice, and the primary module from/to the data storage access data.
Figure 13 B are the schematic diagram of the handshake mechanism according to embodiments of the invention, the wherein primary module and the handshake module
Handshaking information with notice, and only the handshake module from/to the data storage access data.
Figure 14 is the another of handshake mechanism for example, wherein common handshake resume module is for primary module A and primary module B
Handshake mechanism, and only the handshake module accesses the data storage.
Figure 15 is the another for example, a wherein common handshake module quilt of the handshake mechanism according to embodiments of the invention
Use, and only the common handshake module is directly accessed the data storage.
Figure 16 is the another for example, a wherein common handshake module quilt of the handshake mechanism according to embodiments of the invention
Use, and only the common handshake module is directly accessed the data storage with primary module B.
Figure 17 is the another for example, a wherein common handshake module quilt of the handshake mechanism according to embodiments of the invention
Use, and only the common handshake module is directly accessed the data storage with primary module A.
Figure 18 is the another for example, the mould of shaking hands of two of which respectively of the handshake mechanism according to embodiments of the invention
Block handles the handshake mechanism for primary module A and primary module B respectively.
Figure 19 is the flow chart of the exemplary coding system for realizing low latency according to embodiments of the invention.
Embodiment
Follow-up explanation is to realize highly preferred embodiment of the present invention.The explanation is used merely to illustrate the general of the present invention
Spirit, and be not a limitation.The scope of the present invention is determined with reference to attached claims.
In order to reduce the delay in the video link of recording/transmission end, broadcasting/receiving terminal or both ends, the present invention provides
A kind of system, it coordinates the data access and processing time between multiple different disposal modules of the system.
Fig. 7 A are the coded treatments for example, wherein the video is defeated of the video encoder according to embodiments of the invention
It is the write buffer in a manner of by-line to enter, and the CTU sizes are assumed to be 32x32.In fig. 7, source buffer state
It is picture signal processing (image signal during this period during (source buffer state) 710 corresponding one
Processing, ISP) module writes view data to image in the one 32 line (first 32lines) with scanning sequency by-line
During buffer 710.After the one 32 line of the buffer fills up, when ISP persistently writes data to 2 32 line, depending on
Frequency encoder can start first CTU of the coding in the first CTU rows, as shown in source buffer state 720.The of the buffer
After 2 32 lines fill up, when ISP persistently writes data to 3 32 line, video encoder can start coding in the 2nd CTU
The first CTU in row, as shown in source buffer state 730.Fig. 7 A are the acts that tightly (tightly) couples source buffer control
Example explanation, wherein when one or multiple CTU are ready to, the encoder starts the coded treatment in a CTU, and it is in the present invention
Also referred to as encoder source race (encoder source racing).It is noted that source buffer need not retain whole figure
Picture.When a CTU rows are handled by encoder, the space of the CTU rows is releasable and re-uses.
Fig. 7 B are the coded treatments for example, wherein the video is defeated of the video encoder according to embodiments of the invention
It is the write buffer in a manner of by CTU to enter, and the CTU sizes are 32x32.In figure 7b, the ISP is in first a small amount of CTU
Period writes video data to source buffer, as shown in source buffer state 740.When one or more CTU in the buffer of source it is accurate
Get ready, the encoder can first CTU of the start to process in CTU rows, as shown in source buffer state 750.One is write in ISP
Simultaneously, both ISP and video encoder continuous processing data, the CTU encoded have multiple CTU to CTU before.Source buffers
Device state 760 shows that the ISP is written in the 2nd CTU rows when video encoder coding changes the CTU in the first CTU rows again
In a CTU.
After video data encoding, the bit stream is together multiplexed with voice data.The present invention further discloses management
Data access and the technology of processing time between the coder module and the Multiplexing module.Fig. 8 is for based on section
Video frequency output uses a ring buffer (ring buffer) 810 with multiplexer input.Encoder write-in is every for a section
One bit flow to the individual buffer input (independent buffer entry) of the ring buffer.Multiple sections it is multiple
Bit stream be continuously write the ring buffer multiple bufferings input (such as by one or more encoder core write ratio
Spy's stream).When the bit stream of a section is completed, the write-in pointer renewal of the multiplexer (alternatively referred to as Multiplexing module).For example, work as
When section #N data 812 are multiplexed into handled by device 820, the write-in pointer points to the input 1 of the section ring buffer.Cutting
Piece #N data 812 are multiplexed into after the processing of device 820, and the write-in pointer is updated to next input (inputting 2).The multiplexer
820 immediately read out one or more slice of data from the section ring buffer 810, and send to coffret.Now,
One or more slice of datas are considered as completing and the multiplexer updates and notifies the reading pointer (read pointer) extremely
The encoder.Output 830 from multiplexer 820 also illustrates in fig. 8.The input can correspond to sequence output (serial
Output) 832 or parallel output (parallel output) 834.
Fig. 9 is to be directed to the slice of data image of a 8- outputting cutting loop buffers to the illustration of the ring buffer.From
The slice of data 910 caused by the encoder is shown in left-hand side.Ring buffer input 920 for the image of slice of data exists
Right-hand side is shown.As shown in this example, CTU rows #7 slice of data is write-in ring buffer input #7.CTU rows #7's is next
Slice of data (namely #8) is the ring buffer input #0 of write-in (as shown in arrow 922).In this example, every CTU rows
It is considered as a section.
Figure 10 is the schematic diagram based on the encoder system shown in Fig. 3, and wherein current system contains a source based on CTU
Ring buffer 1030 of the buffer 1010 and one based on section.Further, a context buffer (context buffer)
1020 be the data from a previous CTU rows that the context based on context entropy code is formed for storing.
Figure 11 be apply the present invention to wavefront parallel processing (wave-front parallel processing,
WPP) the schematic diagram of a video coding system of frame.Frame 1110 is divided into multiple coding units or arbitrary encoded block,
Each of which block of cells is to the data cell applied to coded treatment.As known in field of video encoding, the data cell can
A corresponding macro zone block (MB), a superzone block (SB), a code tree unit (CTU) or a volume as defined in HEVC coding standards
Code unit (CU).The corresponding coding unit row of the first coding unit collection.Different volumes can be come from according to what WPP feature parallels encoded
The plurality of coding unit of code cell row is by point (1111,1112 or 1113) Suo Shi.
Carry out shared data using source buffer between the ISP module and the video encoder to access, as already identified above.And
And between the video encoder and the multiplexer module using based on section ring buffer come shared data block, as above
It is described.For the Video coding path, the ISP is considered as the front-end module (front-end module) of the video encoder, and
And the multiplexer is considered as the rear module (post-end module) of the video encoder.Figure 12 is to include a first memory
1210 and one second memory 1240 video coding system schematic diagram, the first memory 1210 be the ISP1220 with
The data sharing access of the video encoder 1230, and the second memory 1240 is with being somebody's turn to do in the video encoder 1230
The data sharing access of multiplexer 1250.For example, as described above, the first memory 1210 can to should source buffer, and
And the second memory 1240 can be to that should be based on ring buffer of cutting into slices.However, shared memory access is realized to realize that this is low
The other kinds of reservoir designs of delayed video coding can be used as.
It can realize that the operation of the video coding system of the foundation embodiments of the invention of low latency will be as described below.For
The image signal processing blocks 1220, it writes the data of the first coding unit collection to the first memory 1210, and leads to
Handshake mechanism (handshaking mechanism) is crossed to link up with the video encoder 1230.When the first coding unit collection
DSR is read out, and notifies the video encoder 1230.For video encoder 1230, it is single that it encodes first coding
Metaset is first bit stream, and writes first bit and flow to the second memory 1240.First bit stream can package
To network abstraction layer unit, and the first bit stream of the package writes a second memory.The video encoder 1230 also with
Multiplexing module 1250 is linked up by handshake mechanism, and when first bit stream is ready to be read out, the Multiplexing module
1250 are notified.For the Multiplexing module 1250, it reads the first bit stream of the package from the second memory 1240, and
And transmit first bit and flow to an interface, such as Wi-Fi module, to carry out network transmission.The video link can correspond to one and regard
Frequency is recorded and audio/video player system.In this example, the Multiplexing module 1250 reads the envelope from the second memory 1240
First bit stream of bag, and stored to a memory cell.
In fig. 11, a frame of video is divided into multiple coding unit rows or multiple block columns.One is less than regarding for a frame
Frequency section (video segment), such as a tile, it is also possible to make an input block of the coded system.Therefore, a frame of video
Multiple video sections can be included.Each coding unit collection (alternatively referred to as coded data collection) can correspond to an individual slices or one
Individual attached section.In fig. 12, the video encoder 1220 can be completed first coding is single in the front-end module (such as ISP)
The all pixels data of metaset are write after the first memory, start to encode the pixel data of the first coding unit collection.To the greatest extent
Pipe ISP is the illustration as the front-end module, it is possible to use other kinds of FEP.
The size of first bit stream can be limited to a full-size and the full-size can encode a video area
Determined before section.The full-size can be according to the Video Decoder, related to a target video record device recording ability or
The ability of person's network determines.
The corresponding source buffer of the first memory.According to one embodiment of the invention, the ring with a fixed dimension delays
Device is rushed to be used.The fixed dimension is less than a video section.When the first memory of front-end module write-in video data,
The video data can be in a manner of by-line or block mode writes district by district.In situation about being write based on line (line-based) data
Under, when all video lines of block column video encoder is ready in all video lines of a block column, can start
Encode multiple blocks.In the case where being write based on block (block-based) data, when one or more blocks of the block column
When being ready to, coding first block in a block column can be started.The block can correspond to a CTU, a CU, a SB or MB.
The video data buffer of the corresponding compression of the second memory.According to the embodiment, the ring buffer with a fixed dimension
It can be used as the second memory.The rear module can drive to should video area section the video index.Also, the rear module
The timestamp (time stamp) of a corresponding video section can be obtained.
In fig. 12, two processing modules (namely ISP and video encoder) are coupled to the first memory.Also, two
Individual processing module (namely video encoder and multiplexer) is coupled to the second memory.Two modules provided below are (simple
For, referred to as modules A and module B) between handshake mechanism support the low latency.It is corresponding for the first memory, modules A
The ISP and module B are to should video encoder.For the second memory, modules A is to should video encoder and module
B is to should multiplexer.In one example, handshake mechanism is as described below：
Modules A writes one first data a to data storage；
● the write-in pointer of modules A transmission one to module B, wherein write-in pointer instruction in a data storage one the
The end position of one data；
● module B receives the write-in pointer from the modules A；
● module B reads one first data from a data storage；And
● module B transmits the reading pointer to modules A, wherein reading pointer instruction in a data storage one the
The end position of one data.
In another example, handshake mechanism is as described below：
● modules A writes one first data a to data storage；
● the write-in pointer of modules A transmission one to module B, wherein write-in pointer instruction in a data storage one the
One data；
● module B receives a write-in instruction from the modules A；
● module B reads one first data from a data storage；And
● module B transmission one reads instruction to modules A, wherein reading and indicates that indicating module B have read the first data.
Another handshake mechanism according to the present invention, the wherein primary module and handshake module has been illustrated in Figure 13 A and Figure 13 B
Communication, exchanged with entering row information with notice.In figure 13a, the primary module 1310 from/to data storage 1320 access the number
According to, and the primary module 1310 communicates with the handshake module 1330, to exchange information and notice.In this example, Jin Jinzhu
The direct accessing data memory 1320 of modules A 1310.In Figure 13 B, the handshake module 1330 from/to the data storage 1320
The data are accessed, and the primary module 1310 communicates with the handshake module 1330, to exchange information and notice.In this example
In, only handshake module 1330 is directly accessed from data storage 1320.
Figure 14 is the another for example, wherein one public handshake module of the handshake mechanism according to embodiments of the invention
Handshake mechanism of 1430 processing for primary module A1410 and primary module B1420.When the data storage 1440 is corresponding in fig. 12
During the shown first memory, primary module A1410 to should front-end module and primary module B1420 to should Video coding
Device.When the corresponding second memory in fig. 12 of the data storage 1440, primary module A1410 is to should Video coding
Device, and primary module B1420 is to should multiplexer.In this example, only the handshake module 1430 is directly accessed the data
Memory 1440.
Figure 15 is another illustration of the handshake mechanism according to embodiments of the invention.In this example, one is public
Handshake mechanism of the processing of handshake module 1530 for primary module A1510 and primary module B1520.When the correspondence of data storage 1540
In fig. 12 during the shown first memory, primary module A1510 to should front-end module and primary module B1520 to that should regard
Frequency encoder.When the corresponding second memory in fig. 12 of the data storage 1540, primary module A1510 is to should video
Encoder, and primary module B1520 is to should multiplexer.In this example, primary module A1510 and primary module B1520 are direct
Access the data storage 1540.
Figure 16 is another illustration of the handshake mechanism according to embodiments of the invention.In this example, one is public
Handshake mechanism of the processing of handshake module 1630 for primary module A1610 and primary module B1620.When the correspondence of data storage 1640
In fig. 12 during the shown first memory, primary module A1610 to should front-end module and primary module B1620 to that should regard
Frequency encoder.When the corresponding second memory in fig. 12 of the data storage 1640, primary module A1610 is to should video
Encoder, and primary module B1620 is to should multiplexer.In this example, both primary module B1620 and handshake module 1630
It is directly accessed the data storage 1640.
Figure 17 is another illustration of the handshake mechanism according to embodiments of the invention.In this example, one is public
Handshake mechanism of the processing of handshake module 1730 for primary module A1710 and primary module B1720.When the correspondence of data storage 1740
In fig. 12 during the shown first memory, primary module A1710 to should front-end module and primary module B1720 to that should regard
Frequency encoder.When the corresponding second memory in fig. 12 of the data storage 1740, primary module A1710 is to should video
Encoder, and primary module B1720 is to should multiplexer.In this example, both primary module A1710 and handshake module 1730
It is directly accessed the data storage 1740.
Figure 18 is another illustration of the handshake mechanism according to embodiments of the invention.In this example, two points
Other handshake module (1830 and 1840) handles the handshake mechanism with primary module B1820 for primary module A1810 respectively.Shake hands mould
Block A1830 be coupled to primary module A handle from/to modules A exchange information with notice.On the other hand, handshake module B1840 is coupled
In primary module B1820 come handle from/to module B1820 exchange information with notice.When the data storage 1850 is corresponding in Figure 12
Shown in the first memory when, primary module A1810 to should front-end module and primary module B1820 to should Video coding
Device.When the corresponding second memory in fig. 12 of the data storage 1850, primary module A1810 is to should Video coding
Device, and primary module B1820 is to should multiplexer.In this example, both handshake module A1830 and handshake module B1840
It is directly accessed the data storage 1850.
Figure 19 is foundation embodiments of the invention to realize the flow chart of the exemplary coding system of low latency.According to the reality
Example is applied, in step 1910, it using front-end module processing is inputting video data that video source, which is, and stores the input video number
According in a first memory.Figure 12 is to produce the signal of inputting video data using a front-end module (namely ISP 1220)
Figure.In step 1920, the first input data of inputting video data receives from the first memory, and the input video number
According to being to be encoded to compressed video data using a video encoding module, the data access of the wherein first memory is arranged to
After first inputting video data is write to the first memory by the front-end module, the video encoding module is caused to be read
Take first input data.Figure 12 is the illustration of video encoder 1230 and first memory 1210.A variety of handshake mechanisms
Illustrated in Figure 13 into Figure 18.In step 1930, the video data of the compression from the video encoding module is supplied to one second
Memory.In step 1940, the first compressed video data of the compressed data receives from the second memory, and the compression
Video data be together to be multiplexed using a multiplexer with other data (including voice data) to record or transmit, wherein
The data access of the second memory, be arranged to this first compression video data by the video encoding module write to
After the second memory, the multiplexer is caused to read the video data of first compression.The data access may be configured as using
Handshake module as shown in Figure 13 to Figure 18.
Described above causes those skilled in the art such as content of the concrete application of offer and its demand to realize this hair
It is bright.A variety of modifications of above-described embodiment can all obtain for those skilled in the art, and generic principles defined here can
Using to other embodiment.Therefore, the present invention is not limited to shown specific embodiment, and should be and the principle and novelty
The consistent widest scope of feature.In above-mentioned illustrate, whole detail be for provide for the present invention deep reason
Solution.However, one skilled in the art can be appreciated that the present invention can be achieved.
Described embodiment is used merely to for example, and being not the limitation of the present invention.The scope of the present invention, by asking
Ask indicated by the scope of protection, and be not limited only to above-described embodiment.Modification with claimed scope equivalents is all wrapped
It is contained within the scope of it.
Claims (24)
1. a kind of video coding apparatus, comprising：
Video encoding module, it is compressed video data to carry out coding input video data；
One or more processing modules, come from and be somebody's turn to do to provide the inputting video data to video encoding module or further processing
The video data of the compression of video encoding module；And
The data storage related to each one or more processing modules, storage or offer are in the video encoding module with being somebody's turn to do
The data shared between one or more each processing modules；And
Wherein the video encoding module and one or more each processing modules be for by coordinate the video encoding module with
One or more each processing modules, to manage the data access of the data storage, with from the video encoding module with
After the target shared data of one or more each processing modules is ready in the data storage, from the data storage
Receive the target shared data.
2. video coding apparatus according to claim 1, it is characterised in that before wherein one or more processing modules include
Processing module, and the data storage corresponding first memory related to the front end processing block are held, and wherein before this
Processing module is held to provide the first pixel data of the first coding data collection of corresponding video section, to store to first storage
Device, and when one or more blocks of the first coding data collection of the video section are ready in the first memory, this is regarded
Frequency coding module receive and encode to should video area section the first coding data collection one or more blocks second
Pixel data.
3. video coding apparatus according to claim 2, it is characterised in that wherein first coded number of the video section
It is that the first bit stream is encoded to by the video encoding module according to collection.
4. video coding apparatus according to claim 3, it is characterised in that the size of wherein first bit stream is limited to
Equal to or less than full-size, and wherein the full-size be encode the video section the first coding data collection it
Preceding decision.
5. video coding apparatus according to claim 4, it is characterised in that wherein the full-size is to be based on regarding with target
The related decoder capabilities of frequency decoder, the recording ability related to target video record device regard with that can handle compression
The objective network of frequency evidence related network capabilities determines.
6. video coding apparatus according to claim 2, it is characterised in that wherein the front end processing block correspondence image is believed
Number processing module, the first memory corresponding source buffer, and the first coding data collection of the video section corresponds to block
OK, and wherein the image signal processing blocks provide first pixel data based on by-line, and the video encoding module exists
First pixel data of the block column is all stored to the first memory, starts to encode first volume of the video section
One or multiple blocks of code data set.
7. video coding apparatus according to claim 2, it is characterised in that the wherein corresponding image of the front end processing block
Signal processing module, the corresponding source buffer of the first memory, and the first coding data collection of the video section is corresponding
Block column, and wherein the image signal processing blocks provide first pixel data, and the Video coding based on block district by district
Module after first pixel data of multiple blocks is stored to the first memory, start to encode the video section this
One block of one coded data collection.
8. video coding apparatus according to claim 2, it is characterised in that the wherein corresponding ring buffering of the first memory
Device, the ring buffer have a fixed dimension, and the fixed dimension is less than a video section.
9. video coding apparatus according to claim 2, it is characterised in that each of which frame of video regards comprising one or more
Frequency section.
10. video coding apparatus according to claim 2, it is characterised in that wherein first coding of the video section
Data set includes multiple coding units.
11. video coding apparatus according to claim 2, it is characterised in that first coding of a wherein video section
Data set corresponding a code tree cell row, a coding unit row, an individual slices or an attached section.
12. video coding apparatus according to claim 2, it is characterised in that one or more processing modules are further wrapped
Containing a back end processing module and the corresponding second memory of the data storage related to the back end processing module, and its
In the video encoding module provide to should video area section the first coding data collection compression data package first
Bit stream, to be stored in the second memory, and the back end processing module the package the first bit stream this second
After being ready in memory, the first bit stream of the package is handled to record or transmit.
13. video coding apparatus according to claim 12, it is characterised in that the corresponding multiplexing mould of the back end processing module
Block, and wherein the first bit stream of the package and other data comprising voice data are together multiplexed with by the Multiplexing module
Data, to record or transmit.
14. video coding apparatus according to claim 13, it is characterised in that the Multiplexing module obtains a video channel rope
Draw or to should video area section timestamp, with the data of the multiplexing.
15. video coding apparatus according to claim 13, it is characterised in that the corresponding ring buffering of the second memory
Device.
16. video coding apparatus according to claim 13, it is characterised in that corresponding to be written to data storage
The write-in pointer of the end position of first data cell or instruction, transmitted from the front end processing block signal to the Video coding mould
Block, or transmitted from the video encoding module signal to the back end processing module.
17. video coding apparatus according to claim 16, it is characterised in that it is corresponding reading in data storage
In the second data cell end position reading pointer or instruction, transmitted from the video encoding module signal to the front end
Processing module, or transmitted from the back end processing module signal to the video encoding module.
18. video coding apparatus according to claim 12, it is characterised in that handshake module is coupled to the Video coding
Module with this per one by one or multiple processing modules.
19. video coding apparatus according to claim 18, it is characterised in that only the handshake module is directly accessed the number
According to memory, and by being coupled to the handshake module of the video encoding module and the front end processing block, the front-end processing
Module writes to the first memory and the video encoding module and read from the data storage, or the Video coding mould
Block write to the second memory by being coupled to the handshake module of the video encoding module and the back end processing module and
The back end processing module second is deposited by being coupled to the handshake module of the video encoding module and the back end processing module from this
Read in reservoir.
20. video coding apparatus according to claim 18, it is characterised in that the handshake module and the indirect access number
According to memory, and wherein the front end processing block writes direct the first memory and the video encoding module directly from this
Read in first memory, or the video encoding module write direct to the second memory and the back end processing module from
Directly read in the second memory.
21. video coding apparatus according to claim 18, it is characterised in that only the handshake module and the video are compiled
Code module is directly accessed the data storage with one or more processing module one of both, wherein one or more processing modules
It is related to the data storage, and the front end processing block is write direct to the first memory and the video encoding module
Read by being coupled to the video encoding module with the handshake module of the front end processing block from the first memory；Or
The video encoding module writes direct to the second memory and the back end processing module is by being coupled to the Video coding mould
The handshake module of block and the back end processing module is read from the second memory.
22. video coding apparatus according to claim 18, it is characterised in that only the handshake module and the video are compiled
Code one of module and one or more processing modules are directly accessed the data storage, and
Wherein the front end processing block is write to the first memory by the handshake module, and the video encoding module is direct
Read from the first memory, wherein the handshake module is coupled to the video encoding module and the front end processing block；Or
Person
Wherein the video encoding module is write to the second memory by the handshake module, and the back end processing module is direct
Read from the second memory, wherein the handshake module is coupled to the video encoding module and the back end processing module.
23. video coding apparatus according to claim 12, it is characterised in that the first handshake module is coupled to the video
Coding module and the second handshake module are coupled to one or more processing modules, wherein the front end processing block by this
Two handshake modules are write to the first memory, and the video encoding module by first handshake module from this first storage
Read in device, or the video encoding module is write to the second memory by first handshake module, and the rear end
Module is managed to read from the second memory by second handshake module.
24. a kind of method for video coding, comprising：
Video source is handled to driving into video data using front-end module, and stores the inputting video data in first memory
In；
The first input data of the inputting video data is received from the first memory, and should using video encoding module coding
Inputting video data to the video data compressed, the data access of the wherein first memory is arranged in the first input number
Write according to by the front-end module to the first memory so that the video encoding module reads first input data；
The video data of the compression is provided from the video encoding module to second memory；And
The video data of the first compression of the video data of the compression is received from the second memory, and should using multiplexer
The video data of compression is handled with other data-reusings comprising video data to record or transmit, wherein the second memory
Data access be placed so that the multiplexer this first compression video data by the video encoding module write to
After the second memory, the video data of first compression is read.
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| US201662374966P | 2016-08-15 | 2016-08-15 | |
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| US15/642,586 | 2017-07-06 | ||
| US15/642,586 US20180020222A1 (en) | 2016-07-12 | 2017-07-06 | Apparatus and Method for Low Latency Video Encoding |
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| CN113766235B (en) * | 2021-08-30 | 2023-10-17 | 聚好看科技股份有限公司 | Panoramic video transmission method and equipment |
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