CN107734613B - Power management method and device - Google Patents
Power management method and device Download PDFInfo
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- CN107734613B CN107734613B CN201710964548.1A CN201710964548A CN107734613B CN 107734613 B CN107734613 B CN 107734613B CN 201710964548 A CN201710964548 A CN 201710964548A CN 107734613 B CN107734613 B CN 107734613B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/72—Mobile telephones; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selection
- H04M1/724—User interfaces specially adapted for cordless or mobile telephones
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The present disclosure relates to a power management method and apparatus, which respectively determine an adjusted first input current and an adjusted second input current according to a first input current and a first input voltage of a first power management chip, and a second input current and a second input voltage of a second power management chip, a first corresponding relationship between the input current and the operating efficiency of the first power management chip, and a second corresponding relationship between the input current and the operating efficiency of the second power management chip, therefore, the first power management chip and the second power management chip can work simultaneously under the condition that the system current is overlarge, the input currents of the first power management chip and the second power management chip are reasonably distributed, the total heat power consumption of the first power management chip and the second power management chip is minimum, the service life of the power management chip is prolonged, the working performance of the power management chip is improved, the energy consumption of a battery is reduced, and the endurance time of the terminal device is prolonged.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a power management method and apparatus.
Background
A Power Management (PM) chip is a chip that plays roles in the conversion, distribution, and other Power Management of electric Power in an electronic device. The device is mainly responsible for identifying the power supply amplitude of a Central Processing Unit (CPU), generating corresponding short moment waves and pushing a rear-stage circuit to output power. The power management chip has wide application, and along with the development of information technology, the power management chip is widely applied to terminal equipment such as smart phones and other electronic equipment.
With the increasingly powerful function and the increasingly high operation speed of the CPU, the required electric power is also increased, which results in the increased electric power output by the PM chip to the CPU. When only one PM chip supplies power to the CPU, the current passing through the PM chip is large, the work efficiency of the PM chip is low, and the heat power generated on the PM chip is large, so that the heat flow density of a single PM chip is large, the temperature rise is too high, and the service life and the performance of the PM chip are reduced. And the battery energy will be more consumed, so that the endurance time of the terminal equipment is reduced.
In the related art, in order to ensure the high-power operation of the CPU, two PM chips are usually configured in the terminal device, however, in the related art, even under the condition that the CPU power demand is huge, most of the power can be supplied only through one PM chip of the 2 PM chips, which results in a large current passing through the PM chip, a large thermal power consumption of the PM chip, and a large total thermal power consumption of the 2 PM chips, which results in a serious reduction in the service life and the working performance of the PM chip, an increase in the energy consumption of the battery, and a reduction in the endurance time of the terminal device.
Disclosure of Invention
To overcome the problems in the related art, the present disclosure provides a power management method and apparatus.
According to a first aspect of the present disclosure, a power management method is provided, which is applied to an electronic device including at least two power management chips, the method including: detecting a first input current and a first input voltage of a first power management chip and a second input current and a second input voltage of a second power management chip; according to a first corresponding relation between the input current and the working efficiency of a first power management chip, a second corresponding relation between the input current and the working efficiency of a second power management chip, and the detected first input voltage and second input voltage, respectively determining regulated first input current and regulated second input current from a first current value set contained in the first corresponding relation and a second current value set contained in the second corresponding relation, wherein the sum of the adjusted first input current and the adjusted second input current is equal to the sum of the detected first input current and second input current, and, wherein, of the current values included in the first set of current values and the current values included in the second set of current values, the determined adjusted first input current and the adjusted second input current minimize the total thermal power of the first power management chip and the second power management chip.
In a possible implementation manner, determining, according to a first corresponding relationship between an input current and an operating efficiency of a first power management chip, a second corresponding relationship between an input current and an operating efficiency of a second power management chip, and the detected first input voltage and second input voltage, an adjusted first input current and an adjusted second input current from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship, respectively, includes: selecting a first current value from the first set of current values and a second current value from the second set of current values, resulting in one or more current value pairs, wherein the sum of the first current value and the second current value in each current value pair is equal to the sum of the detected first input current and second input current; for the first current value and the second current value in each current value pair, the following operations are performed: determining a first working efficiency corresponding to the first current value according to a first corresponding relation, and determining a second working efficiency corresponding to the second current value according to a second corresponding relation; calculating a first thermal power of the first power management chip according to the detected first input voltage, the detected first current value and the detected first working efficiency, and calculating a second thermal power of the second power management chip according to the detected second input voltage, the detected second current value and the detected second working efficiency; calculating the sum of the first thermal power and the second thermal power as the total thermal power; and determining the minimum value in the total thermal power obtained by aiming at each current value pair, taking the first current value in the current value pair corresponding to the minimum value as the adjusted first input current, and taking the second current value in the current value pair corresponding to the minimum value as the adjusted second input current.
In one possible implementation, calculating a sum of the first thermal power and the second thermal power as the total thermal power includes:
calculating the total thermal power according to the following formula 1;
Pa＝(1-η1(Ian))×Ian×V1+(1-η2(Iam))×Iam×V2formula 1
Wherein, PaRepresents the total thermal power, I, corresponding to the current value pair aanRepresenting a first current value, I, of the current value pair aamRepresenting a second current value, V, of the pair of current values a1Representing a first input voltage, V2Representing the second input voltage, η1(Ian) Indicates a first current value I determined according to the first correspondenceanFirst working efficiency of2(Iam) Indicating a value corresponding to the second current value I determined according to the second correspondenceamThe second operating efficiency of (1).
In a possible implementation manner, determining, according to a first corresponding relationship between an input current and an operating efficiency of a first power management chip, a second corresponding relationship between an input current and an operating efficiency of a second power management chip, and the detected first input voltage and second input voltage, an adjusted first input current and an adjusted second input current from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship, respectively, includes: under the condition that the first input current and the second input current meet the current regulation condition, according to a first corresponding relation between the input current and the working efficiency of the first power management chip, a second corresponding relation between the input current and the working efficiency of the second power management chip, and the detected first input voltage and the detected second input voltage, the regulated first input current and the regulated second input current are respectively determined from a first current value set contained in the first corresponding relation and a second current value set contained in the second corresponding relation.
In one possible implementation, the first input current and the second input current satisfy the current regulation condition if the first input current is greater than a first current regulation threshold and the second input current is greater than a second current regulation threshold, or the first input current and the second input current satisfy the current regulation condition if a sum of the first input current and the second input current is greater than a third current regulation threshold.
According to a second aspect of the embodiments of the present disclosure, there is provided a power management apparatus applied to an electronic device including at least two power management chips, the apparatus including: the detection module is used for detecting a first input current and a first input voltage of the first power management chip and a second input current and a second input voltage of the second power management chip; a determining module, configured to determine, according to a first corresponding relationship between an input current and an operating efficiency of a first power management chip, a second corresponding relationship between an input current and an operating efficiency of a second power management chip, and the detected first input voltage and second input voltage, an adjusted first input current and an adjusted second input current from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship, respectively, where a sum of the adjusted first input current and the adjusted second input current is equal to a sum of the detected first input current and the detected second input current, and where, among current values included in the first current value set and current values included in the second current value set, the determined adjusted first input current and the adjusted second input current cause a total thermal current of the first power management chip and the second power management chip The power is minimal.
In one possible implementation manner, the determining module includes: a first determination submodule for selecting a first current value from the first set of current values and a second current value from the second set of current values, resulting in one or more current value pairs, wherein the sum of the first current value and the second current value in each current value pair is equal to the sum of the detected first input current and second input current; a second determination submodule, configured to, for the first current value and the second current value in each current value pair, perform the following operations: determining a first working efficiency corresponding to the first current value according to a first corresponding relation, and determining a second working efficiency corresponding to the second current value according to a second corresponding relation; calculating a first thermal power of the first power management chip according to the detected first input voltage, the detected first current value and the detected first working efficiency, and calculating a second thermal power of the second power management chip according to the detected second input voltage, the detected second current value and the detected second working efficiency; calculating the sum of the first thermal power and the second thermal power as the total thermal power; and the third determining submodule is used for determining the minimum value in the total thermal power obtained by aiming at each current value pair, taking the first current value in the current value pair corresponding to the minimum value as the adjusted first input current, and taking the second current value in the current value pair corresponding to the minimum value as the adjusted second input current.
In one possible implementation, calculating a sum of the first thermal power and the second thermal power as the total thermal power includes: calculating the total thermal power according to the following formula 1;
Pa＝(1-η1(Ian))×Ian×V1+(1-η2(Iam))×Iam×V2formula 1
Wherein, PaRepresents the total thermal power, I, corresponding to the current value pair aanRepresenting a first current value, I, of the current value pair aamRepresenting a second current value, V, of the pair of current values a1Representing a first input voltage, V2Representing the second input voltage, η1(Ian) Indicates a first current value I determined according to the first correspondenceanFirst working efficiency of2(Iam) Indicating a value corresponding to the second current value I determined according to the second correspondenceamThe second operating efficiency of (1).
In a possible implementation manner, the determining module is configured to determine, according to a first corresponding relationship between an input current and a working efficiency of a first power management chip, a second corresponding relationship between the input current and the working efficiency of a second power management chip, and the detected first input voltage and the detected second input voltage, an adjusted first input current and an adjusted second input current from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship, when the first input current and the second input current satisfy a current adjustment condition
In one possible implementation, the first input current and the second input current satisfy the current regulation condition if the first input current is greater than a first current regulation threshold and the second input current is greater than a second current regulation threshold, or the first input current and the second input current satisfy the current regulation condition if a sum of the first input current and the second input current is greater than a third current regulation threshold.
According to a third aspect of the present disclosure, there is provided a power management apparatus, the apparatus comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the steps of the above method.
According to a fourth aspect of the present disclosure, a computer-readable storage medium is proposed, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the above-mentioned method.
The aspects of the disclosure can ensure that the first power management chip and the second power management chip work simultaneously under the condition of overlarge system current by detecting the first input current and the first input voltage of the first power management chip and the second input current and the second input voltage of the second power management chip, respectively determining the adjusted first input current and the adjusted second input current from the first current value set contained in the first corresponding relation and the second current value set contained in the second corresponding relation according to the first corresponding relation between the input current and the working efficiency of the first power management chip, the second corresponding relation between the input current and the working efficiency of the second power management chip and the detected first input voltage and second input voltage, thereby avoiding the condition of uneven load of the power management chips, and the input currents of the first power management chip and the second power management chip can be reasonably distributed under the condition of overlarge system current, so that the total thermal power consumption of the first power management chip and the second power management chip is minimum, the service life of the power management chip is prolonged, the working performance of the power management chip is improved, the energy consumption of a battery is reduced, and the endurance time of the terminal equipment is prolonged.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic diagram illustrating an application scenario of a power management method according to an exemplary embodiment.
FIG. 2 is a flow diagram illustrating a method of power management according to an example embodiment.
FIG. 3 is a flowchart illustrating one power management method step 102 according to one example of an exemplary embodiment.
FIG. 4 is a block diagram illustrating a power management device according to an example embodiment.
Fig. 5 is a block diagram of a power management device according to an example of an example embodiment.
Fig. 6 is a block diagram illustrating a terminal device 800 for power management according to an example embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
Fig. 1 is a schematic diagram illustrating an application scenario of a power management method according to an exemplary embodiment. The method may be applied to an electronic device comprising at least two power management chips. Fig. 1 schematically shows the connection relationship between a current regulator 14 and a power supply 11, a first power management chip 12, a second power management chip 13 and a central processor 15 in a terminal device, wherein the current regulator may be a device capable of implementing the current management method or apparatus of the present disclosure. However, it should be understood by those skilled in the art that the current management method and apparatus of the present disclosure may be implemented in other ways, for example, may be integrated in a certain power management chip.
As shown in fig. 1, the power source 11 may be connected to the central processing unit 15 through a first power management chip 12 and a second power management chip 13, respectively, and the first power management chip 12 and the second power management chip 13 are jointly responsible for managing the power supplied to the central processing unit 15. In terms of hardware, the first power management chip 12 and the second power management chip 13 can simultaneously supply power to the central processing unit 15 in any high-power scene.
As shown in fig. 1, the current regulator 14 may be connected to the first power management chip 12 and the second power management chip 13, respectively, to detect an input current (first input current), an input voltage (first input voltage) of the first power management chip 12, and an input current (second input current) and an input voltage (second input voltage) of the second power management chip 13, respectively, and determine the adjusted first input current and the adjusted second input current to control the distribution of the output current of the power supply 11 between the first power management chip 12 and the second power management chip 13.
The current regulator 14 may also be connected to the power supply 11 and the central processing unit 15, respectively, to thereby obtain the operating states of the power supply 11 and the central processing unit 15.
FIG. 2 is a flow diagram illustrating a method of power management according to an example embodiment. The method can be applied to terminal equipment. As shown in fig. 2, the method includes step 101 and step 102.
In step 101, a first input current and a first input voltage of a first power management chip and a second input current and a second input voltage of a second power management chip are detected.
As an example of the present embodiment, the first input current and the first input voltage of the first power management chip, and the second input current and the second input voltage of the second power management chip may be detected at fixed time intervals. The fixed time interval may be arbitrarily set as required, and may be, for example, 1 second.
In step 102, according to a first corresponding relationship between the input current and the operating efficiency of the first power management chip, a second corresponding relationship between the input current and the operating efficiency of the second power management chip, and the detected first input voltage and second input voltage, an adjusted first input current and an adjusted second input current are respectively determined from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship.
Wherein the sum of the adjusted first input current and the adjusted second input current is equal to the sum of the detected first input current and second input current, an
And determining the regulated first input current and the regulated second input current in the current values contained in the first current value set and the current values contained in the second current value set, wherein the determined regulated first input current and the regulated second input current enable the total thermal power of the first power management chip and the second power management chip to be minimum.
In this embodiment, by detecting the first input current and the first input voltage of the first power management chip, and the second input current and the second input voltage of the second power management chip, according to the first corresponding relationship between the input current and the operating efficiency of the first power management chip, the second corresponding relationship between the input current and the operating efficiency of the second power management chip, and the detected first input voltage and the detected second input voltage, the adjusted first input current and the adjusted second input current are respectively determined from the first current value set included in the first corresponding relationship and the second current value set included in the second corresponding relationship, so as to ensure that the first power management chip and the second power management chip operate simultaneously when the system current is too large, thereby avoiding the situation of uneven load of the power management chip, and simultaneously, when the system current is too large, the input currents of the first power management chip and the second power management chip are reasonably distributed, so that the total thermal power consumption of the first power management chip and the second power management chip is minimum, the service life of the power management chip is prolonged, the working performance of the power management chip is improved, the energy consumption of a battery is reduced, and the endurance time of the terminal equipment is prolonged.
In a possible implementation manner, in step 102, in a case that the first input current and the second input current satisfy the current regulation condition, according to a first corresponding relationship between the input current and the operating efficiency of the first power management chip, a second corresponding relationship between the input current and the operating efficiency of the second power management chip, and the detected first input voltage and second input voltage, the regulated first input current and the regulated second input current may be respectively determined from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship.
The current regulation condition may be arbitrarily set as required, and when the first input current and the second input current satisfy the condition, the operation in step 102 may be performed to regulate the distribution of the current between the first power management chip and the second power management chip, and if the first input current and the second input current do not satisfy the current regulation condition, the current may be randomly distributed between the first power management chip and the second power management chip, or the original distribution manner is not changed, which is not limited by the present disclosure.
By setting the current regulation condition, the input currents of the first power management chip and the second power management chip can be reasonably regulated under the condition that the system current is overlarge, and meanwhile, the current is not regulated under the condition that the system current is small, so that the calculation burden of the system is reduced.
In one possible implementation, the first input current and the second input current satisfy the current regulation condition when the first input current is greater than a first current regulation threshold and the second input current is greater than a second current regulation threshold. For example, when the first input current is 65 milliamps and the second input current is 65 milliamps, if the first current adjustment threshold is 50 milliamps and the second current adjustment threshold is 60 milliamps, the first input current and the second input current satisfy the current adjustment condition.
In another possible implementation, the first input current and the second input current satisfy the current regulation condition in a case where a sum of the first input current and the second input current is greater than a third current regulation threshold. For example, when the first input current is 70 milliamps and the second input current is 100 milliamps, if the third current adjustment threshold is 150 milliamps, the first input current and the second input current satisfy the current adjustment condition.
The product of the input current and the input voltage of the power management chip can be regarded as the input electric power of the power management chip, one part of the input electric power is output to supply the load, the part can be called effective power, and the other part forms heat loss, and can be called thermal power. The operating efficiency of the power management chip may be expressed as a percentage between the active power and the input electrical power. The higher the operating efficiency, the smaller the heat loss. Generally, the working efficiency increases with the increase of the input current, and after the input current reaches a certain threshold value, the working efficiency decreases with the increase of the input current.
In one possible implementation manner, a first corresponding relationship between the input current and the working efficiency of the first power management chip and a second corresponding relationship between the input current and the working efficiency of the second power management chip may be stored in the mobile terminal in advance. For example, for the first power management chip, discrete first current values a {10,20,30,40,50,60,70,80,90} (unit: milliamp) and first operating efficiencies corresponding to the respective first current values may be stored as a first correspondence, and for the second power management chip, discrete second current values B {10,20,30,40,50,60},7(0 unit, bit 8: 0, milli 9 ampere 0) and second operating efficiencies corresponding to the respective second current values may be stored as a second correspondence. Table 1 gives examples of the first correspondence and the second correspondence.
TABLE 1
| First current value (milliamp) | First working efficiency | Second Current value (milliampere) | Second work efficiency |
| 10 | 78％ | 10 | 60％ |
| 20 | 81％ | 20 | 65％ |
| 30 | 85％ | 30 | 70％ |
| 40 | 90％ | 40 | 80％ |
| 50 | 85％ | 50 | 85％ |
| 60 | 83％ | 60 | 90％ |
| 70 | 80％ | 70 | 85％ |
| 80 | 78％ | 80 | 80％ |
| 90 | 75％ | 90 | 75％ |
| 100 | 70％ | 100 | 75％ |
| 110 | 65％ | 110 | 72％ |
| 120 | 63％ | 120 | 71％ |
| 130 | 60％ | 130 | 68％ |
| 140 | 55％ | 140 | 65％ |
| 150 | 50％ | 150 | 60％ |
Wherein, for a certain minimum current interval (for example, less than 30 milliamperes), the working efficiency can also be set to be constant so as to reduce the calculation amount of the subsequent calculation of the heating power consumption.
FIG. 3 is a flowchart illustrating one power management method step 102 according to one example of an exemplary embodiment. As shown in fig. 3, step 102 may include steps 201 through 203.
In step 201, a first current value is selected from a first set of current values and a second current value is selected from a second set of current values, resulting in one or more current value pairs, wherein the sum of the first current value and the second current value in each current value pair is equal to the sum of the detected first input current and second input current.
For example, if the first set of current values is a ═ {10,20,30,40,50,60,70,80,90} (unit: milliamps) and the second set of current values is B ═ {10,20,30,40,50,60,70,80,90} (unit: milliamps), and the first input current is detected at 65 milliamps and the second input current at 65 milliamps, the sum of which is 130 milliamps, then each current value pair can be determined to be C { (40,90), (50,80), (60,70), (70,60), (80,50), (90,40) } (unit: milliamps).
In step 202, for the first current value and the second current value in each current value pair, the following operations are performed:
and determining a first working efficiency corresponding to the first current value according to the first corresponding relation, and determining a second working efficiency corresponding to the second current value according to the second corresponding relation.
For example, according to the example shown in table 1 above, if the current pair is C { (40,90), (50,80), (60,70), (70,60), (80,50), (90,40) } (unit: milliamp), the first and second operating efficiencies determined according to the respective current pairs, the first correspondence relationship and the second correspondence relationship are D { (90%, 75%), (85%, 80%), (83%, 85%), (80%, 90%), (78%, 85%), (75%, 80%) }
And calculating a first thermal power of the first power management chip according to the detected first input voltage, first current value and first working efficiency, and calculating a second thermal power of the second power management chip according to the detected second input voltage, second current value and second working efficiency.
And calculating the sum of the first thermal power and the second thermal power as the total thermal power.
As an example of the embodiment, calculating the sum of the first thermal power and the second thermal power as the total thermal power may include:
the total thermal power was calculated according to the following equation 1.
Pa＝(1-η1(Ian))×Ian×V1+(1-η2(Iam))×Iam×V2Formula 1
Wherein, PaRepresents the total thermal power, I, of the current value pair aanRepresenting a first current value, I, of the current value pair aamRepresenting a second current value, V, of the pair of current values a1Representing a first input voltage, V2Representing the second input voltage, η1(Ian) Indicates a first current value I determined according to the first correspondenceanFirst working efficiency of2(Iam) Indicating a value corresponding to the second current value I determined according to the second correspondenceamThe second operating efficiency of (1).
For example, if each current pair is C { (40,90), (50,80), (60,70), (70,60), (80,50), (90,40) } (unit: milliamp), the first and second operating efficiencies determined according to the respective current pair, the first correspondence relationship, and the second correspondence relationship are D { (90%, 75%), (85%, 80%), (83%, 85%), (80%, 90%), (78%, 85%), (75%, 80%) }, V { (90%, 75%, 80%) } or13.5V ═ V2At 3.5 volts, the total thermal power for the current value pair (40,90) is determined according to equation 1 as:
(1-90％)×0.04×3.5+(1-75％)×0.09×3.5＝0.0927W。
similarly, the total thermal power corresponding to the current value pair (50,80) is 0.08225W, the total thermal power corresponding to the current value pair (60,70) is 0.07245W, the total thermal power corresponding to the current value pair (70,60) is 0.07W, the total thermal power corresponding to the current value pair (80,50) is 0.08785W, and the total thermal power corresponding to the current value pair (90,40) is 0.10675W.
In step 203, the minimum value of the total thermal power obtained for each current value pair is determined, the first current value of the current value pair corresponding to the minimum value is used as the adjusted first input current, and the second current value of the current value pair corresponding to the minimum value is used as the adjusted second input current.
For example, as described in the above example, the adjusted first input current may be determined to be 70 milliamps and the adjusted second input current may be determined to be 60 milliamps based on the current value pair (70,60) corresponding to the minimum total thermal power value of 0.07.
In this embodiment, the minimum value in the total thermal power obtained for each current value pair is quickly determined according to the first corresponding relationship and the second corresponding relationship, the first current value in the current value pair corresponding to the minimum value is used as the adjusted first input current, and the second current value in the current value pair corresponding to the minimum value is used as the adjusted second input current, so that the minimum total thermal power of the first current management chip and the second current management chip after adjustment is ensured, the service life of the power management chip is prolonged, the working performance of the power management chip is improved, the energy consumption of the battery is reduced, and the endurance time of the terminal device is prolonged.
FIG. 4 is a block diagram illustrating a power management device according to an example embodiment. The device is applied to electronic equipment comprising at least two power management chips. Referring to fig. 4, the apparatus includes a detection module 41 and a determination module 42.
The detection module 41 is configured to detect a first input current and a first input voltage of a first power management chip, and a second input current and a second input voltage of a second power management chip
The determining module 42 is configured to determine the adjusted first input current and the adjusted second input current from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship according to a first corresponding relationship between the input current and the operating efficiency of the first power management chip, a second corresponding relationship between the input current and the operating efficiency of the second power management chip, and the detected first input voltage and the detected second input voltage,
wherein the sum of the adjusted first input current and the adjusted second input current is equal to the sum of the detected first input current and second input current, an
Wherein, of the current values included in the first set of current values and the current values included in the second set of current values, the determined adjusted first input current and the adjusted second input current minimize the total thermal power of the first power management chip and the second power management chip.
Fig. 5 is a block diagram of a power management device according to an example of an example embodiment. Components in fig. 5 that are numbered the same as those in fig. 4 have the same functions, and detailed descriptions of these components are omitted for the sake of brevity. As shown in figure 5 of the drawings,
in a possible implementation manner, the determining module 42 includes a first determining submodule 421, a second determining submodule 422, and a third determining submodule 423:
the first determination submodule 421 is configured to select a first current value from the first set of current values and a second current value from the second set of current values, resulting in one or more current value pairs, wherein the sum of the first current value and the second current value in each current value pair is equal to the sum of the detected first input current and second input current.
The second determination submodule 422 is configured to, for the first current value and the second current value in each current value pair, perform the following operations:
and determining a first working efficiency corresponding to the first current value according to the first corresponding relation, and determining a second working efficiency corresponding to the second current value according to the second corresponding relation.
Calculating first thermal power of the first power management chip according to the detected first input voltage, the detected first current value and the detected first working efficiency, and calculating second thermal power of the second power management chip according to the detected second input voltage, the detected second current value and the detected second working efficiency.
And calculating the sum of the first thermal power and the second thermal power as the total thermal power.
The third determining submodule 423 is configured to determine a minimum value of the total thermal power obtained for each current value pair, with a first current value of the current value pair corresponding to the minimum value as the adjusted first input current and a second current value of the current value pair corresponding to the minimum value as the adjusted second input current.
In one possible implementation, calculating a sum of the first thermal power and the second thermal power as the total thermal power includes:
the total thermal power is calculated according to equation 1 below.
Pa＝(1-η1(Ian))×Ian×V1+(1-η2(Iam))×Iam×V2Formula 1
Wherein, PaRepresents the total thermal power, I, corresponding to the current value pair aanRepresenting a first current value, I, of the current value pair aamRepresenting a second current value, V, of the pair of current values a1Representing a first input voltage, V2Representing the second input voltage, η1(Ian) Indicates a first current value I determined according to the first correspondenceanFirst working efficiency of2(Iam) Indicating a value corresponding to the second current value I determined according to the second correspondenceamThe second operating efficiency of (1).
In a possible implementation manner, the determining module 42 is configured to determine, according to a first corresponding relationship between the input current and the operating efficiency of the first power management chip, a second corresponding relationship between the input current and the operating efficiency of the second power management chip, and the detected first input voltage and the detected second input voltage, the adjusted first input current and the adjusted second input current from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship, respectively, when the first input current and the second input current satisfy the current adjusting condition.
In one possible implementation, the first input current and the second input current satisfy the current regulation condition if the first input current is greater than a first current regulation threshold and the second input current is greater than a second current regulation threshold, or the first input current and the second input current satisfy the current regulation condition if a sum of the first input current and the second input current is greater than a third current regulation threshold.
With regard to the apparatus in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be described in detail here.
Fig. 6 is a block diagram illustrating a terminal device 800 for power management according to an example embodiment. For example, the terminal device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, and the like. The terminal device 800 may be loaded with the power management apparatus described above, or implement the power management method described above.
Referring to fig. 6, terminal device 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input/output (I/O) interface 812, sensor component 814, and communication component 816.
The processing component 802 generally controls overall operation of the terminal device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components 802 may include one or more processors 820 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.
The memory 804 is configured to store various types of data to support operations at the terminal device 800. Examples of such data include instructions for any application or method operating on terminal device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The multimedia component 808 comprises a screen providing an output interface between the terminal device 800 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. When the terminal device 800 is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive an external audio signal when the terminal device 800 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.
The I/O interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
In an exemplary embodiment, the terminal device 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.
In an exemplary embodiment, a non-transitory computer-readable storage medium comprising instructions, such as the memory 804 comprising instructions, executable by the processor 820 of the terminal device 800 to perform the above-described method is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (8)
1. A power management method is applied to an electronic device comprising at least two power management chips, and is characterized by comprising the following steps:
detecting a first input current and a first input voltage of a first power management chip and a second input current and a second input voltage of a second power management chip;
under the condition that the first input current and the second input current meet a current regulation condition, respectively determining regulated first input current and regulated second input current from a first current value set contained in the first corresponding relation and a second current value set contained in the second corresponding relation according to a first corresponding relation between the input current and the working efficiency of a first power management chip, a second corresponding relation between the input current and the working efficiency of a second power management chip and the detected first input voltage and second input voltage, wherein the current regulation condition is used for representing the magnitude of system current; the first input current and the second input current satisfy a current regulation condition in a case where the first input current is greater than a first current regulation threshold and the second input current is greater than a second current regulation threshold, or the first input current and the second input current satisfy the current regulation condition in a case where a sum of the first input current and the second input current is greater than a third current regulation threshold;
wherein the sum of the adjusted first input current and the adjusted second input current is equal to the sum of the detected first input current and second input current, an
Wherein, of the current values included in the first set of current values and the current values included in the second set of current values, the determined adjusted first input current and the adjusted second input current minimize the total thermal power of the first power management chip and the second power management chip.
2. The method of claim 1, wherein determining the adjusted first input current and the adjusted second input current from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship according to a first corresponding relationship between the input current and the operating efficiency of a first power management chip, a second corresponding relationship between the input current and the operating efficiency of a second power management chip, and the detected first input voltage and the detected second input voltage respectively comprises:
selecting a first current value from the first set of current values and a second current value from the second set of current values, resulting in one or more current value pairs, wherein the sum of the first current value and the second current value in each current value pair is equal to the sum of the detected first input current and second input current;
for the first current value and the second current value in each current value pair, the following operations are performed:
determining a first working efficiency corresponding to the first current value according to a first corresponding relation, and determining a second working efficiency corresponding to the second current value according to a second corresponding relation;
calculating a first thermal power of the first power management chip according to the detected first input voltage, the detected first current value and the detected first working efficiency, and calculating a second thermal power of the second power management chip according to the detected second input voltage, the detected second current value and the detected second working efficiency;
calculating the sum of the first thermal power and the second thermal power as the total thermal power;
and determining the minimum value in the total thermal power obtained by aiming at each current value pair, taking the first current value in the current value pair corresponding to the minimum value as the adjusted first input current, and taking the second current value in the current value pair corresponding to the minimum value as the adjusted second input current.
3. The method of claim 2, wherein calculating a sum of the first thermal power and the second thermal power as the total thermal power comprises:
calculating the total thermal power according to the following formula 1;
Pa＝(1-η1(Ian))×Ian×V1+(1-η2(Iam))×Iam×V2formula 1
Wherein, PaRepresents the total thermal power, I, corresponding to the current value pair aanRepresents the second of the current value pairs aA current value, IamRepresenting a second current value, V, of the pair of current values a1Representing a first input voltage, V2Representing the second input voltage, η1(Ian) Indicates a first current value I determined according to the first correspondenceanFirst working efficiency of2(Iam) Indicating a value corresponding to the second current value I determined according to the second correspondenceamThe second operating efficiency of (1).
4. A power management device applied to an electronic device comprising at least two power management chips, the device comprising:
the detection module is used for detecting a first input current and a first input voltage of the first power management chip and a second input current and a second input voltage of the second power management chip;
a determining module, configured to determine, according to a first corresponding relationship between an input current and an operating efficiency of a first power management chip, a second corresponding relationship between the input current and the operating efficiency of a second power management chip, and the detected first input voltage and the detected second input voltage, an adjusted first input current and an adjusted second input current from a first current value set included in the first corresponding relationship and a second current value set included in the second corresponding relationship, respectively, when the first input current and the second input current satisfy a current adjustment condition, where the current adjustment condition is used to characterize a magnitude of a system current; the first input current and the second input current satisfy a current regulation condition in a case where the first input current is greater than a first current regulation threshold and the second input current is greater than a second current regulation threshold, or the first input current and the second input current satisfy the current regulation condition in a case where a sum of the first input current and the second input current is greater than a third current regulation threshold;
wherein the sum of the adjusted first input current and the adjusted second input current is equal to the sum of the detected first input current and second input current, an
Wherein, of the current values included in the first set of current values and the current values included in the second set of current values, the determined adjusted first input current and the adjusted second input current minimize the total thermal power of the first power management chip and the second power management chip.
5. The apparatus of claim 4, wherein the determining module comprises:
a first determination submodule for selecting a first current value from the first set of current values and a second current value from the second set of current values, resulting in one or more current value pairs, wherein the sum of the first current value and the second current value in each current value pair is equal to the sum of the detected first input current and second input current;
a second determination submodule, configured to, for the first current value and the second current value in each current value pair, perform the following operations:
determining a first working efficiency corresponding to the first current value according to a first corresponding relation, and determining a second working efficiency corresponding to the second current value according to a second corresponding relation;
calculating a first thermal power of the first power management chip according to the detected first input voltage, the detected first current value and the detected first working efficiency, and calculating a second thermal power of the second power management chip according to the detected second input voltage, the detected second current value and the detected second working efficiency;
calculating the sum of the first thermal power and the second thermal power as the total thermal power;
and the third determining submodule is used for determining the minimum value in the total thermal power obtained by aiming at each current value pair, taking the first current value in the current value pair corresponding to the minimum value as the adjusted first input current, and taking the second current value in the current value pair corresponding to the minimum value as the adjusted second input current.
6. The apparatus of claim 5, wherein calculating a sum of the first thermal power and the second thermal power as the total thermal power comprises:
calculating the total thermal power according to the following formula 1;
Pa＝(1-η1(Ian))×Ian×V1+(1-η2(Iam))×Iam×V2formula 1
Wherein, PaRepresents the total thermal power, I, corresponding to the current value pair aanRepresenting a first current value, I, of the current value pair aamRepresenting a second current value, V, of the pair of current values a1Representing a first input voltage, V2Representing the second input voltage, η1(Ian) Indicates a first current value I determined according to the first correspondenceanFirst working efficiency of2(Iam) Indicating a value corresponding to the second current value I determined according to the second correspondenceamThe second operating efficiency of (1).
7. A power management device, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform the steps of the method of any one of claims 1 to 3.
8. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 3.
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