CN107731703A - A kind of preparation method of interconnection structure and preparation method thereof and semiconductor devices - Google Patents
A kind of preparation method of interconnection structure and preparation method thereof and semiconductor devices Download PDFInfo
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- CN107731703A CN107731703A CN201710772600.3A CN201710772600A CN107731703A CN 107731703 A CN107731703 A CN 107731703A CN 201710772600 A CN201710772600 A CN 201710772600A CN 107731703 A CN107731703 A CN 107731703A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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Abstract
The invention discloses the preparation method of a kind of interconnection structure and preparation method thereof He semiconductor devices, including：One substrat structure is provided；After the substrat structure etching groove, first time monitoring is carried out to the groove pattern；After the lamination of barrier layer and Seed Layer is sequentially depositing along the inwall of the groove, second is carried out to the lamination pattern and is monitored；Interconnection line is formed in the groove that the lamination is formed.As shown in the above, technical scheme provided by the invention, during interconnection line is made, by carrying out first time monitoring to groove pattern, then second is carried out to lamination pattern to monitor, supported by monitoring to provide subsequent technique every time on the parameter of pattern, the situation the defects of interior void for the interconnection line for improving formation；And pinpointed the problems ahead of time when deviation occurs in preamble technique, reduce and make loss, ensure that production efficiency is high.
Description
Technical field
The present invention relates to interconnection structure manufacture technology field, more specifically, is related to a kind of interconnection structure and its making
The preparation method of method and semiconductor devices.
Background technology
At present, in the manufacture craft of semiconductor devices, multiple layer metal interconnection can be formed on substrate according to different needs
Layer, every layer of metal interconnecting layer include interconnection line, and this just needs the etching that groove is carried out to the dielectric layer on substrate, then in ditch
The interconnection line is formed in groove, the pattern and its stability of interconnection line produce very big influence to the performance of semiconductor devices.It is existing
There is technology during interconnection line is made, it is necessary to form multiple structure sheafs in groove and make it that the pattern of groove is unstable,
And then the defects of interior void for the interconnection line for often causing to ultimately form so that production efficiency is relatively low.
The content of the invention
In view of this, the invention provides the preparation method of a kind of interconnection structure and preparation method thereof He semiconductor devices,
During interconnection line is made, by carrying out first time monitoring to groove pattern, second then is carried out to lamination pattern and is supervised
Survey, supported by monitoring to provide subsequent technique every time on the parameter of pattern, improve interior void of the interconnection line of formation etc.
The situation of defect；And pinpointed the problems ahead of time when deviation occurs in preamble technique, reduce and make loss, ensure that production efficiency is high.
To achieve the above object, technical scheme provided by the invention is as follows：
A kind of preparation method of interconnection structure, including：
One substrat structure is provided；
After the substrat structure etching groove, first time monitoring is carried out to the groove pattern；
After the lamination of barrier layer and Seed Layer is sequentially depositing along the inwall of the groove, the is carried out to the lamination pattern
Secondary monitoring；
Interconnection line is formed in the groove that the lamination is formed.
Optionally, the parameter of the first time monitoring comprises at least the A/F of the groove；
And the parameter of second of monitoring comprises at least the A/F of the lamination.
Optionally, interconnection line is formed in the groove that the lamination is formed includes：
Link material filling is carried out in the groove that the lamination is formed；
There is the link material to fill a side surface to the substrat structure and carry out planarization process, with described in removal
The interconnection line is formed after the unnecessary link material of link material filling.
Optionally, after the interconnection line is formed, in addition to：
Enter pattern monitoring to the interconnection line.
Optionally, it is described that there is the link material to fill side surface progress planarization process to the substrat structure
For：
There is the link material to fill a side surface using chemical mechanical milling tech to the substrat structure to put down
Smoothization processing.
Optionally, the first time monitoring and second of monitoring are monitored using CDSEM.
Optionally, the width of the groove is not more than 40 nanometers.
Optionally, the barrier layer is tantalum layer；
Or, the barrier layer is the tantalum nitride layer and tantalum layer sequentially formed.
Optionally, the thickness on the barrier layer is less than 10 nanometers.
Optionally, the Seed Layer is copper seed layer.
Optionally, the thickness of the Seed Layer is less than 10 nanometers.
Optionally, the interconnection line is copper interconnecting line.
Accordingly, present invention also offers a kind of interconnection structure, the interconnection structure to use the system of above-mentioned interconnection structure
It is made as method.
Accordingly, present invention also offers a kind of preparation method of semiconductor devices, the making side of the semiconductor devices
The preparation method that method includes above-mentioned interconnection structure.
Optionally, the semiconductor devices is three-dimensional storage.
Compared to prior art, technical scheme provided by the invention at least has advantages below：
The invention provides the preparation method of a kind of interconnection structure and preparation method thereof He semiconductor devices, including：There is provided
One substrat structure；After the substrat structure etching groove, first time monitoring is carried out to the groove pattern；Along the groove
Inwall be sequentially depositing the lamination of barrier layer and Seed Layer after, second is carried out to the lamination pattern and is monitored；In the lamination
Interconnection line is formed in the groove of formation.As shown in the above, technical scheme provided by the invention, the mistake of interconnection line is being made
Cheng Zhong, by carrying out first time monitoring to groove pattern, second then is carried out to lamination pattern and is monitored, by monitoring every time
Subsequent technique is provided and supported on the parameter of pattern, the situation the defects of interior void for the interconnection line for improving formation；And
And pinpointed the problems ahead of time when deviation occurs in preamble technique, reduce and make loss, ensure that production efficiency is high.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will to embodiment or
The required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only
Embodiments of the invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to the accompanying drawing of offer.
Fig. 1 is a kind of flow chart of the preparation method for interconnection structure that the embodiment of the present application provides；
Fig. 2 a- Fig. 2 d are structural representation corresponding with each steps of Fig. 1；
Fig. 3 is a kind of forming process flow chart for interconnection line that the embodiment of the present application provides；
Fig. 4 a- Fig. 4 b are the structural representation corresponding with each steps of Fig. 3.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
As described in background, prior art during interconnection line is made, it is necessary to form multiple knots in groove
Structure layer and make it that the pattern of groove is unstable, and then the defects of the interior void for the interconnection line for often causing to ultimately form, make
It is relatively low to obtain production efficiency.
Based on this, the embodiment of the present application provides the making of a kind of interconnection structure and preparation method thereof and semiconductor devices
Method, during interconnection line is made, by carrying out first time monitoring to groove pattern, the then is carried out to lamination pattern
Secondary monitoring, supported by monitoring to provide subsequent technique every time on the parameter of pattern, improve the inside of the interconnection line of formation
The situation of the defects of empty；And pinpointed the problems ahead of time when deviation occurs in preamble technique, reduce and make loss, ensure production
Efficiency high.To achieve the above object, the technical scheme that the embodiment of the present application provides is as follows, specifically combines Fig. 1 to Fig. 4 b to this Shen
Please embodiment provide technical scheme be described in detail.
With reference to shown in figure 1, a kind of flow chart of the preparation method of the interconnection structure provided for the embodiment of the present application, make
Method includes：
S1, provide a substrat structure；
S2, to the substrat structure etching groove after, to the groove pattern carry out first time monitoring；
S3, after being sequentially depositing the lamination of barrier layer and Seed Layer along the inwall of the groove, the lamination pattern is carried out
Second of monitoring；
S4, form interconnection line in the groove that the lamination is formed.
As shown in the above, the technical scheme that the embodiment of the present application provides, during interconnection line is made, passes through
First time monitoring is carried out to groove pattern, then carrying out second to lamination pattern monitors, by monitoring every time to subsequent technique
There is provided and supported on the parameter of pattern, the situation the defects of interior void for the interconnection line for improving formation；And in preamble technique
Pinpointed the problems ahead of time when there is deviation, reduce and make loss, ensure that production efficiency is high.
It is described in more detail with reference to Fig. 2 a- Fig. 2 d preparation methods provided the above embodiments of the present application,
Fig. 2 a- Fig. 2 d are structural representation corresponding with each steps of Fig. 1.
Join shown in Fig. 2 a, corresponding step S1 a, there is provided substrat structure 100.
The preparation method that the embodiment of the present application provides is to make interconnection structure to form the method for interconnection layer.Thus, this Shen
Please the substrat structure that provides of embodiment include Semiconductor substrate, and multiple dielectric layers being grown in Semiconductor substrate are most upper
One layer of dielectric layer is the structure sheaf of interconnection layer to be produced, and remaining dielectric layer can be the interconnection layer for making and finishing, to this
The application is not particularly limited.Wherein, it is necessary to dielectric layer by the interconnection layer to be produced during subsequent etching groove
Entirely run through.
With reference to shown in figure 2b, corresponding step S2, to the etching of the progress groove 200 of substrat structure 100, and to having etched
The pattern of complete groove 200 carries out first time monitoring.
After etching groove, the pattern of groove is monitored, and then structural parameters branch is provided for subsequent technique
Hold；Meanwhile the pattern of groove is monitored, it can understand whether the groove has defect ahead of time, and can interpolate that this is lacked
Situations such as whether can repairing is fallen into, the problem of to understand groove ahead of time, and reduces and makes loss.
In the embodiment of the application one, the etching of respective grooves can be performed etching using photoetching process, can also be used
Other etching technics are performed etching to groove, and this application is not particularly limited.In addition, the institute that the embodiment of the present application provides
The width for stating groove is not more than 40 nanometers, is specifically as follows 36 nanometers, 32 nanometers, 25 nanometers, 20 nanometers etc., root is needed to this
Specifically chosen according to practical application.
With reference to shown in figure 2c, corresponding step S3, the folded of barrier layer 300 and Seed Layer 400 is sequentially depositing along the inwall of groove
Layer, and after deposited seed layer 400, second of monitoring is carried out to the pattern of the lamination.
After the lamination of barrier layer and Seed Layer makes, pattern monitoring, Jin Erwei are carried out to the lamination of the groove-like
Subsequent technique provides structural parameters and supported；Meanwhile the pattern of the lamination is monitored, whether can understand the lamination ahead of time
With defect, and situations such as whether defect can repair can interpolate that, with ahead of time understand lamination the problem of, and reduce system
Lose.
In the embodiment of the application one, the deposition of barrier layer and Seed Layer is deposited using the vacuum chamber of same board,
And then it can prevent Seed Layer from aoxidizing.Barrier layer can be conductive barrier layer, can also be non-conductive barrier layer, stop
The effect of layer predominantly prevents the diffusion and electromigration of Seed Layer；When on barrier layer being nonconducting barrier layer, because interconnection line needs
To be made electrical contact with other interconnection layers, so, it is necessary to the part for being located at channel bottom to barrier layer carries out windowing processing, make seed
Layer contacts with lower section interconnection layer, same as the prior art to this, therefore does not do unnecessary repeat.
The barrier layer and Seed Layer that the embodiment of the present application provides can be made using physical gas-phase deposition；
In the application other embodiment, it can also be made using other techniques, specific such as sputtering technique, to this application
It is not particularly limited.
In the embodiment of the application one, the barrier layer that the application provides is tantalum layer；
Or, the barrier layer is the tantalum nitride layer and tantalum layer sequentially formed.In the application other embodiment, barrier layer
Can also be other materials barrier layer, this application is not particularly limited, it is necessary to according to Seed Layer in practical application
The parameters such as material are specifically chosen.In addition, the thickness on the barrier layer that the embodiment of the present application provides is less than 10 nanometers, tool
Body can be 8 nanometers, 5 nanometers, 3 nanometers etc., and this application is not particularly limited.
And in the embodiment of the application one, the Seed Layer that the application provides is copper seed layer.The application other
In embodiment, Seed Layer can also be the Seed Layer of other materials, and this application is not specifically limited.In addition, the application is real
The thickness for applying the Seed Layer of example offer is less than 10 nanometers, is specifically as follows 8 nanometers, 5 nanometers, 3 nanometers etc., to this this Shen
It please be not particularly limited.
With reference to shown in figure 2d, corresponding step S4, interconnection line 500 is formed in the groove that lamination is formed.
The material for the interconnection line that the embodiment of the present application provides can be identical with the material of Seed Layer, wherein, the application is implemented
The interconnection line that example provides is copper interconnecting line.In addition, in the application other embodiment, interconnection line can also be other materials
The interconnection line of matter, this application is not particularly limited.
It is described in detail with reference to the manufacturing process of Fig. 3 to Fig. 4 b interconnection lines provided the embodiment of the present application,
Fig. 3 is a kind of forming process flow chart for interconnection line that the embodiment of the present application provides, and Fig. 4 a- Fig. 4 b are and each step phases of Fig. 3
Corresponding structural representation.
Wherein, forming interconnection line in the groove formed in the lamination that the embodiment of the present application provides includes：
S41, link material filling is carried out in the groove that the lamination is formed；
With reference to shown in figure 4a, corresponding step S41, link material filling 500 ' is carried out in the groove that lamination is formed first.
After the barrier layer 300 and the lamination of Seed Layer 400 that the embodiment of the present application provides are formed, lamination can form a groove
Shape, link material then is filled in the groove, to provide basis for the follow-up interconnection line that makes.In the embodiment of the application one
In, the link material that the application provides is metallic copper, wherein, filling link material can be entered using electroplating technology in groove
OK；Or in the application other embodiment, link material is filled in groove to use other techniques to carry out, specifically
Depositing operation is such as used, this application is not particularly limited.
S42, there is the link material to fill side surface progress planarization process to the substrat structure, to remove
The interconnection line is formed after the unnecessary link material of the link material filling.
With reference to shown in figure 4b, corresponding step S42, due to after link material is filled to groove, the line material of formation
Material fills out 500 ' and fills and can be higher than the surface of the substrat structure 100, and forms rough surface, and link material filling is covered
The surface of lid substrat structure 100 and the surface of the lamination of barrier layer 300 and Seed Layer 400, so, it is necessary to the substrat structure
100 surface carries out planarization process, that is, removes unnecessary link material part, and expose substrat structure 100, barrier layer
300 and the surface of Seed Layer 400.
It is described that there is one side surface of link material filling to enter to the substrat structure in the embodiment of the application one
Row planarization process is：
There is the link material to fill a side surface using chemical mechanical milling tech to the substrat structure to put down
Smoothization processing.To this planarization process process, other techniques can also be used to carry out in the application other embodiment, to this
The application is not particularly limited.
Further, after interconnection line is made, the application can also carry out pattern monitoring to interconnection line, to understand
The structural parameters of interconnection line, and judge whether interconnection line has defect, i.e. after the interconnection line is formed, in addition to：
Enter pattern monitoring to the interconnection line.
In the embodiment of the application one, after groove is made, and after the lamination of barrier layer and Seed Layer is made, all need
Carry out pattern monitoring.Because the parameter on influenceing maximum in follow-up interconnection line manufacturing process is groove opening width and lamination
The A/F of the groove of formation, so, the parameter for the first time monitoring that the embodiment of the present application provides is including at least described
The A/F of groove；
And the parameter of second of monitoring comprises at least the A/F of the lamination.
In the embodiment of the application one, first time monitoring and second of monitoring that the application provides use
CDSEM (microspur measurement sweep electron microscope) is monitored, and this application is not particularly limited, the application other
In embodiment, groove pattern and lamination pattern can also be monitored using other equipment.
Accordingly, the embodiment of the present application additionally provides a kind of interconnection structure, and the interconnection structure uses above-mentioned any one reality
The preparation method for applying the interconnection structure of example offer is made.
Connect in addition, the preparation method for the interconnection structure that the embodiment of the present application provides can also be applied to Damascus metal
In the techniques such as Wiring technology, this application is not particularly limited.
Accordingly, the embodiment of the present application additionally provides a kind of preparation method of semiconductor devices, the semiconductor devices
The preparation method that preparation method includes the interconnection structure that above-mentioned any one embodiment provides.
Optionally, the semiconductor devices that the embodiment of the present application provides is three-dimensional storage (3D NAND).In this Shen
Please be in other embodiment, semiconductor devices can also be other specific devices, and this application is not particularly limited.
The preparation method that the embodiment of the present application provides a kind of interconnection structure and preparation method thereof and semiconductor devices, bag
Include：One substrat structure is provided；After the substrat structure etching groove, first time monitoring is carried out to the groove pattern；Along institute
State groove inwall be sequentially depositing the lamination of barrier layer and Seed Layer after, second is carried out to the lamination pattern and is monitored；Institute
State and interconnection line is formed in the groove of lamination formation.As shown in the above, the technical scheme that the embodiment of the present application provides, is making
During making interconnection line, by carrying out first time monitoring to groove pattern, second then is carried out to lamination pattern and is monitored,
Supported by monitoring to provide subsequent technique every time on the parameter of pattern, improve interior void of the interconnection line of formation etc. and lack
Sunken situation；And pinpointed the problems ahead of time when deviation occurs in preamble technique, reduce and make loss, ensure that production efficiency is high.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, defined herein
General Principle can realize in other embodiments without departing from the spirit or scope of the present invention.Therefore, originally
Invention is not intended to be limited to the embodiments shown herein, and is to fit to special with principles disclosed herein and novelty
The consistent most wide scope of point.
Claims (15)
- A kind of 1. preparation method of interconnection structure, it is characterised in that including：One substrat structure is provided；After the substrat structure etching groove, first time monitoring is carried out to the groove pattern；After the lamination of barrier layer and Seed Layer is sequentially depositing along the inwall of the groove, second is carried out to the lamination pattern and is supervised Survey；Interconnection line is formed in the groove that the lamination is formed.
- 2. the preparation method of interconnection structure according to claim 1, it is characterised in that the parameter of the first time monitoring is extremely Include the A/F of the groove less；And the parameter of second of monitoring comprises at least the A/F of the lamination.
- 3. the preparation method of interconnection structure according to claim 1, it is characterised in that in the groove that the lamination is formed Forming interconnection line includes：Link material filling is carried out in the groove that the lamination is formed；There is the link material to fill a side surface to the substrat structure and carry out planarization process, to remove the line material The interconnection line is formed after expecting the unnecessary link material of filling.
- 4. the preparation method of interconnection structure according to claim 3, it is characterised in that after the interconnection line is formed, also Including：Enter pattern monitoring to the interconnection line.
- 5. the preparation method of interconnection structure according to claim 3, it is characterised in that described to have to the substrat structure The link material fills side surface progress planarization process：There is the link material to fill a side surface using chemical mechanical milling tech to the substrat structure to planarize Processing.
- 6. the preparation method of interconnection structure according to claim 1, it is characterised in that first time monitoring and described the Secondary monitoring is monitored using CDSEM.
- 7. the preparation method of interconnection structure according to claim 1, it is characterised in that the width of the groove is not more than 40 Nanometer.
- 8. the preparation method of interconnection structure according to claim 1, it is characterised in that the barrier layer is tantalum layer；Or, the barrier layer is the tantalum nitride layer and tantalum layer sequentially formed.
- 9. the preparation method of interconnection structure according to claim 1, it is characterised in that the thickness on the barrier layer is less than 10 Nanometer.
- 10. the preparation method of interconnection structure according to claim 1, it is characterised in that the Seed Layer is copper seed layer.
- 11. the preparation method of interconnection structure according to claim 1, it is characterised in that the thickness of the Seed Layer is less than 10 nanometers.
- 12. the preparation method of interconnection structure according to claim 1, it is characterised in that the interconnection line is copper interconnecting line.
- 13. a kind of interconnection structure, it is characterised in that the interconnection structure is using mutual described in claim 1~12 any one The preparation method for linking structure is made.
- 14. a kind of preparation method of semiconductor devices, it is characterised in that the preparation method of the semiconductor devices will including right The preparation method for seeking the interconnection structure described in 1~12 any one.
- 15. the preparation method of semiconductor devices according to claim 14, it is characterised in that the semiconductor devices is three Tie up memory.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880477A (en) * | 2018-09-06 | 2020-03-13 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor device |
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| CN1460134A (en) * | 2001-02-23 | 2003-12-03 | 株式会社荏原制作所 | Copper-plating solution, plating method and plating apparatus |
| CN102859035A (en) * | 2009-09-30 | 2013-01-02 | 东京电子株式会社 | Methods for multi-step copper plating on a continuous ruthenium film in recessed features |
| CN103839920A (en) * | 2012-11-20 | 2014-06-04 | 意法半导体公司 | Copper seed layer for an interconnect structure having a doping concentration level gradient |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1460134A (en) * | 2001-02-23 | 2003-12-03 | 株式会社荏原制作所 | Copper-plating solution, plating method and plating apparatus |
| CN102859035A (en) * | 2009-09-30 | 2013-01-02 | 东京电子株式会社 | Methods for multi-step copper plating on a continuous ruthenium film in recessed features |
| CN103839920A (en) * | 2012-11-20 | 2014-06-04 | 意法半导体公司 | Copper seed layer for an interconnect structure having a doping concentration level gradient |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110880477A (en) * | 2018-09-06 | 2020-03-13 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor device |
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Application publication date: 20180223 |