CN107731684A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN107731684A CN107731684A CN201610662883.1A CN201610662883A CN107731684A CN 107731684 A CN107731684 A CN 107731684A CN 201610662883 A CN201610662883 A CN 201610662883A CN 107731684 A CN107731684 A CN 107731684A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 193
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000003475 lamination Methods 0.000 claims abstract description 123
- 239000000725 suspension Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims description 84
- 238000001312 dry etching Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 14
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 9
- 229910052733 gallium Inorganic materials 0.000 claims description 9
- 229910052787 antimony Inorganic materials 0.000 claims description 8
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000010884 ion-beam technique Methods 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052702 rhenium Inorganic materials 0.000 claims description 3
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 230000005641 tunneling Effects 0.000 abstract description 19
- 238000009826 distribution Methods 0.000 abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000000873 masking effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000004767 nitrides Chemical group 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 241000243251 Hydra Species 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- XSKUQABTDMBZCN-UHFFFAOYSA-N [Sb].[As].[In] Chemical compound [Sb].[As].[In] XSKUQABTDMBZCN-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- BOIGHUSRADNYQR-UHFFFAOYSA-N aluminum;lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Al+3].[La+3] BOIGHUSRADNYQR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- RGZQGGVFIISIHZ-UHFFFAOYSA-N strontium titanium Chemical compound [Ti].[Sr] RGZQGGVFIISIHZ-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- -1 yittrium oxide Chemical compound 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of semiconductor structure, including：Substrate is provided；The first semiconductor layer and the second semiconductor layer are formed on substrate；Gate dielectric layer is formed on the second semiconductor layer；Pseudo- gate layer is formed on gate dielectric layer；First grid lamination is formed on gate dielectric layer surface；Remove pseudo- gate layer；Second grid lamination is formed on the gate dielectric layer surface exposed, the work function of second grid lamination is less than the work function of first grid lamination.Because the work function of first grid lamination is larger, it is possible to increase suspension area and the tunnelling starting voltage into interface intersection；The work function of second grid lamination is smaller, the tunnelling starting voltage away from suspension area can be reduced, so technical solution of the present invention can effectively reduce the variable gradient from the tunnelling starting voltage into interface to suspension area direction, so as to effectively improve the uniformity coefficient of tunnelling current distribution, and then improve the subthreshold swing performance for forming tunneling transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of forming method of semiconductor structure.
Background technology
As integrated circuit is to super large-scale integration development, the current densities of IC interior are increasing, institute
Comprising component number it is also more and more, the size of component also reduces therewith.With the reduction of semiconductor structure size, half
The raceway groove of device shortens therewith in conductor structure.Due to channel shortening, gradual channel approximation is no longer set up, and highlight it is various not
The physical effect of profit, this causes device performance and reliability to degenerate, and limits the further diminution of device size.
As the progress of device fabrication, the diminution of device size, the operating voltage of semiconductor devices are more and more lower.Pass
The subthreshold swing of system MOS structure device cannot be below 60mV/dec.The minimum of subthreshold swing limits traditional cmos device
The minimum operating voltage of part.
In order to further reduce the minimum operating voltage of cmos device, prior art has developed various new device to break through
The limitation of subthreshold swing, one of which are exactly tunneling transistor (Tunneling FET, TFET).Tunneling transistor is to be based on
Quantum tunneling effect, the transistor arrangement using tunnel(l)ing current as main current component.In the range of certain voltage, tunnelling is brilliant
The subthreshold value of body pipe can have the characteristics that speed is fast, operating efficiency is high with as little as 15mV/dec.
But tunneling transistor often has the problem of tunnelling current skewness in the prior art, tunnelling crystal have impact on
The performance of pipe.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor structure, with raising formation tunneling transistor
Performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided；Formed over the substrate the first semiconductor layer and on first semiconductor layer the second half
Conductor layer, the area of second semiconductor layer are more than the area of first semiconductor layer, and second semiconductor layer includes
Be in contact with first semiconductor layer into interface, and with it is described adjacent into interface and be not in contact with the first semiconductor layer
Suspension area；Form gate dielectric layer on second semiconductor layer, the gate dielectric layer covering it is described into interface and with institute
State into the connected part suspension area in interface；Form pseudo- gate layer on the gate dielectric layer, the pseudo- gate layer is led described the second half
Projection on body layer is positioned at described into interface；Folded not forming first grid by the gate dielectric layer surface of the pseudo- gate layer covering
Layer；The pseudo- gate layer is removed, exposes the gate dielectric layer surface；Second grid is formed on the gate dielectric layer surface exposed to fold
Layer, the work function of the second grid lamination are less than the work function of the first grid lamination.
Optionally, in the step of forming the first grid lamination, the work function of the first grid lamination is more than
4.6eV；In the step of forming the second grid lamination, the work function of the second grid lamination is less than 4.4eV.
Optionally, in the step of forming the first grid lamination, the first grid lamination includes the first cap；Shape
The step of second grid lamination in, the second grid lamination includes the second cap, the work(of second cap
Function is less than the work function of first cap.
Optionally, the material of first cap includes：Tungsten, molybdenum, platinum, rhenium or iridium.
Optionally, the material of second cap includes：Titanium nitride, nitrogen titanium silicide, tantalum nitride, nitrogen tantalum silicide, silication
Nickel, tungsten silicide, molybdenum nitride or cobalt silicide.
Optionally, in the step of forming the second grid lamination, described in the second grid lamination also covering part
One gate stack.
Optionally, formed after the first grid lamination, before removing the pseudo- gate layer, in the first grid lamination
Part surface away from described pseudo- gate layer one end forms hard mask layer, and the hard mask layer is in second semiconductor layer surface
Projection is in the suspension area；The step of forming the second grid lamination includes：Formed and cover the gate dielectric layer, described
The second grid material layer of first grid lamination and the hard mask layer；Return and carve the second grid material layer, described in formation
Second grid lamination, the top surface of the second grid lamination flush with the hard mask layer.
Optionally, returning the step of carving the second grid material layer includes：Returned by the way of dry etching and carve described the
Two gate material layers.
Optionally, included using the step of by the way of dry etching times quarter second grid material layer：Using gas group
The mode of ion beam etching carries out the dry etching；Or carried out by the way of the adjustable etching in wafer temperature region described
Dry etching.
Optionally, returning the step of carving the second grid material layer includes：Described return is controlled by the way of end point determination
Carving technology makes the top surface of the second grid lamination be flushed with the hard mask layer.
Optionally, formed after the second grid lamination, the forming method also includes：Remove the hard mask layer.
Optionally, the step of removing the hard mask layer includes：The hard mask layer is removed by the way of wet etching.
Optionally, after the first grid lamination is formed, before hard mask layer is formed, the forming method is also wrapped
Include：Planarization process is carried out to the first grid lamination, the first grid lamination is flushed with the pseudo- gate layer.
Optionally, the step of carrying out planarization process to the first grid lamination includes：Using cmp
Mode carries out the planarization process.
Optionally, the step of forming first semiconductor layer and second semiconductor layer over the substrate includes：
The second the half of the first semiconductor material layer for being formed on the substrate and covering the first semi-conducting material layer surface
Conductor layer；Remove part first semiconductor material layer and form the first semiconductor layer, so that part second semiconductor layer
Vacantly, the area of second semiconductor layer is more than the area of first semiconductor layer, connects with first semiconductor layer
The second tactile semiconductor layer is into interface, is suspension area with described adjacent into interface and hanging second semiconductor layer.
Optionally, the step of forming the first semiconductor layer includes：Part described first is removed by the way of laterally etched
Semiconductor material layer forms the first semiconductor layer.
Optionally, in the step of forming gate dielectric layer, the material of the gate dielectric layer includes high K dielectric material.
Optionally, in the step of forming gate dielectric layer, the material of the gate dielectric layer includes zirconium oxide.
Optionally, in the step of forming first semiconductor layer and second semiconductor layer, first semiconductor
The material of layer includes：Gallium antimony；The material of second semiconductor layer includes：Indium arsenic.
Compared with prior art, technical scheme has advantages below：
In technical solution of the present invention, gate dielectric layer covering it is described into interface and with the part being connected into interface
Suspension area, and projection of the pseudo- gate layer on second semiconductor layer positioned at it is described into interface (i.e. pseudo- gate layer positioned at into
Interface corresponding position, and do not cover into the boundary of interface and suspension area)；Therefore, it is situated between in the grid not by the pseudo- gate layer covering
When matter layer surface forms first grid lamination, the first grid lamination is located at friendship of second semiconductor layer into interface and suspension area
Top at boundary, in addition, second grid lamination is formed at second semiconductor layer into above interface in this programme, and described the
The work function of two gate stacks is less than the work function of the first grid lamination.Due to the first grid lamination work function compared with
Greatly, it is possible to increase the suspension area and the tunnelling starting voltage into interface intersection；The work function of the second grid lamination compared with
It is small, the tunnelling starting voltage away from the suspension area can be reduced, so technical solution of the present invention can be effectively reduced from into knot
Area to tunnelling starting voltage on the direction of suspension area variable gradient, so as to effectively improve tunnelling current distribution uniform journey
Degree, and then improve the subthreshold swing performance for forming tunneling transistor.
Brief description of the drawings
Fig. 1 is a kind of cross-sectional view of semiconductor structure；
Fig. 2 to Fig. 8 is that cross-section structure corresponding to each step of the embodiment of method for forming semiconductor structure one of the present invention is illustrated
Figure.
Embodiment
From background technology, there is tunnelling current skewness and influence performance in tunneling transistor of the prior art
Problem.In conjunction with a kind of semiconductor structure profile shown in Fig. 1, analysator semiconductor structure analyzes the distribution of its tunnelling current not
The reason for equal problem：As shown in figure 1, the semiconductor structure includes：
Substrate (not shown)；Source region semiconductor layer 11 on the substrate；Positioned at the leakage of the area surface
Area's semiconductor layer 12, described one end of drain region semiconductor layer 12 flush with the source region semiconductor layer 11, and the other end exceeds the source
Area's semiconductor layer 11, so the drain region semiconductor layer 12 with the source region semiconductor layer 11 including being in contact into interface 12j
And with the suspension area 12c adjacent into interface 12j；Cover the gate dielectric layer of the part surface of drain region semiconductor layer 12
13, the gate dielectric layer 13 is positioned at described on interface 12j and the part suspension area 12c；Cover the table of gate dielectric layer 13
The grid 14 in face.
In tunneling transistor, the material of source region semiconductor layer 11 is usually gallium antimony, and the material of drain region semiconductor layer 12 is usual
For indium arsenic.Because drain region semiconductor layer 12 only contacts into interface 12j with the source region semiconductor layer 11, and suspension area 12c is in
Vacant state, therefore many energy be present and be higher than conduction band bottom in the suspension area 12c surface of drain region semiconductor layer 12
The surface state of (Conduction Band Minimum, CBM).
Fermi level (Fermi level) pinning of the drain region semiconductor layer 12 is in the surface state, so described
Electronics gatherable layer be present in the surface of drain region semiconductor layer 12.The formation of the surface electronic gatherable layer of drain region semiconductor layer 12, meeting
Tunnelling current is set to concentrate on drain region semiconductor layer 12 into interface 12j and suspension area 12c intersection, so that the tunnelling crystal
Pipe tunnelling current skewness, and then make under subthreshold swing (Subthreshold Swing) performance of the tunneling transistor
Drop.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided；Formed over the substrate the first semiconductor layer and on first semiconductor layer the second half
Conductor layer, the area of second semiconductor layer are more than the area of first semiconductor layer, including with first semiconductor
Layer be in contact into interface, and with suspension area that is described adjacent into interface and not being in contact with the first semiconductor layer；Described
Form gate dielectric layer on second semiconductor layer, the gate dielectric layer covering it is described into interface and with the portion being connected into interface
Divide suspension area；Pseudo- gate layer is formed on the gate dielectric layer, projection of the pseudo- gate layer on second semiconductor layer is located at
It is described into interface；First grid lamination is formed on the gate dielectric layer surface not by the pseudo- gate layer covering；Remove the pseudo- grid
Layer, exposes the gate dielectric layer surface；Second grid lamination, the second grid are formed on the gate dielectric layer surface exposed
The work function of lamination is less than the work function of the first grid lamination.
In technical solution of the present invention, gate dielectric layer covering it is described into interface and with the part being connected into interface
Suspension area, and projection of the pseudo- gate layer on second semiconductor layer positioned at it is described into interface (i.e. pseudo- gate layer positioned at into
Interface corresponding position, and do not cover into the boundary of interface and suspension area)；Therefore, it is situated between in the grid not by the pseudo- gate layer covering
When matter layer surface forms first grid lamination, the first grid lamination is located at friendship of second semiconductor layer into interface and suspension area
Top at boundary, in addition, second grid lamination is formed at second semiconductor layer into above interface in this programme, and described the
The work function of two gate stacks is less than the work function of the first grid lamination.Due to the first grid lamination work function compared with
Greatly, it is possible to increase the suspension area and the tunnelling starting voltage into interface intersection；The work function of the second grid lamination compared with
It is small, the tunnelling starting voltage away from the suspension area can be reduced, so technical solution of the present invention can be effectively reduced from into knot
Area to tunnelling starting voltage on the direction of suspension area variable gradient, so as to effectively improve tunnelling current distribution uniform journey
Degree, and then improve the subthreshold swing performance for forming tunneling transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Referring to figs. 2 to Fig. 8, section corresponding to each step of the embodiment of method for forming semiconductor structure one of the present invention is shown
Structural representation.
In the present embodiment, illustrated exemplified by forming tunneling transistor, still, technical solution of the present invention can be also used for
Form other semiconductor structures.
With reference to figure 2, there is provided substrate (not shown).
The substrate is the operating platform of semiconductor technology.Specifically, in the present embodiment, the material of the substrate is monocrystalline
Silicon.But the material of the substrate can also be polysilicon or non-crystalline silicon.In addition, the substrate can also be selected from germanium, arsenic
Other semi-conducting materials such as gallium or germanium silicon.In other embodiments of the invention, the substrate can also be with semiconductor structure
Deng substrate.Specifically, the substrate can also be with the silicon structure on epitaxial layer or epitaxial layer.
With continued reference to Fig. 2, the first semiconductor layer 101 is formed over the substrate and positioned at first semiconductor layer 101
On the second semiconductor layer 102, the area of second semiconductor layer 102 is more than the area of first semiconductor layer 101, bag
Include be in contact with first semiconductor layer 101 into interface 102j, and with it is described adjacent into interface 102j and with the first half
The suspension area 102c that conductor layer 101 is not in contact.
First semiconductor layer 101 is used to being formed the source region of transistor in the semiconductor structure, and described the second half lead
Body layer 102 is used for the drain region for forming transistor in the semiconductor structure.In the present embodiment, the transistor formed is brilliant for tunnelling
Body pipe, the area material are gallium antimony, and the material in the drain region is indium arsenic, so first semiconductor layer 101 is gallium antimony layer,
And the thickness T of the gallium antimony layerGaSbFor in 90 nanometers to 110 nanometer ranges, the material of second semiconductor layer 102 is indium
Arsenic layer, and the thickness T of the indium arsenic layerInAsFor in 4 nanometers to 6 nanometer ranges.
It should be noted that because first semiconductor layer 101 and second semiconductor layer 102 are used to form crystal
The source region of pipe or drain region.So the material of first semiconductor layer 101 is p-type doped semiconductor materials, P in the gallium antimony layer
The doping concentration of type ion is 9 × 1018atom/cm3To 1.1 × 1019atom/cm3In the range of；Second semiconductor layer 102
Material be n-type doping semi-conducting material, the doping concentration of N-type ion is 1.1 × 10 in the indium arsenic layer16To 1.1 ×
1017atom/cm3In the range of.
In addition, in other embodiments of the present invention, the material of first semiconductor layer 101 is also selected from germanium, SiGe
Or other semi-conducting materials such as germanium tin；The material of second semiconductor layer 102 is also selected from indium arsenic antimony or indium gallium arsenic etc. half
Conductor material.
The step of forming first semiconductor layer 101 and the second semiconductor layer 102 over the substrate includes：
First, the first semiconductor material layer and covering first semiconductor material layer formed on the substrate
Second semiconductor layer 102 on surface.
Specifically, the present embodiment passes through the film depositions such as chemical vapor deposition, physical vapour deposition (PVD) or ald
Mode form first semiconductor material layer and second semiconductor layer 102.But this side using film deposition
It is only an example that formula, which forms first semiconductor material layer and the way of second semiconductor layer 102,.The present invention other
In embodiment, the material of the substrate is gallium antimony, direct over the substrate afterwards using the substrate as the first semiconductor layer
Second semiconductor layer is formed to form the source region of the tunneling transistor or drain region.
Afterwards, remove part first semiconductor material layer and form the first semiconductor layer 101, so that part described second
Semiconductor layer 102 is hanging, and the area of second semiconductor layer 102 is more than the area of first semiconductor layer 101, and described
The second semiconductor layer 102 that first semiconductor layer 101 is in contact be into interface 102j, it is and described adjacent and hanging into interface 102j
Second semiconductor layer 102 be suspension area 102c.
In the present embodiment, by removing part first semiconductor material layer, make part second semiconductor layer 102
Vacantly, so as to forming less first semiconductor layer 101 of area.Specifically, second semiconductor layer 102 into interface 102j
Contacted with each other with the surface of the first semiconductor layer 101, form PN junction；The semiconductor layer 102 of the suspension area 102c is in hanging.
In the present embodiment, part first semiconductor material layer is removed by laterally etched mode, forms the first half
Conductor layer 101.Specifically, along into interface 102j to suspension area 102c direction, first semiconductor material layer is removed
Size LucIn 63 nanometers to 77 nanometer ranges；Form the size L of the first semiconductor layer 101jIn 45 nanometers to 55 nanometers models
In enclosing.So it is along into interface 102j to suspension area 102c direction, the size into the second semiconductor layers of interface 102j 102
45 nanometers in 55 nanometer ranges；The size of second semiconductor layers of suspension area 102c 102 is at 63 nanometers to 77 nanometer ranges
It is interior.
It should be noted that in the present embodiment, the remote side having a common boundary into the interface 102j and suspension area 102c,
Second semiconductor layer 102 flushes with first semiconductor layer 101.
With continued reference to Fig. 2, gate dielectric layer 103 is formed on second semiconductor layer 102, the gate dielectric layer 103 covers
Cover it is described into interface 102j and with the part suspension area 102c being connected into interface 102j.
Specifically, the semiconductor structure has high-K metal gate structure.So the gate dielectric layer 103 is high K dielectric
Material.The present embodiment, the material silica zirconium (ZrO of the gate dielectric layer 1032), chemical vapor deposition, physics gas can be passed through
The methods of phase deposition or ald, is formed.In the present embodiment, the thickness T of the gate dielectric layer 103ZrO2Arrived at 9 nanometers
In 11 nanometer ranges.
In other embodiments of the present invention, the material of the gate dielectric layer 103 is also selected from hafnium oxide, lanthana, oxygen
Change aluminium, titanium oxide, strontium titanates, aluminum oxide lanthanum, yittrium oxide, nitrogen oxidation hafnium, nitrogen oxidation zirconium, nitrogen oxidation lanthanum, titanium oxynitrides, nitrogen oxidation
One or more in strontium titanium, nitrogen oxidation lanthanum aluminium, yttrium oxynitride.
The gate dielectric layer 103 cover it is described into interface 102j and it is described into interface 102j be connected part suspension area
102c.The area of the gate dielectric layer 103 is more than the area of first semiconductor layer 101 and is less than second semiconductor layer
102 area.
It should be noted that away from the side having a common boundary into the interface 102j and suspension area 102c, the gate medium
Layer 103 is flush with second semiconductor layer 102 and first semiconductor layer 101；Along into interface 102j to suspension area
102c direction, the size L of the gate dielectric layer 103mMore than the size L of first semiconductor layer 1101jAnd less than described the
The size of two semiconductor layers 102.Specifically, the size L of the gate dielectric layer 103mIn 63 nanometers to 77 nanometer ranges.
With continued reference to Fig. 2, pseudo- gate layer 120a is formed on the gate dielectric layer 103, the pseudo- gate layer 102a is described
Projection on two semiconductor layers 102 is positioned at described into the 102j of interface.
The pseudo- gate layer 120a is used to define follow-up position and the chi for forming first grid lamination and second grid lamination
It is very little.Specifically, the material of the pseudo- gate layer 120a is polysilicon.Because the semiconductor structure is with high-K metal gate knot
The semiconductor structure of structure, therefore extended meeting is removed after the pseudo- gate layer 120a, to form metal gates.
Due to projections of the pseudo- gate layer 120a on second semiconductor layer 102 positioned at described into the 102j of interface,
So the area of the pseudo- gate layer 120a is less than the area into interface 102j of second semiconductor layer 102.
It should be noted that in the present embodiment, the remote side having a common boundary with the suspension area 102c is described into interface 102j
The second semiconductor layer 102 flushed with the pseudo- gate layer 120a.In addition, flushing side along backwards to described, the pseudo- gate layer is formed
After 120a, the size of the remaining gate dielectric layer 103 is in 27 nanometers to 33 nanometer ranges.
The step of forming the pseudo- gate layer 120a includes：Pseudo- gate material layer is formed on the surface of gate dielectric layer 103；Institute
State pseudo- gate material layer surface and form the first patterned layer；Using first patterned layer as mask, the pseudo- gate material layer is etched
Until exposing the surface of gate dielectric layer 103, the pseudo- gate layer 120a is formed.
First patterned layer is used for size and the position for defining the pseudo- gate layer 120a.In the present embodiment, described
One patterned layer is photoresist layer, and the gate dielectric layer 103 can be formed at by photoresist coating process and photoetching process
Surface.
But the way for forming first patterned layer of photoresist layer is only an example.Other embodiments of the invention
In, in order to reduce formed pseudo- gate layer 120a size, so as to reduce the size of follow-up institute's formation second grid lamination, described
One patterned layer can also be formed using multiple graphical masking process.The multiple graphical masking process includes：Autoregistration
Dual graphing (Self-aligned Double Patterned, SaDP) technique, the triple graphical (Self- of autoregistration
Aligned Triple Patterned) graphical (the Self-aligned Double Double of technique or autoregistration quadruple
Patterned, SaDDP) technique.
With reference to figure 3, first grid lamination 110 is formed on the surface of gate dielectric layer 103 not by the pseudo- gate layer 120a coverings.
Due to projections of the pseudo- gate layer 120a on second semiconductor layer 102 positioned at described into the 102j of interface,
So projection of the first grid lamination 110 formed on second semiconductor layer 102 cover the suspension area 102c with
And with the part that the suspension area 102c is connected into interface.So the first grid lamination 110 is used to control described the second half
Raceway groove of the conductor layer 102 into interface 102j and the suspension area 102c intersections, that is to say, that the first grid lamination 110
For controlling second semiconductor layer into the raceway groove at interface 102j edges.
It should be noted that in the present embodiment, along side is flushed backwards, formed after the pseudo- gate layer 120a, it is remaining
The size of the gate dielectric layer 103 is in 27 nanometers to 33 nanometer ranges, so the size L of the first grid lamination 110m1
27 nanometers in 33 nanometer ranges.
In order to effectively improve the tunnelling starting voltage of trench edges (Tunneling Onset Voltage), described first
Gate stack 110 has larger work function.Specifically, the work function of the first grid lamination 110 is more than 4.6eV.
Specifically, the first grid lamination 110 includes the first cap.First cap is used to adjust described the
The work function of one gate stack 110, so the material of first cap includes tungsten, molybdenum, platinum, rhenium or iridium.In the present embodiment,
The material of first cap is tungsten.
It should be noted that in the present embodiment, the second grid lamination subsequently formed is also covered in part described first
On gate stack 110.So with reference to figure 4, it is remote in the first grid lamination 110 after the gate stack 110 is formed
Part surface from described pseudo- gate layer 120a one end forms hard mask layer 120b, the hard mask layer 120b and led described the second half
The projection on the surface of body layer 102 is located in the suspension area 102c.
It should be noted that being formed after the first grid lamination 110, formed before the hard mask 120b, it is described
Forming method also includes：Planarization process is carried out to the first grid lamination 110, so that the He of first grid lamination 110
The pseudo- gate layer 120a top surfaces flush, so as to provide smooth operating platform for follow-up semiconductor technology.Specifically, this
Embodiment carries out the planarization process by the way of cmp.
The hard mask layer 120b is used for size and the position for defining follow-up institute's formation second grid lamination.Further, since
The hard mask layer 120b is located at part surface of the first grid lamination 110 away from described pseudo- gate layer 120a one end, and
Projections of the hard mask layer 120b on the surface of the second semiconductor layer 102 is located in the suspension area 102c, so subsequently
First grid lamination 110 described in the second grid lamination also covering part formed.
Specifically, the material of the hard mask layer 120b is nitride, such as silicon nitride, silicon oxynitride or carbonitride of silicium
Deng.Size and the position of the second grid lamination are defined using the hard mask layer 120b of nitride material, can effectively be reduced
Error is etched, obtains and designs closer figure with former.
The step of forming the hard mask layer 120b includes：On the pseudo- gate layer 120a and the surface of first grid lamination 110
Form hardmask material；Second graphical layer is formed to the hard mask material layer surface, the second graphical layer is used for
Define the positions and dimensions of the hard mask layer 120b；Using the second graphical layer as mask, the hard mask material is etched
Layer forms hard mask layer 120b.
Specifically, the hardmask material 120b can pass through chemical vapor deposition, physical vapour deposition (PVD) or atomic layer
The mode of deposition is formed；The second graphical layer is photoresist layer, can be formed by coating process and photoetching process；Etching
The step of hardmask material, can be carried out by way of mask dry etching.
It should be noted that in other embodiments of the present invention, the second graphical layer can also pass through multigraph
The patterned layer that shape masking process is formed.The way of the patterned layer is formed using multiple graphical masking process, can
The size for forming hard mask layer is reduced, improves the craft precision for forming hard mask layer.
With reference to figure 5, the pseudo- gate layer 120a (as shown in Figure 4) is removed, exposes the surface of gate dielectric layer 103.
In the present embodiment, the material of the pseudo- gate layer 120a is polysilicon.Therefore the step of removing the pseudo- gate layer 120a
Including：The pseudo- gate layer 120a is removed by way of wet etching or dry etching, exposes the pseudo- gate layer 120a coverings
Part gate dielectric layer 103.
With reference to figure 6 and Fig. 7, second grid lamination 120 is formed on the surface of the gate dielectric layer 103 exposed, described second
The work function of gate stack 120 is less than the work function of the first grid lamination 110.
Due to projections of the pseudo- gate layer 120a on second semiconductor layer 102 positioned at described into the 102j of interface,
Therefore the projection of the second grid lamination 120 that is formed on second semiconductor layer 102 positioned at described into the 102j of interface,
So the second grid lamination 120 is used to control the raceway groove away from the suspension area 102c.
In order to effectively reduce the tunnelling starting voltage of trench edges (Tunneling Onset Voltage), described second
Gate stack 120 has less work function.Specifically, the work function of the second grid lamination 120 is less than 4.4eV.
Because the first grid lamination 110 is located at friendship of second semiconductor layer 102 into interface 102j and suspension area 102c
Top at boundary, the second grid lamination 120 are formed at second semiconductor layer 102 into interface 102j tops；It is and described
The work function of first grid lamination 110 is larger, it is possible to increase the suspension area 102c and the tunnelling into interface 102j intersections rise
Beginning voltage；The work function of the second grid lamination 120 is smaller, can reduce the tunnelling starting electricity away from the suspension area 102j
Pressure.So technical solution of the present invention can be effectively reduced from the tunnelling starting voltage into interface 102j to suspension area 102c directions
Variable gradient, so as to effectively improve the uniformity coefficient of tunnelling current distribution, and then improve the Asia for forming tunneling transistor
Threshold value amplitude of oscillation performance.
Specifically, the second grid lamination 120 includes the second cap.Second cap is used to adjust described the
The work function of two gate stacks 120, so the work function of second cap is less than the work function of first cap.Tool
Body, the material of second cap includes：Titanium nitride, nitrogen titanium silicide, tantalum nitride, nitrogen tantalum silicide, nickle silicide, tungsten silicide,
Molybdenum nitride or cobalt silicide.In the present embodiment, the material of second cap is titanium nitride.
It should be noted that in the present embodiment, the second grid lamination 120 also first grid lamination described in covering part
110, further to reduce the variable gradient from the tunnelling starting voltage into interface 102j to suspension area 102c directions, so as to improve
The uniformity coefficient of tunnelling current distribution, and then improve the subthreshold swing of the tunneling transistor.Specifically, in the present embodiment,
From into interface 102j to suspension area 102c direction, the size L of the second grid lamination 120m2At 34 nanometers to 42 nanometers
In the range of.
Specifically, the step of forming second grid lamination 120 includes：
With reference to figure 6, formed and cover gate dielectric layer 103, the first grid lamination 110 and the hard mask layer
120b second grid material layer 120c.
The second grid material layer 120c is used to form the second grid lamination 120.Specifically, chemistry can be passed through
The mode of vapour deposition, physical vapour deposition (PVD) or ald forms the second grid material layer 120c.
In order to improve the filling extent of the second grid material layer 120c, in the present embodiment, the second grid material
Layer 120c also covers the mask layer 120b.
With reference to figure 7, return and carve the second grid material layer 120c (as shown in Figure 6), form the second grid lamination
120, the top surface of the second grid lamination 120 flushes with the hard mask layer 120b.
Return and carve the second grid material layer 120c, remove the segment thickness of the second grid material layer 120c, make institute
The top surface for stating second grid material layer 120c flushes with the top surface of the hard mask layer 120b.
The second grid material layer 120c is carved specifically, being returned by way of dry etching.In the present embodiment, using gas
The mode of body cluster ions beam (Gas Cluster Ion Beams, GCIB) etching carries out the dry etching.Using gas group
The way etching precision that ion beam etching mode performs etching is larger, can cross and effectively improve the removal second grid material layer
The precision of 120c thickness, so as to improve the control to being covered in the thickness of second grid lamination 120 on the first grid lamination 110
Precision.
It should be noted that in order to improve the control accuracy of etching technics, in the present embodiment, the second grid is carved returning
In the step of material layer, the etching technics is controlled by the way of end point determination (endpoint), that is to say, that using terminal
The mode of detection controls the thickness for being covered in the first grid stack surface second grid lamination.
In other embodiments of the present invention, using by the way of dry etching return carve the second grid material layer the step of
In, in addition to carry out the dry etching by the way of the adjustable etching (Hydra-based) of wafer temperature.Using wafer temperature
Spend adjustable etching mode carry out the dry etching during, whole wafer is divided into individual region more than 60, each region
Wafer can independently adjust temperature, therefore the uniformity coefficient of the adjustable etching of wafer temperature is higher, be advantageous to improve back and carve described the
The etching precision of two gate material layers, improve the performance for forming semiconductor structure.
It should be noted that with reference to figure 8, in the present embodiment, after the second grid lamination 120 is formed, the shape
Also include into method：Remove the hard mask layer 120b.
Specifically, the present embodiment removes the hard mask layer 120b (as shown in Figure 7) by the way of wet etching.Using
Wet etching removes the way of the hard mask layer 120b, can reduce the technique for removing the hard mask layer 120b to semiconductor
The influence of structure, so as to improve the performance of formed semiconductor devices.
To sum up, in technical solution of the present invention, the gate dielectric layer covering is described to be connected into interface and with described into interface
Part suspension area, and projection of the pseudo- gate layer on second semiconductor layer is positioned at described into (i.e. pseudo- gate layer in interface
Positioned at into interface corresponding position, and the boundary of interface and suspension area is not covered into)；Therefore, do not covered by the pseudo- gate layer
Gate dielectric layer surface formed first grid lamination when, the first grid lamination be located at the second semiconductor layer into interface and vacantly
Above the intersection in area, in addition, second grid lamination is formed at second semiconductor layer into interface top in this programme, and
The work function of the second grid lamination is less than the work function of the first grid lamination.Due to the work(of the first grid lamination
Function is larger, it is possible to increase the suspension area and the tunnelling starting voltage into interface intersection；The work(of the second grid lamination
Function is smaller, the tunnelling starting voltage away from the suspension area can be reduced, so technical solution of the present invention can effectively reduce
From the variable gradient of the tunnelling starting voltage into interface to suspension area direction, so as to effectively improve the equal of tunnelling current distribution
Even degree, and then improve the subthreshold swing performance for forming tunneling transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (19)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is provided；Form the first semiconductor layer and the second semiconductor layer on first semiconductor layer over the substrate, described The area of two semiconductor layers is more than the area of first semiconductor layer, and second semiconductor layer includes leading with described the first half Body layer be in contact into interface, and with suspension area that is described adjacent into interface and not being in contact with the first semiconductor layer；Form gate dielectric layer on second semiconductor layer, the gate dielectric layer covering it is described into interface and with described into knot The connected part suspension area in area；Form pseudo- gate layer on the gate dielectric layer, projection of the pseudo- gate layer on second semiconductor layer positioned at it is described into In interface；First grid lamination is formed on the gate dielectric layer surface not by the pseudo- gate layer covering；The pseudo- gate layer is removed, exposes the gate dielectric layer surface；Second grid lamination is formed on the gate dielectric layer surface exposed, the work function of the second grid lamination is less than described The work function of first grid lamination.
- 2. forming method as claimed in claim 1, it is characterised in that described in the step of forming the first grid lamination The work function of first grid lamination is more than 4.6eV；In the step of forming the second grid lamination, the work function of the second grid lamination is less than 4.4eV.
- 3. forming method as claimed in claim 1, it is characterised in that described in the step of forming the first grid lamination First grid lamination includes the first cap；In the step of forming the second grid lamination, the second grid lamination includes the second cap, second block The work function of layer is less than the work function of first cap.
- 4. forming method as claimed in claim 3, it is characterised in that the material of first cap includes：Tungsten, molybdenum, platinum, rhenium or iridium.
- 5. forming method as claimed in claim 3, it is characterised in that the material of second cap includes：Titanium nitride, nitrogen titanium silicide, tantalum nitride, nitrogen tantalum silicide, nickle silicide, tungsten silicide, molybdenum nitride or cobalt silicide.
- 6. forming method as claimed in claim 1, it is characterised in that described in the step of forming the second grid lamination First grid lamination described in second grid lamination also covering part.
- 7. forming method as claimed in claim 6, it is characterised in that formed after the first grid lamination,Before removing the pseudo- gate layer, formed in part surface of the first grid lamination away from described pseudo- gate layer one end and covered firmly Film layer, the hard mask layer are located in the suspension area in the projection of second semiconductor layer surface；The step of forming the second grid lamination includes：Form the second grid material layer for covering the gate dielectric layer, the first grid lamination and the hard mask layer；Return and carve the second grid material layer, form the second grid lamination, the top surface of the second grid lamination with The hard mask layer flushes.
- 8. forming method as claimed in claim 7, it is characterised in that returning the step of carving the second grid material layer includes： Returned by the way of dry etching and carve the second grid material layer.
- 9. forming method as claimed in claim 8, it is characterised in that returned by the way of dry etching and carve the second grid The step of material layer, includes：The dry etching is carried out by the way of gas cluster ion beam etching；Or use wafer temperature The mode of the degree adjustable etching in region carries out the dry etching.
- 10. forming method as claimed in claim 7, it is characterised in that returning the step of carving the second grid material layer includes： The carving technology that returns is controlled to make the top surface of the second grid lamination and the hard mask layer by the way of end point determination Flush.
- 11. forming method as claimed in claim 7, it is characterised in that formed after the second grid lamination,The forming method also includes：Remove the hard mask layer.
- 12. forming method as claimed in claim 11, it is characterised in that the step of removing the hard mask layer includes：Using The mode of wet etching removes the hard mask layer.
- 13. forming method as claimed in claim 7, it is characterised in that after the first grid lamination is formed, formed Before hard mask layer, the forming method also includes：Planarization process is carried out to the first grid lamination, makes the first grid Pole lamination flushes with the pseudo- gate layer.
- 14. forming method as claimed in claim 13, it is characterised in that planarization process is carried out to the first grid lamination The step of include：The planarization process is carried out by the way of cmp.
- 15. forming method as claimed in claim 1, it is characterised in that form first semiconductor layer over the substrate Include with the step of second semiconductor layer：The of the first semiconductor material layer for being formed on the substrate and covering the first semi-conducting material layer surface Two semiconductor layers；Remove part first semiconductor material layer and form the first semiconductor layer, so that part second semiconductor layer hangs Sky, the area of second semiconductor layer are more than the area of first semiconductor layer, are in contact with first semiconductor layer The second semiconductor layer be into interface, be suspension area with described adjacent into interface and hanging second semiconductor layer.
- 16. forming method as claimed in claim 15, it is characterised in that the step of forming the first semiconductor layer includes：Using Laterally etched mode removes part first semiconductor material layer and forms the first semiconductor layer.
- 17. forming method as claimed in claim 1, it is characterised in that in the step of forming gate dielectric layer, the gate dielectric layer Material include high K dielectric material.
- 18. forming method as claimed in claim 17, it is characterised in that in the step of forming gate dielectric layer, the gate medium The material of layer includes zirconium oxide.
- 19. forming method as claimed in claim 1, it is characterised in that form first semiconductor layer and described the second half In the step of conductor layer, the material of first semiconductor layer includes：Gallium antimony；The material of second semiconductor layer includes：Indium Arsenic.
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| US20150014630A1 (en) * | 2013-07-15 | 2015-01-15 | Sungkyunkwan University Foundation For Corporate Collaboration | Tunneling devices and methods of manufacturing the same |
| CN105405875A (en) * | 2015-11-18 | 2016-03-16 | 湘潭大学 | Low off-state current tunneling field effect transistor |
| CN105702721A (en) * | 2016-04-20 | 2016-06-22 | 杭州电子科技大学 | Novel asymmetric double-gate tunnelling field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20150014630A1 (en) * | 2013-07-15 | 2015-01-15 | Sungkyunkwan University Foundation For Corporate Collaboration | Tunneling devices and methods of manufacturing the same |
| CN105405875A (en) * | 2015-11-18 | 2016-03-16 | 湘潭大学 | Low off-state current tunneling field effect transistor |
| CN105702721A (en) * | 2016-04-20 | 2016-06-22 | 杭州电子科技大学 | Novel asymmetric double-gate tunnelling field effect transistor |
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