CN107704489B - Processing method and device for read-write timeout and computer readable storage medium - Google Patents
Processing method and device for read-write timeout and computer readable storage medium Download PDFInfo
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- CN107704489B CN107704489B CN201710720127.4A CN201710720127A CN107704489B CN 107704489 B CN107704489 B CN 107704489B CN 201710720127 A CN201710720127 A CN 201710720127A CN 107704489 B CN107704489 B CN 107704489B
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Abstract
The disclosure relates to a processing method and device for read-write timeout and a computer readable storage medium. The method comprises the following steps: the method comprises the steps of obtaining all read-write operations occurring in a preset time period, determining whether the read-write operations are all completed when the preset time is away from the end time in the preset time period, and when at least one read-write operation in the read-write operations is not completed, setting the read-write operation in the preset time period to be overtime by a first timer and resetting a second timer. According to the technical scheme, the operation that each previous read-write operation needs to be set for one time overtime is optimized to the state that the timer is reset only once within a certain time period. Because under the condition of large data volume, the read-write timeout is not required to be set for each communication, the performance loss caused by the setting timeout can be greatly reduced by stripping the timer logic, and the effect of performance optimization is achieved.
Description
Technical Field
The present disclosure relates to the field of internet technologies, and in particular, to a method and an apparatus for processing read-write timeout, and a computer-readable storage medium.
Background
At present, with the development of network technology, the internet is used as a huge information resource and becomes the most convenient and fast way for people to acquire information. Currently, a user generally accesses a network using a personal computer and accesses a web page through a Browser (Browser) installed in the personal computer to obtain desired information.
In the related art, a socket service is often used to establish a connection between a server and a client, so-called socket is a communication way between the client and the server in a network, when the server and the client are to establish a connection and perform data transmission, the server and the client (target client) that needs to establish a connection need to be docked, and the socket can be regarded as a "docking number" of the docking, and only if the "docking number" of the server and the target client is the same, the server and the target client can be connected to transmit data. And the socket service is the docking service provided for the server and the client.
Disclosure of Invention
In order to overcome the problems in the related art, embodiments of the present disclosure provide a method and an apparatus for processing read-write timeout, and a computer-readable storage medium. The technical scheme is as follows:
according to a first aspect of the embodiments of the present disclosure, a method for processing read-write timeout is provided, including:
acquiring all read-write operations occurring in a preset time period;
when the distance from the end time in the preset time period to the end time is preset time length, determining whether the read-write operation is finished;
and when at least one read-write operation in the read-write operations is not finished, the first timer sets the read-write operation timeout in the preset time period, and resets the second timer.
In one embodiment, the method may further comprise:
when read-write operation occurs, setting the read-write mark position of the read-write operation as a first value;
when the distance from the end time in the preset time period to the preset time period is longer, determining whether the read-write operation is finished or not, wherein the determining comprises the following steps:
detecting the state of a read-write mark bit of the read-write operation when the preset time duration is away from the end time in the preset time period;
and when the read-write mark bit of the read-write operation is still the first value, determining that the read-write operation is not finished.
In one embodiment, the method may further comprise:
and when the read-write operation is finished, setting the read-write mark position corresponding to the read-write operation as a second value.
When the distance from the end time in the preset time period to the preset time period is longer, determining whether the read-write operation is finished or not, wherein the determining comprises the following steps:
and when the distance from the end time in the preset time period to the preset time length is a second value, determining that the read-write operation is finished when the read-write mark bit of the read-write operation is the second value.
In an embodiment, after setting the read-write operation timeout within the preset time period when at least one of the read-write operations is not completed by read-write, the method may further include:
and setting the reading and writing mark position of the overtime reading and writing operation as a second value.
According to a second aspect of the embodiments of the present disclosure, there is provided a processing apparatus for read/write timeout, including:
the acquisition module is used for acquiring all read-write operations occurring in a preset time period;
the determining module is used for determining whether the read-write operation is finished or not when the preset time duration is away from the end time in the preset time period;
and the resetting module is used for setting the reading and writing operation timeout in the preset time period by the first timer and resetting the second timer when at least one reading and writing operation in the reading and writing operations is not completed.
In one embodiment, the apparatus may further comprise:
the first marking module is used for setting the read-write marking position of the read-write operation as a first value when the read-write operation occurs;
the determining module includes:
the detection submodule is used for detecting the state of a read-write mark bit of the read-write operation when the preset time duration is away from the end time in the preset time period;
and the first determining submodule is used for determining that the read-write operation is not finished when the read-write mark bit of the read-write operation is still a first value.
In one embodiment, the apparatus may further comprise:
and the second marking module is used for setting the read-write marking position corresponding to the read-write operation as a second value when the read-write operation is finished.
The determining module includes:
and the second determining submodule is used for determining that the reading and writing of the reading and writing operation are finished when the reading and writing mark bit of the reading and writing operation is a second value when the preset time duration is away from the end time in the preset time period.
In one embodiment, the apparatus may further comprise:
and the third marking module is used for setting the reading and writing marking position of the overtime reading and writing operation as a second value.
According to a third aspect of the embodiments of the present disclosure, there is provided a processing apparatus for read/write timeout, including:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to:
acquiring all read-write operations occurring in a preset time period;
when the distance from the end time in the preset time period to the end time is preset time length, determining whether the read-write operation is finished;
and when at least one read-write operation in the read-write operations is not finished, the first timer sets the read-write operation timeout in the preset time period, and resets the second timer.
According to a fourth aspect of embodiments of the present disclosure, there is provided a computer-readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the steps of the method according to any one of the embodiments of the first aspect.
The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:
according to the technical scheme, all read-write operations occurring in the preset time period are obtained, when the preset time length is away from the end time in the preset time period, whether the read-write operations are all completed is determined, when at least one read-write operation in the read-write operations is not completed, the first timer sets the read-write operation timeout in the preset time period, and the second timer is reset. Therefore, the operation that each previous read-write operation needs to be set for timeout is optimized to the reset of the timer only once in a certain time period. Because under the condition of large data volume, the read-write timeout is not required to be set for each communication, the performance loss caused by the setting timeout can be greatly reduced by stripping the timer logic, and the effect of performance optimization is achieved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a flow diagram illustrating a method for processing read and write timeouts, according to an example embodiment.
FIG. 2 is a flow diagram illustrating another read-write timeout processing method in accordance with an illustrative embodiment.
FIG. 3 is a flow diagram illustrating another read-write timeout processing method in accordance with an illustrative embodiment.
FIG. 4 is a flow diagram illustrating another read-write timeout processing method in accordance with an illustrative embodiment.
FIG. 5 is a flow diagram illustrating a method for read and write timeout processing according to an example embodiment.
Fig. 6 is a schematic structural diagram illustrating a processing apparatus for read-write timeout according to an exemplary embodiment.
Fig. 7 is a schematic structural diagram illustrating another read-write timeout processing apparatus according to an exemplary embodiment.
Fig. 8 is a schematic structural diagram illustrating another read-write timeout processing apparatus according to an exemplary embodiment.
Fig. 9 is a schematic structural diagram illustrating another read-write timeout processing apparatus according to an exemplary embodiment.
Fig. 10 is a block diagram illustrating a structure of a processing device adapted to read and write timeouts according to an example embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
In the related art, in the conventional socket communication, read-write timeout is required to be set for a data packet to be sent in the communication. Read-write timeout is a mechanism to detect network link disconnection. Under the condition of large data volume, because the system generates an independent timer for the read-write overtime, frequent setting of the read-write overtime causes little overhead to the system resources. In order to solve the problem, the embodiment of the present disclosure provides a method for processing read-write timeout, which can greatly reduce performance loss caused by setting timeout under the condition of high network concurrency by optimizing the timeout setting method, so as to achieve the purpose of saving resources.
Fig. 1 is a flowchart illustrating a processing method of read/write timeout according to an exemplary embodiment, where as shown in fig. 1, the processing method of read/write timeout includes the following steps 101 and 103:
in step 101, all read/write operations occurring within a preset time period are obtained.
The preset time period may be set according to actual conditions, for example, the preset time period may be set to 5S, that is, all read-write operations occurring within 5S are acquired.
In step 102, when the distance from the end time in the preset time period is a preset time length, it is determined whether the read-write operation is completed.
The preset time period is, for example, 5S, the end time in the preset time period is 5S, the preset duration is, for example, 4S, and when the preset duration is away from the end time in the preset time period, that is, at 9S, it is determined whether all the read-write operations in 0S to 5S are completed.
In step 103, when at least one of the read/write operations is not completed, the first timer sets the read/write operation timeout within the preset time period, and resets the second timer.
And if the 9 th S has unfinished read-write operation in all the read-write operations occurring in the 0S-5S, setting the read-write timeout, resetting the second timer at the bottom layer, and feeding errors back to the upper layer by the second timer.
In this embodiment, for each socket link, a timer, that is, a first timer, is separately established when connection starts, and when a read-write operation occurs, the first timer may set a read-write timeout for the read-write operation within a certain time period, instead of setting a timeout for each read-write operation, and after the read-write operation is set, the second timer on the bottom layer is reset. That is, the operation cycle of the first timer is a preset time period (e.g., 0S-5S), and the trigger cycle of the second timer is a preset time period (e.g., 0S-5S) + a preset duration (e.g., 4S).
In the method of the embodiment of the present disclosure, by obtaining all read-write operations occurring within a preset time period, when a preset time duration is obtained from an end time in the preset time period, it is determined whether all the read-write operations are completed, and when at least one read-write operation in the read-write operations is not completed, a first timer sets that the read-write operation within the preset time period is overtime, and resets a second timer. Therefore, the operation that each previous read-write operation needs to be set for timeout is optimized to the reset of the timer only once in a certain time period. Because under the condition of large data volume, the read-write timeout is not required to be set for each communication, the performance loss caused by the setting timeout can be greatly reduced by stripping the timer logic, and the effect of performance optimization is achieved.
In one embodiment, as shown in fig. 2, the method for processing read/write timeout may further include the following step 104:
in step 104, when a read/write operation occurs, the read/write flag position of the read/write operation is set to a first value.
Step 102 may be implemented as steps 1021-:
in step 1021, the state of the read/write flag bit of the read/write operation is detected when a preset time duration is reached from the end time in the preset time period.
In step 1022, when the read/write flag bit of the read/write operation is still the first value, it is determined that the read/write operation is not completed.
In one embodiment, the first value is 1, and when a read operation occurs, the read flag position is set to 1; when a write operation occurs, the flag position is set to 1. At intervals (at 9S in the above embodiment), the first timer detects the state of the current read/write flag bit, and if the current read flag bit is 1, it is determined that the read operation is over time, and if the current write flag bit is 1, it is determined that the write operation is over time.
In this embodiment, whether the read-write operation occurs within a period of time can be accurately determined by detecting the state of the read-write flag bit.
In one embodiment, as shown in fig. 3, the method for processing read/write timeout may further include the following step 105:
in step 105, when the read/write operation is completed, the read/write flag corresponding to the read/write operation is set to a second value.
Step 102 may be implemented as the following step 1023:
in step 1023, when the time length is preset from the end time in the preset time period, and the read-write flag bit of the read-write operation is a second value, it is determined that the read-write operation is completed.
In one embodiment, the first value is 1 and the second value is 0. When a reading operation occurs, setting the reading mark position to be 1; when a write operation occurs, the flag position is set to 1. When the reading operation is completed, setting the reading mark position to be 0; when the write operation is complete, the flag position is set to 0. At intervals (at 9S in the above embodiment), the first timer detects the state of the current read/write flag bit, and if the current read flag bit is 1, it is determined that the read operation is over time, and if the current write flag bit is 1, it is determined that the write operation is over time. If the current read flag bit is 0, the read operation is considered complete, and if the current write flag bit is 0, the write operation is complete.
In this embodiment, the state of the read/write flag bit is detected when the preset time duration is away from the end time in the preset time period, when the read/write flag bit of the read/write operation is still the first value, it is determined that the read/write operation is over time, and when the read/write flag bit of the read/write operation is the second value, it is determined that the read/write operation is completed. Therefore, whether the read-write operation occurs within a period of time can be accurately determined.
In an embodiment, as shown in fig. 4, after step 103, the method for processing the read-write timeout may further include the following step 106:
in step 106, the read-write flag position of the read-write operation that is timed out is set to a second value.
In this embodiment, in order to avoid network congestion, after the first timer is set to timeout, the corresponding flag position needs to be set to the second value.
The implementation is described in detail below by way of specific embodiments.
Fig. 5 is a flowchart illustrating a processing method of read-write timeout, which is applied to a network high concurrency situation according to an exemplary embodiment, where a first value is 1, a second value is 0, a preset time period is 5S, and a preset duration is 4S. As shown in fig. 5, the read/write timeout processing method includes the following steps 501 to 508:
in step 501, when a read/write operation occurs, the read/write flag position of the read/write operation is set to a first value.
In step 502, when the read/write operation is completed, the read/write flag corresponding to the read/write operation is set to a second value.
In step 503, all read/write operations occurring within a preset time period are obtained.
In step 504, when the distance from the end time in the preset time period is a preset time length, the states of the read-write flag bits of all read-write operations occurring in the preset time period are detected.
In step 505, when the read/write flag bit of the read/write operation is still the first value, it is determined that the read/write operation is not completed.
In step 506, when the read-write flag bit of the read-write operation is the second value, it is determined that the read-write operation is completed.
In step 507, when at least one of the read/write operations is not completed, the first timer sets the read/write operation timeout within the preset time period, and resets the second timer.
In step 508, the read/write flag position of the read/write operation that times out is set to a second value.
Since in the case of large data volumes, read-write timeouts do not need to be set every communication. In this embodiment, multiple times of timeout settings generated under a large data volume are optimized to a mode of timing settings, so that performance loss caused by setting timeout is greatly reduced, and an effect of performance optimization is achieved. Through development experiments, under the condition that a single machine requests 24w times per second, 15% of loss can be saved for CPU computing resources. The reset times of the timer are reduced by 1000 times by counting with 1 millisecond of one network request and 1 second of timeout.
The following are embodiments of the disclosed apparatus that may be used to perform embodiments of the disclosed methods.
Fig. 6 is a schematic structural diagram illustrating a read-write timeout processing apparatus according to an exemplary embodiment, where the apparatus may be implemented as part or all of an electronic device through software, hardware, or a combination of the two. As shown in fig. 6, the read/write timeout processing device includes:
an obtaining module 61 configured to obtain all read-write operations occurring within a preset time period;
a determination module 62 configured to determine whether the read-write operations are all completed when a preset time duration is reached from an end time in a preset time period;
and the resetting module 63 is configured to reset the second timer when the read-write operation is not completed in at least one read-write operation in the read-write operation, and the first timer sets the read-write operation timeout in a preset time period.
In this embodiment, for each socket link, a timer, that is, a first timer, is separately established when connection starts, and when a read-write operation occurs, the first timer may set a read-write timeout for the read-write operation within a certain time period, instead of setting a timeout for each read-write operation, and after the read-write operation is set, the second timer on the bottom layer is reset. That is, the operation cycle of the first timer is a preset time period (e.g., 0S-5S), and the trigger cycle of the second timer is a preset time period (e.g., 0S-5S) + a preset duration (e.g., 4S).
According to the device in the embodiment of the disclosure, all read-write operations occurring in the preset time period are obtained, when the preset time length is away from the end time in the preset time period, whether the read-write operations are all completed is determined, and when at least one read-write operation in the read-write operations is not completed, the first timer sets the read-write operation in the preset time period to be overtime, and resets the second timer. Therefore, the operation that each previous read-write operation needs to be set for timeout is optimized to the reset of the timer only once in a certain time period. Because under the condition of large data volume, the read-write timeout is not required to be set for each communication, the performance loss caused by the setting timeout can be greatly reduced by stripping the timer logic, and the effect of performance optimization is achieved.
In one embodiment, as shown in fig. 7, the processing device for read-write timeout may further include:
a first flag module 64 configured to set a read/write flag position of a read/write operation to a first value when the read/write operation occurs;
a determination module 62, comprising:
a detection sub-module 621 configured to detect a state of a read-write flag bit of the read-write operation when a preset time duration is apart from an end time in a preset time period;
the first determining sub-module 622 is configured to determine that the read/write operation is not read/written when the read/write flag bit of the read/write operation is still the first value.
In one embodiment, the first value is 1, and when a read operation occurs, the read flag position is set to 1; when a write operation occurs, the flag position is set to 1. At intervals (at 9S in the above embodiment), the first timer detects the state of the current read/write flag bit, and if the current read flag bit is 1, it is determined that the read operation is over time, and if the current write flag bit is 1, it is determined that the write operation is over time.
In this embodiment, whether the read-write operation occurs within a period of time can be accurately determined by detecting the state of the read-write flag bit.
In one embodiment, as shown in fig. 8, the processing device for read-write timeout may further include:
and the second marking module 65 is configured to set the read-write marking position corresponding to the read-write operation to a second value when the read-write operation completes the read-write operation.
A determination module 62, comprising:
the second determining sub-module 623 is configured to determine that the read/write operation is completed when the read/write flag bit of the read/write operation is a second value when the preset time duration is longer than the end time in the preset time period.
In one embodiment, the first value is 1 and the second value is 0. When a reading operation occurs, setting the reading mark position to be 1; when a write operation occurs, the flag position is set to 1. When the reading operation is completed, setting the reading mark position to be 0; when the write operation is complete, the flag position is set to 0. At intervals (at 9S in the above embodiment), the first timer detects the state of the current read/write flag bit, and if the current read flag bit is 1, it is determined that the read operation is over time, and if the current write flag bit is 1, it is determined that the write operation is over time. If the current read flag bit is 0, the read operation is considered complete, and if the current write flag bit is 0, the write operation is complete.
In this embodiment, the state of the read/write flag bit is detected when the preset time duration is away from the end time in the preset time period, when the read/write flag bit of the read/write operation is still the first value, it is determined that the read/write operation is over time, and when the read/write flag bit of the read/write operation is the second value, it is determined that the read/write operation is completed. Therefore, whether the read-write operation occurs within a period of time can be accurately determined.
In one embodiment, as shown in fig. 9, the processing device for read-write timeout may further include:
and a third flag block 66 configured to set the read/write flag position of the read/write operation that is timed out to a second value.
In this embodiment, in order to avoid network congestion, after the first timer is set to timeout, the corresponding flag position needs to be set to the second value.
The embodiment of the present disclosure further provides a processing apparatus for read-write timeout, including:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to:
acquiring all read-write operations occurring in a preset time period;
when the distance from the end time in the preset time period to the end time is preset time length, determining whether the read-write operation is finished;
and when at least one read-write operation in the read-write operations is not finished, the first timer sets the read-write operation timeout in the preset time period, and resets the second timer.
The processor is further configured to:
when read-write operation occurs, setting the read-write mark position of the read-write operation as a first value;
detecting the state of a read-write mark bit of the read-write operation when the preset time duration is away from the end time in the preset time period;
and when the read-write mark bit of the read-write operation is still the first value, determining that the read-write operation is not finished.
The processor is further configured to:
and when the read-write operation is finished, setting the read-write mark position corresponding to the read-write operation as a second value.
And when the distance from the end time in the preset time period to the preset time length is a second value, determining that the read-write operation is finished when the read-write mark bit of the read-write operation is the second value.
The processor is further configured to:
and setting the reading and writing mark position of the overtime reading and writing operation as a second value.
Fig. 10 is a block diagram illustrating a processing apparatus for read-write timeout, which is suitable for a terminal device, according to an exemplary embodiment. For example, the apparatus 1200 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.
The apparatus 1200 may include one or more of the following components: processing component 1202, memory 1204, power component 1206, multimedia component 1208, audio component 1210, input/output (I/O) interface 1212, sensor component 1214, and communications component 1216.
The processing component 1202 generally controls overall operation of the apparatus 1200, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components 1202 may include one or more processors 1220 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 1202 can include one or more modules that facilitate interaction between the processing component 1202 and other components. For example, the processing component 1202 can include a multimedia module to facilitate interaction between the multimedia component 1208 and the processing component 1202.
The memory 1204 is configured to store various types of data to support operation at the apparatus 1200. Examples of such data include instructions for any application or method operating on the device 1200, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 1204 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
A power supply component 1206 provides power to the various components of the device 1200. Power components 1206 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for apparatus 1200.
The multimedia components 1208 include a screen that provides an output interface between the device 1200 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1208 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the apparatus 1200 is in an operation mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The I/O interface 1212 provides an interface between the processing component 1202 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
The sensor assembly 1214 includes one or more sensors for providing various aspects of state assessment for the apparatus 1200. For example, the sensor assembly 1214 may detect an open/closed state of the apparatus 1200, the relative positioning of the components, such as a display and keypad of the apparatus 1200, the sensor assembly 1214 may also detect a change in the position of the apparatus 1200 or a component of the apparatus 1200, the presence or absence of user contact with the apparatus 1200, orientation or acceleration/deceleration of the apparatus 1200, and a change in the temperature of the apparatus 1200. The sensor assembly 1214 may include a proximity sensor configured to detect the presence of a nearby object in the absence of any physical contact. The sensor assembly 1214 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1214 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communications component 1216 is configured to facilitate communications between the apparatus 1200 and other devices in a wired or wireless manner. The apparatus 1200 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 1216 receives the broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communications component 1216 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the apparatus 1200 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.
In an exemplary embodiment, a non-transitory computer readable storage medium comprising instructions, such as memory 1204 comprising instructions, executable by processor 1220 of apparatus 1200 to perform the above-described method is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
A non-transitory computer readable storage medium, wherein instructions of the storage medium, when executed by a processor of an apparatus 1200, enable the apparatus 1200 to perform the above-mentioned read-write timeout processing method, the method comprising:
acquiring all read-write operations occurring in a preset time period;
when the distance from the end time in the preset time period to the end time is preset time length, determining whether the read-write operation is finished;
and when at least one read-write operation in the read-write operations is not finished, the first timer sets the read-write operation timeout in the preset time period, and resets the second timer.
In one embodiment, the method may further comprise:
when read-write operation occurs, setting the read-write mark position of the read-write operation as a first value;
when the distance from the end time in the preset time period to the preset time period is longer, determining whether the read-write operation is finished or not, wherein the determining comprises the following steps:
detecting the state of a read-write mark bit of the read-write operation when the preset time duration is away from the end time in the preset time period;
and when the read-write mark bit of the read-write operation is still the first value, determining that the read-write operation is not finished.
In one embodiment, the method may further comprise:
and when the read-write operation is finished, setting the read-write mark position corresponding to the read-write operation as a second value.
When the distance from the end time in the preset time period to the preset time period is longer, determining whether the read-write operation is finished or not, wherein the determining comprises the following steps:
and when the distance from the end time in the preset time period to the preset time length is a second value, determining that the read-write operation is finished when the read-write mark bit of the read-write operation is the second value.
In an embodiment, after setting the read-write operation timeout within the preset time period when at least one of the read-write operations is not completed by read-write, the method may further include:
and setting the reading and writing mark position of the overtime reading and writing operation as a second value.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A method for processing read-write timeout is characterized by comprising the following steps:
when read-write operation occurs in socket connection, the first timer and the second timer start timing;
acquiring all read-write operations occurring within a preset time period timed by the first timer in the socket connection;
when the preset time length which is timed by the second timer and is far away from the end time in the preset time period is reached, determining whether the read-write operation is finished;
and when at least one read-write operation in the read-write operations is not finished, the first timer sets the read-write operation timeout in the preset time period, and resets the second timer.
2. The method of claim 1, further comprising:
when read-write operation occurs, setting the read-write mark position of the read-write operation as a first value;
when the preset time length from the end time in the preset time period counted by the second timer is reached, determining whether the read-write operation is finished or not, including:
when the preset time length which is timed by the second timer and is far away from the end time in the preset time period reaches, detecting the state of a read-write mark bit of the read-write operation;
and when the read-write mark bit of the read-write operation is still the first value, determining that the read-write operation is not finished.
3. The method of claim 2, further comprising:
when the read-write operation is finished, setting the read-write mark position corresponding to the read-write operation as a second value;
when the preset time length from the end time in the preset time period counted by the second timer is reached, determining whether the read-write operation is finished or not, including:
and when the preset time length which is timed by the second timer and is far away from the end time in the preset time period is reached, and the read-write mark bit of the read-write operation is a second value, determining that the read-write operation is finished.
4. The method according to claim 2 or 3, wherein after the first timer sets the read-write operation timeout within the preset time period when at least one of the read-write operations is not completed, the method further comprises:
and setting the reading and writing mark position of the overtime reading and writing operation as a second value.
5. A device for processing read/write timeout, comprising:
the acquisition module is used for starting timing by the first timer and the second timer when read-write operation occurs in socket connection; acquiring all read-write operations occurring within a preset time period timed by the first timer in the socket connection;
the determining module is used for determining whether the read-write operation is finished or not when a preset time length which is timed by the second timer and is far away from the end time in the preset time period is reached;
and the resetting module is used for setting the reading and writing operation timeout in the preset time period by the first timer and resetting the second timer when at least one reading and writing operation in the reading and writing operations is not completed.
6. The apparatus of claim 5, further comprising:
the first marking module is used for setting the read-write marking position of the read-write operation as a first value when the read-write operation occurs;
the determining module includes:
the detection submodule is used for detecting the state of a read-write mark bit of the read-write operation when a preset time length which is timed by the second timer and is far away from the end time in the preset time period is reached;
and the first determining submodule is used for determining that the read-write operation is not finished when the read-write mark bit of the read-write operation is still a first value.
7. The apparatus of claim 6, further comprising:
the second marking module is used for setting the read-write marking position corresponding to the read-write operation as a second value when the read-write operation is finished;
the determining module includes:
and the second determining submodule is used for determining that the read-write operation is finished when the read-write flag bit of the read-write operation is a second value when the preset time length which is timed by the second timer and is far away from the end time in the preset time period is reached.
8. The apparatus of claim 6 or 7, further comprising:
and the third marking module is used for setting the reading and writing marking position of the overtime reading and writing operation as a second value.
9. A device for processing read/write timeout, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to:
when read-write operation occurs in socket connection, the first timer and the second timer start timing; acquiring all read-write operations occurring within a preset time period timed by the first timer in the socket connection;
when the preset time length which is timed by the second timer and is far away from the end time in the preset time period is reached, determining whether the read-write operation is finished;
and when at least one read-write operation in the read-write operations is not finished, the first timer sets the read-write operation timeout in the preset time period, and resets the second timer.
10. A computer-readable storage medium having stored thereon computer instructions, which when executed by a processor, implement the steps of the method of any one of claims 1 to 4.
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| CN110018789B (en) * | 2019-03-26 | 2022-03-25 | 记忆科技(深圳)有限公司 | Method, device and storage medium for dynamically adapting Tr and Tprom time of NAND |
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| US8386667B2 (en) * | 2008-08-26 | 2013-02-26 | Sun Management, Llc | Techniques for managing the transmission and reception of data fragments |
| CN103019651A (en) * | 2012-08-02 | 2013-04-03 | 青岛海信传媒网络技术有限公司 | Parallel processing method and device for complex tasks |
| CN103477331A (en) * | 2012-02-20 | 2013-12-25 | 松下电器产业株式会社 | Initiator apparatus, target apparatus, communication system, timeout detection method, and timeout detection program |
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| US8386667B2 (en) * | 2008-08-26 | 2013-02-26 | Sun Management, Llc | Techniques for managing the transmission and reception of data fragments |
| CN103477331A (en) * | 2012-02-20 | 2013-12-25 | 松下电器产业株式会社 | Initiator apparatus, target apparatus, communication system, timeout detection method, and timeout detection program |
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