CN107689222A - A kind of display device - Google Patents
A kind of display device Download PDFInfo
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- CN107689222A CN107689222A CN201711023283.1A CN201711023283A CN107689222A CN 107689222 A CN107689222 A CN 107689222A CN 201711023283 A CN201711023283 A CN 201711023283A CN 107689222 A CN107689222 A CN 107689222A
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- signal line
- voltage
- scan signal
- signal
- scanning
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
Abstract
The present embodiments relate to a kind of display device, including：Multiple pixels；The image signal line of data-signal is provided to the multiple pixel；The scan signal line intersected with image signal line；Gate driving circuit, scanning signal is output to scan signal line by it, and exports scanning signal to drive scan signal line；And control circuit, it has the waveform voltage in the cycle with voltage change by control signal control gate drive circuit, control signal；Wherein, at the beginning of at least one of which scan period of scanning signal, the voltage of the scanning signal rises, and tilt to high level from low level with the parabolical curvature of convex, at the end of during at least one of which scans, the voltage of the scanning signal declines, and tilts to low level from high level with the parabolical curvature of matrix.The embodiment of the present invention can control scanning signal it is not flown up or is declined, it is ensured that the level deviation of the pixel potential as caused by parasitic capacitance can be reduced.
Description
Technical field
The present invention relates to matrix type liquid crystal to show（LCD）The display device such as equipment and its display methods, more particularly to one
Kind of display device, such as LCD device, wherein each display pixel equipped with for example, as switch module thin film transistor (TFT) and
Its display methods.
Background technology
LCD device is widely used as the display device for TV, graphic alphanumeric display etc..Wherein, sizable pass is caused
Note is wherein each display pixel equipped with thin film transistor (TFT)（Hereinafter referred to as TFT）As the LCD device of switch module, because
Such LCD device is even in the display image for also not producing crosstalk between adjacent display pixel.Existing LCD device includes
As the LCD of critical piece, and driving circuit section, and LCD is by the way that liquid-crystal composition is sealed in a pair
Between electrode substrate, and deflecting plates is arranged on the outer surface of electrode substrate and formed.
Tft array substrate is in the matrix form to form multiple signal wires and multiple scan lines on transparent insulating substrate,
Transparent insulating substrate may be, for example, glass.In signal wire and each intersection of scan line, switch module is provided with, it is by even
The TFT for being connected to pixel electrode is formed, and is provided with alignment film and is covered above-mentioned all parts.On the other hand, as another electrode
The counter substrate of substrate is formed by reverse electrode and alignment film lamination, and counter substrate is almost made with transparent insulating substrate completely,
For example, glass substrate, and it is used as tft array substrate.And driving circuit section, driven by scan signal line drive circuit, signal wire
Dynamic circuit and reverse electrode drive circuit are formed, and it connects the scan line of panel, signal wire and reverse electrode respectively.Control electricity
Road is the circuit for control signal line drive circuit and scan signal line drive circuit.
In the transmission equivalent circuit in the case that the signal transmission delay of scan signal line is focused, multiple parasitic capacitances
It is included in cross capacitance caused by the point of intersection of scan signal line and signal wire.Therefore, scan signal line forms signal delay and passed
Defeated path.As noted previously, as the level deviation that pixel potential occurs caused by the parasitic capacitance of panel itself is entirely showing
Show uneven in plane, and because LCD device has larger screen and becomes higher definition, therefore become more
It is difficult to ignore.Therefore, the difference of the level deviation on whole display plane can not be absorbed by biasing the conventional scheme of backward voltage, from
And optimal exchange driving can not be carried out relative to each pixel.Therefore, cause and such as flashed caused by alternating component applies
The defects of with aging afterimage.
The content of the invention
Technical problems to be solved of the embodiment of the present invention are, there is provided a kind of display device, can fully suppress due to picture
Flicker etc., the generation of parasitic capacitance caused by the fluctuation of plain current potential, and reach fine definition and high-performance.
In order to solve the above technical problems, the embodiment of the present invention provides following technical scheme first：A kind of display device, bag
Include：
It is arranged to rectangular multiple pixels；
For providing the image signal line of data-signal to the multiple pixel；
The scan signal line intersected with described image signal wire；
Gate driving circuit, scanning signal is output to scan signal line by it, and exports scanning signal to drive scan signal line；
And
Control circuit, it controls the gate driving circuit by control signal, and the control signal has with voltage change
Cycle waveform voltage；
Wherein, at the beginning of at least one of which scan period of the scanning signal, the voltage of the scanning signal rises, and
High level is tilted to from low level with the parabolical curvature of convex, it is described at the end of during at least one of which scans
The voltage of scanning signal declines, and tilts to the low level from the high level with the parabolical curvature of matrix.
Alternatively, the control circuit by the control signal by being input to the gate driving circuit, to cause
State the part change of the change between the high level of scanning signal and low level.
Alternatively, the gate driving circuit includes the shift register portion being made up of the cascade of multiple triggers, and
Selecting switch, it is switched on or off individually according to the output of the multiple trigger.
Alternatively, the display device also includes the capacitor for being connected to the input of the gate drivers, and voltage source leads to
The input that first switch is connected to the gate drivers is crossed, and resistance is parallel-connected to the electric capacity by second switch
Device.
On the other hand, the embodiment of the present invention also provides a kind of display device, including：
It is arranged to rectangular multiple pixels；
For providing the image signal line of data-signal to the multiple pixel；
The scan signal line intersected with described image signal wire；
Gate driving circuit, scanning signal is output to the scan signal line by it, and exports scanning signal to drive scanning to believe
Number line；
Control circuit, it controls the gate driving circuit by control signal, and the control signal has with voltage change
Cycle waveform voltage；And
Capacitor, the input of the gate drivers is connected to, wherein voltage source is connected to the grid by first switch and driven
The input of dynamic device, and resistance is parallel-connected to the capacitor by second switch,
At the beginning of at least one of which scan period of wherein described scanning signal, the voltage of the scanning signal rises, and
High level is tilted to from low level with the parabolical curvature of convex, it is described at the end of during at least one of which scans
The voltage of scanning signal declines, and tilts to the low level from the high level with the parabolical curvature of matrix,
Wherein described control circuit by the control signal by being input to the gate driving circuit, to cause the scanning letter
Number high level and low level between change a part change,
Wherein described gate driving circuit includes the shift register portion being made up of the cascade of multiple triggers, and selection is opened
Close, be switched on or off individually according to the output of the multiple trigger.
By using above-mentioned technical proposal, the embodiment of the present invention at least has the advantages that：Generally, due in film
Parasitic capacitance is inevitably formed between the grid of transistor and drain electrode.In normal conditions scanning signal fly up and under
In the case of drop, thin film transistor (TFT) immediately becomes cut-off state, therefore the current potential of pixel electrode（Hereinafter referred to as pixel potential）Drop
Low ascending amount and slippage corresponding to the scanning signal caused by parasitic capacitance（Scanning voltage subtracts Non-scanning mode voltage）, from
And pixel potential occurs significant level deviation.This significant level deviation that pixel potential occurs causes the image of display
Flicker, the deterioration of display etc..However, according to above-mentioned display device, the rise and fall of scanning signal are controlled, therefore can control
Scanning signal processed makes it not fly up or decline.Which ensure that the level deviation of the pixel potential as caused by parasitic capacitance can
Reduce.
In addition, being arranged in for example by the wire made of glass in transparent insulation substrate and nonideal path, and cause
Form the signal delay path for undergoing signal delay to a certain extent.Therefore, said structure is ensured as caused by signal delay
Display inhomogeneities is eliminated, and the level deviation of the pixel potential as caused by parasitic capacitance becomes smaller and uniform.As a result,
High performance display image can be obtained.
Brief description of the drawings
Fig. 1 is the explanation figure for the structure for representing existing liquid crystal display.
Fig. 2 is the explanation figure for the structure for representing existing scan signal line drive circuit.
Fig. 3 be by pixel capacitor and auxiliary capacitor be parallel-connected to reverse electrode drive circuit reverse potential it is aobvious
Show the equivalent circuit diagram of pixel.
Fig. 4 is the drive waveforms figure of existing liquid crystal display.
Fig. 5 is the explanation figure for illustrating the present invention and prior art contrast.
Fig. 6 is the transmission equivalent circuit diagram in the case where the signal transmission delay of a scan signal line is focused.
Fig. 7 is the waveform for representing the waveform that the component according to embodiments of the present invention from scan signal line drive circuit exports
Figure.
Fig. 8 is to represent the scan signal line waveform near the input side of scan signal line, the other end of scan signal line
Neighbouring scan signal line waveform and the oscillogram of each pixel potential.
Fig. 9 is the explanation figure of the configuration for the scan signal line drive circuit for representing another embodiment of the present invention.
Figure 10 is the frame of the structure of the major part for the scan signal line drive circuit for representing a further embodiment of this invention
Figure.
Figure 11 is the electricity of the configuration of the major part for the scan signal line drive circuit for representing a further embodiment of this invention
Lu Tu.
Figure 12 is the oscillogram of the waveform for the major part for representing Figure 11.
Figure 13 is the ripple for the waveform that the component from scan signal line drive circuit represented according to embodiments of the present invention exports
Shape figure.
Figure 14 is the scan signal line waveform near the input side of the scan signal line represented according to embodiments of the present invention,
The oscillogram of scan signal line waveform and each pixel potential near the other end of scan signal line.
Figure 15 is the ripple for the waveform that the component from scan signal line drive circuit represented according to embodiments of the present invention exports
Shape figure.
Figure 16 is the scan signal line ripple near the input side of the scan signal line represented according to an embodiment of the invention
Shape, the oscillogram of scan signal line waveform and each pixel potential near the other end of scan signal line.
Figure 17 is the ripple for the waveform that the component from scan signal line drive circuit represented according to embodiments of the present invention exports
Shape figure.
Figure 18 is the scan signal line ripple near the input side of the scan signal line represented according to an embodiment of the invention
Shape, the oscillogram of scan signal line waveform and each pixel potential near the other end of scan signal line.
Figure 19 is the ripple for the waveform that the component from scan signal line drive circuit represented according to embodiments of the present invention exports
Shape figure.
Figure 20 is the scan signal line ripple near the input side of the scan signal line represented according to an embodiment of the invention
Shape, the oscillogram of scan signal line waveform and each pixel potential near the other end of scan signal line.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation describes.Obviously, described embodiment is some embodiments of the present application, rather than whole embodiments.Based on this Shen
Please in embodiment, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example, belong to the scope of the application protection.
The present invention is carried out on the basis of following：In the display device of such as LCD device, input signal not trusted
Number delay transmission characteristic influence and change, the input signal is input to the wiring being arranged in transparent insulation substrate, also,
By doing so it is possible, any opening position that can be on wire obtains the waveform identical waveform with input signal, while can make
It is constant to be influenceed caused by signal intensity in whole electric wire.
The present invention is also carried out based on following aspect：It is special according to the ON/OFF of the TFT being connected with wire etc. switch module
Property, can be by making input waveform and substantially homogeneous in the certain point waveform of wire, to reduce the level caused by parasitic capacitance
Displacement.
Fig. 1 is refer to, LCD device described above includes the LCD 1 as critical piece, and driving as shown in Figure 1
Circuit part, and LCD 1 be by the way that liquid-crystal composition is sealed in into a pair of electrodes substrate between, and deflecting plates is set
Formed on the outer surface of electrode substrate.
Tft array substrate be in the matrix form by multiple signal wire S1, S2 ... SN and multiple scan line G1, G2 ... GN shapes
Into on transparent insulating substrate 100, transparent insulating substrate 100 may be, for example, glass.Crossed in signal wire and each of scan line
Place, is provided with switch module 102, and it is made up of the TFT for being connected to pixel electrode 103, and is provided with alignment film covering
State all parts.
On the other hand, the counter substrate as another electrode substrate is formed by reverse electrode 101 and alignment film lamination, reversely
Substrate is almost made with transparent insulating substrate completely, for example, glass substrate, and it is used as tft array substrate.And drive circuit portion
Point, it is made up of scan signal line drive circuit 300, signal-line driving circuit 200 and reverse electrode drive circuit COM, its point
Not Lian Jie LCD scan line, signal wire and reverse electrode.Control circuit 600 is for control signal line drive circuit 200
With the circuit of scan signal line drive circuit 300.
Scan signal line drive circuit 300 can be considered gate drivers, and the shifting by being for example made up of M trigger cascade
Bit register part 3a and selecting switch 3b composition, also, selecting switch 3b according to the output signal of the trigger received and
Opening/closing is beaten, as shown in Figure 2.Input port VD1 in each selecting switch 3b two input ports is provided with grid startup
Voltage Vgh, it is enough to make switch module 102 reach opening (see Fig. 1), and another input port VD is provided with grid pass
Voltage Vgl is closed, it is enough to make switch module 102 reach closed mode.Accordingly, in response to clock signal（GCK）, grid, which starts, to be believed
Number（GSP）It is sequentially transmitted by trigger, and is outputed sequentially to selecting switch 3b.In response to this, each selecting switch
3b selects the voltage Vgh for turning on TFT, and in a scan period（TH）Period is output to scan signal line 105, then
Voltage Vgl for TFT to be turned off is output to scan signal line 105.Under operating herein, exported from signal-line driving circuit 200
Picture signal to individual signal lines 104 can be write in indivedual corresponding pixels.
Fig. 3 shows a display pixel P（I, j）Equivalent circuit, wherein, pixel capacitor Clc and auxiliary capacitor
Cs is parallel-connected to reverse electrode drive circuit COM reverse potential VCOM.In figure, Cgd is represented between grid and drain electrode
Parasitic capacitance.Fig. 4 shows the drive waveforms of conventional LCD apparatus.As shown in figure 4, Vg is the letter for single scanning signal wire
Number waveform, Vs is the waveform for the signal of single signal line, and Vd is drain waveforms.
Here, traditional driving method will be illustrated with reference to figure 1, Fig. 3, Fig. 4 in the lump below.Incidentally, it is well known that liquid
Crystalline substance is needed to exchange driving, and to avoid the deterioration of the generation of aging afterimage and display image, and tradition described below is driven
Dynamic method is so that for example, frame Reversal Drive illustrates, it is a kind of exchange driving.When scanning voltage Vgh is as shown in Figure 4
The firstth area (TF1) section by scan signal line drive circuit 300 put on individual monitor pixel P (i, j) gate g (i,
J), TFT reaches starting state, and the source electrode that the image signal voltage Vsp from signal-line driving circuit 200 passes through TFT
Pixel electrode is applied to drain electrode.Until in next area（TF2）Before period applies scanning voltage Vgh, pixel electrode maintains
Pixel potential Vdp as shown in Figure 4.Due to reverse electrode have be set as by reverse electrode drive circuit COM it is predetermined anti-
To current potential VCOM current potential, so the liquid-crystal composition being maintained between pixel electrode and reverse electrode is according to pixel potential Vdp
Potential difference between reverse potential VCOM is responded, and is shown so as to carry out image.
Similarly, as shown in figure 4, when scanning voltage Vgh is in the secondth area（TF2）Period is from scan signal line drive circuit
The 300 individual monitor pixel P being applied to（I, j）TFT gate g（I, j）When, TFT reaches starting state, and comes from signal
The image signal voltage Vsn of line drive circuit 200 is written into pixel electrode.Pixel electrode maintains pixel potential Vdn, and liquid
Crystal composite is responded according to the potential difference between pixel potential Vdn and reverse potential VCOM, so as to realize LCD alternating-current
Image is performed while driving to show.Due to that will necessarily can not be kept away between TFT grid and drain electrode under structure as shown in Figure 3
Form parasitic capacitance Cgd with exempting from, in scanning voltage Vgh decline, level shift Vd is betided as caused by parasitic capacitance Cgd
Pixel potential Vd, as shown in Figure 4.Make the Non-scanning mode voltage of scanning signal（TFT is in voltage during OFF state）For Vgl, and
The level deviation Vd that the pixel potential Vd caused by the parasitic capacitance Cgd inevitably formed in TFT occurs is expressed as：
Vd=Cgd（Vgh-Vgl）/（Clc+Cs+Cgd）
The problems such as image flicker and display deterioration are caused due to level deviation, so being unfavorable for LCD device, wherein needing
The performance of definition that will be higher and Geng Gao.Therefore, the counter potential of such measure, i.e. comparative electrode traditionally has been proposed
VCOM is biased in advance so that the level deviation Vd as caused by parasitic capacitance Cgd reduces.However, by above-mentioned routine techniques, it is difficult
With by scan signal line G（1）、G（2）、...G（j）、...G（M）Arrange in an ideal way so that scan signal line does not suffer from
Signal delay is transmitted, therefore so causes the scan signal line of arrangement to undergo signal delay to a certain extent.
In addition, TFT is not to be entirely startup/shut-off switch, but there is V-I characteristics as shown in Figure 5（Grid voltage-
Drain current characteristics）.As shown in figure 5, the voltage for being applied to TFT gate is drawn as axis of abscissas, and draw drain voltage work
For the longitudinal axis.Usual scanning impulse is made up of two voltage levels, and one is the voltage level for being enough to make TFT reach conducting state
Vgh, another is the voltage level Vgl for being enough to make TFT reach off state.However, as illustrated, TFT threshold level VT
There is also the conducting region of centre between Vgh（The range of linearity）.
Fig. 6 is in a scan signal line G（j）Signal transmission delay be focused in the case of transmission equivalent circuit
Figure.In figure 6, rg1, rg2, rg3...rgN mainly represent resistive component.Cg1, cg2, cg3...cgN are represented and scanning signal
Capacity coupled various parasitic capacitances in cable architecture.Parasitic capacitance is included in caused by the point of intersection of scan signal line and signal wire
Cross capacitance.Therefore, scan signal line forms signal delay transmission path as depicted.As noted previously, as panel itself
Parasitic capacitance Cgd caused by pixel potential Vd occur level deviation Vd it is uneven in whole display plane, and by
There is larger screen in LCD device and become higher definition, therefore become more to be difficult to ignore.Therefore, biasing is anti-
The difference of the level deviation on whole display plane can not be absorbed to the conventional scheme of voltage, so that can not be relative to each pixel
Carry out optimal exchange driving.Therefore, cause due to alternating component apply caused by such as flicker with aging afterimage the defects of.
Hereinafter, 7 ~ Figure 12 of reference picture illustrates embodiments of the present invention.Pay attention to, CLK represents clock signal in the figure 7.Fig. 7
Output waveform VG (j-1), the VG (j) and VG (j+1) according to the scan signal line drive circuit of the present embodiment are shown with Fig. 8,
Scan signal line waveform Vg（1, j）Near the input side of scan signal line, scan signal line waveform Vg（N, j）Believe in scanning
Near the other end of number line, also, each pixel potential Vd（1, j）And Vd（N, j）Near the front end of scan signal line.Scanning
The output waveform VG of signal-line driving circuit（j）In, the rise and fall from scanning voltage Vgh to Non-scanning mode voltage Vgl be with
The slope represented by rate of change SxF and SxE（Gradient）Rise and fall, it is the knots modification of time per unit, such as Fig. 1 institutes
Show.
By suitably setting rate of change SxF and SxE, the change of the rising waveform inputted near side of scan signal line
Rate SxF1 and the rate of change SxFN scan signal lines of the rising waveform near the other end of scan signal line become basic phase
Deng, scan signal line input side near falling waveform rate of change SxE1 and near the other end of scan signal line
The rate of change SxEN scan signal lines of rising waveform become of substantially equal, without being passed by the parasitic signal delay of scan signal line
The influence of defeated characteristic, such as scan signal line waveform Vg（1, j）And Vg（N, j）（See Fig. 7 and Fig. 8）.This causes due to scanning signal
The level deviation that pixel potential Vd caused by parasitic capacitance Cgd occurs in line becomes substantially uniform on whole display plane.Knot
Fruit, by application biasing counter potential VCOM conventional scheme, to reduce in advance due to parasitic parasitism in scan signal line
Level deviation Vd that pixel potential Vd occurs caused by electric capacity Cgd etc., display device can realize that flicker can be reduced fully
And the defects of such as aging afterimage will not occur.
In order that the rate of change SxF1 and SxFN of rising waveform are substantially identical, and make the rate of change SxE1 of falling waveform
Be substantially identical with SxEN, without being influenceed by its position in scan line, can be based on signal delay transmission characteristic come
Carry out the control of rise and fall.The slope that control by this way makes it possible to scanning signal is any in scan line
Position is all of substantially equal, so that the level shift of pixel electrode is of substantially equal.
Based on signal delay transmission characteristic rather than it is above-mentioned rise or fall control, can the grid voltage based on TFT-
Drain current characteristics control the raising and lowering slope of scanning signal.In TFT, the voltage in application threshold voltage ranges
To its grid conducting voltage when, the drain electrode depending on the TFT of grid voltage（Conducting resistance）Electric current linearly changes.In other words
Say, TFT is not in the ON states of binary condition, but reaches middle ON states（Wherein drain current is according to grid voltage
Change in an analogue form）.
Optionally, scanning signal can be controlled with grid voltage-drain current characteristics based on TFT signal delay transmission
The slope of raising and lowering.In such a case, it is possible to the slope of any rising of scanning signal is set to be substantially equal to scanning letter
The rate of rise from anywhere on number line, and the slope of any decline of scanning signal is substantially equal to scan signal line
Descending slope from anywhere in upper.
Optionally, the rate of change SxF of the sloping portion of high level is risen to by low level, different from being dropped to by high level
The slope S xE (as shown in Figure 7) of low level sloping portion, in this manner, can make near the input of scan signal line
And the waveform near terminal will not be influenceed by signal delay propagation characteristic possessed by scan signal line parasitics ground, form
To be roughly the same, and the generation of pixel potential Vd level displacement is reduced, realize that nothing prints off image retention etc. and shows that bad display is set
It is standby.As a result, make the level deviation of pixel potential substantially mutually equal, and reduce each level deviation.
In addition, the voltage level VT shown in Fig. 8 is the threshold voltage of the TFT shown in Fig. 7, and due in scanning signal from sweeping
Retouch during voltage Vgh drops to threshold V T, TFT keeps starting state, so hardly occur within the above-mentioned time by
Level deviation caused by parasitic capacitance Cgd.On the other hand, due to making TFT cause the scanning signal line skew of off state（VT-
Vgl）Influenceed by parasitic capacitance Cgd, level deviation occurs.
Due to meeting VT-Vgl in the present embodiment<Vgh-Vgl, it can not only eliminate by the parasitism on whole display plane
The difference of level deviation caused by electric capacity, and each level deviation as caused by parasitic capacitance Cgd can be reduced.
Here, by prior art scan signal line drive circuit side scan signal line end near pixel post
Level deviation caused by raw electric capacity Cgd and pixel potential Vd is Vd（1）, in the electricity that the pixel of the other end of prior art occurs
Flat skew is Vd（N）In the case of, and then make pixel potential Vd level deviation this implementation near the end of scan signal line
The side of the scan signal line drive circuit of example is Vdx（1）, and what the pixel potential Vd of its other end in the present embodiment occurred
Level deviation is Vdx（N）.In this case, because the rate of change SxF1 of rising waveform, SxFN are substantially identical, and due to
Due to the rate of change SxE1 of rising waveform, SxEN is substantially identical, without being passed by the parasitic signal delay of said scanning signals line
The influence of defeated characteristic, therefore the level deviation that the pixel potential Vd as caused by parasitic capacitance Cgd occurs is on whole display plane
Become substantially uniform, and meet following relation（See Fig. 2 and Figure 15）：
Vdx(1)=Vdx(N)<Vd(N)<Vd(1)
Therefore, the counter potential VCOM of opposite electrode conventional scheme is biased by application so that from level caused by parasitic capacitance
Skew is tentatively reduced, and can provide a kind of display device with relatively low bias level, less flicker and display defect, example
Such as, aging afterimage is reduced, and there is less power consumption.
Hereinafter, reference picture 9 illustrates embodiments of the present invention.For convenience's sake, there is structure identical with Fig. 1（Work(
Energy）Component.It is presented with like reference characters in Fig. 9.
In an embodiment of the present invention, the situation of traditional scan signal line drive circuit as shown in Figure 2, as shown in figure 9,
Scan signal line drive circuit is included by M trigger（F1, F2..., Fj..., FM）Cascade the shift register portion of composition
3a, and selecting switch 3b are closed respectively according to the output of trigger.It is defeated in each selecting switch 3b two input terminals
Enter terminal VD1 and be provided with the gate-on voltage Vgh for being enough to make TFT reach conducting state, and another input terminal VD2 quilts
Gate-on voltage is provided with, turns off voltage Vgl, it is enough to make TFT reach OFF state.Each switch 3b public terminal with
Scan signal line 105 connects.
Accordingly, in response to clock signal（CLK）, grid enabling signal（GSP）Transmitted by trigger order, and by order
Ground is output to selecting switch 3b.In response to this, in a scan period（TH）Period, each selecting switch 3b select to be used to make
TFT reaches the voltage Vgh of conducting state, and is output to scan signal line 105, then selects voltage Vgl, and TFT, which is reached, to close
Disconnected state is simultaneously output to scan signal line 105.
The each slew-rate control component SC being arranged between selecting switch 3b and input terminal VD2 is equal to control gate drive
The output impedance control assembly of the impedance of each output end of dynamic device, it only increases output impedance in raising and lowering.Output
To the grid cut-off voltage of scan signal line（The raising and lowering of grid cut-off voltage is hereinafter referred to as " on scan signal line
Rise and scan signal line rise and fall "）, and make the output waveform rust of gate drivers.This causes the rising in display panel
With the difference of decrease speed, it comes from the waveform dullness of the transmission characteristic as scan signal line and cancelled each other out.So as to suppress
The level deviation Vd generation caused by above-mentioned parasitic capacitance Cgd influence, while make the level between whole display panel
Offset equal.
On the other hand, conversion rate control component SC is not particularly limited, and can change output impedance to change
Any component of raising and lowering speed.Can be by using, for example, by control the grid voltage of MOS transistor component come
The known control technology for adjusting impedance is realized.
In addition, output impedance just increases in scan signal line raising and lowering, therefore in the present embodiment, rise and under
The equal rust of waveform is dropped, but can only rise or scan letter in scan signal line according to used panel construction, output impedance
Just increase when number line declines, but remain increased level, unless the cut-off of output grid is electric after scan signal line declines
It is interior for a period of time in another display defect that such as crosstalk occurs with high impedance when pressing Vgl.
For above-described embodiment, to scan signal line drive circuit（Gate drivers）Traditional structure in the addition of and be used for
Control the raising and lowering speed of scanning signal（Slope）Conversion rate control component SC situation be illustrated.However,
In this case it is necessary to conversion rate control component SC is additionally provided in gate drivers, and can not be directly using biography
The cheap gate drivers of system.Therefore, this is uneconomic.
In an embodiment of the present invention, using traditional cheap gate drivers.Said below with reference to Figure 10 and Figure 11
The fact that bright.
Traditional gate drivers are as reference chart 2 is explained above.As shown in Fig. 2 arrangement is as follows：Grid is provided
Conducting voltage Vgh and grid cut-off voltage Vgl, and electric conduction will be scanned successively in response to clock signal clk, gate drivers
Pressure Vgh is output to scan signal line 105, i.e., in a scan period（TH）Middle selection a line, at the same the above-mentioned scan period it
The voltage Vgl of the off state for making TFT reach each scan signal line 105 is exported afterwards.On the other hand, in the present embodiment
In, circuit as shown in Figure 10, it exports the voltage Vgh as scan signal line drive circuit.
Signal voltage Vdd is applied to a switch SW1 terminal.Signal voltage Vdd is that have and Vgh identical voltages
The DC voltage of level, it is sufficient to make TFT reach conducting state.Switch SW1 another terminal and resistor Rcnt one end with
And capacitor Ccnt terminal connection.Resistor Rcnt another terminal is by switching SW2 ground connection.According to by anti-phase
The signal Stc that device INV is provided（Referring to Figure 11）To perform switch SW2 ON/OFF control.The letter generated by unshowned control unit
Number Stc is synchronous with during each scanning, and is also used for switching SW1 ON/OFF control.Signal Stc is arranged to and clock signal
（CLK）It is synchronous, as shown in Figure 10.For example, can be by using monophonic multivibrator（It is not shown）To produce.
On switching SW1 and SW2 on/off operation, when signal Stc is in high level, switch SW1 is closed, and this
In switch SW2 due to being applied with low level voltage by phase inverter INV to disconnect.On the other hand, when signal Stc is in low level
（Discharge control signal）When, switch SW1 disconnects, and switchs SW2 here due to being applied to high level voltage by phase inverter INV
And close.In brief, in the arrangement shown, as shown in Figure 10, it is high level activation component to switch SW1 and SW2.
The output signal VD1a as caused by foregoing circuit is sent to the scan signal line drive circuit 300 shown in Fig. 2
Input VD1.Signal Stc is to be used for control gate raising and lowering（Scanning signal rise and fall）The timing signal of time,
As shown in figure 11, itself and each scan period（TH）It is synchronous.
According to said structure, when signal Stc is in high level, switch SW1 disconnects, and switch SW2 disconnects, output signal
VD1a as level Vgh voltage output to scanning input terminal VD1 signal-line driving circuits 300.On the other hand, signal is worked as
When Stc is in low level, switch SW1 is disconnected, and Simultaneous Switching SW2 is closed, and the electric charge being stored in capacitor Ccnt passes through
Resistor Rcnt is discharged, and thus, voltage level is gradually reduced.As a result, output signal VD1a has waveform as shown in Figure 5.
By sending output signal VD1a caused by circuit as shown in Figure 12（Referring to Figure 10）Driven to scan signal line
The input terminal VD1 of circuit 300, the waveform of scan signal line decline can be produced, that is, waveform VG as shown in Figure 4（j）.It is logical
Cross and change signal Stc low-level period to adjust the ramping time of waveform, and by changing resistor Rcnt resistance and electricity
Container Ccnt electric capacity carrys out the tuned slope Vslope so that the time constant of circuit is adjusted.Therefore, it can be directed to and to drive
Each display panel optimize.
Figure 13 and Figure 14 shows output waveform VG (j-1), the VG according to the scan signal line drive circuit of the present embodiment
And VG (j+1), scan signal line waveform Vg (j)（1, j）Near the input side of scan signal line, scan signal line waveform Vg
（N, j）Near the other end of scan signal line, also, each pixel potential Vd（1, j）And Vd（N, j）Before scan signal line
Near end.In the output waveform VG of scan signal line drive circuit（j）In, from scanning voltage Vgh to the upper of Non-scanning mode voltage Vgl
Liter and the slope that decline is to be represented by rate of change SxF and SxE（Gradient）Rise and fall, it is the change of time per unit
Amount, as shown in figure 13.
In the present embodiment, it is as shown in figure 13 in the rise and fall of activating control scanning signal, and by suitable
Locality sets rate of change SxF and SxE to realize the control of rise and fall.
Specifically, waveform voltage caused by gate drivers is to include rising to the non-perpendicular of high level by low level
The acclivitous sloping portion of mode, the horizontal component of high level is maintained, and dropped to by high level low level non-perpendicular
The sloping portion that mode tilts down.In order to reach this purpose, it is necessary to by suitably setting rate of change SxF and SxE, scanning letter
The rate of change SxF1 and the ascending wave near the other end of scan signal line of rising waveform near the input side of number line
The rate of change SxFN scan signal lines of shape become of substantially equal, the change of the falling waveform near the input side of scan signal line
Rate SxE1 and the rate of change SxEN scan signal lines of the rising waveform near the other end of scan signal line become basic phase
Deng without being influenceed by the parasitic signal delay transmission characteristic of scan signal line, such as scan signal line waveform Vg（1, j）And Vg
（N, j）（See Figure 13 and Figure 14）.Similar, this can equally make the pixel caused by parasitic capacitance Cgd in scan signal line
The level deviation that current potential Vd occurs becomes substantially uniform on whole display plane.
In order that the rate of change SxF1 and SxFN of rising waveform are substantially identical, and make the rate of change SxE1 of falling waveform
Be substantially identical with SxEN, without being influenceed by its position in scan line, can be based on signal delay transmission characteristic come
Carry out the control of rise and fall.The slope that control by this way makes it possible to scanning signal is any in scan line
Position is all of substantially equal, so that the level shift of pixel electrode is of substantially equal.
Based on signal delay transmission characteristic rather than it is above-mentioned rise or fall control, can the grid voltage based on TFT-
Drain current characteristics control the raising and lowering slope of scanning signal.In TFT, the voltage in application threshold voltage ranges
To its grid conducting voltage when, the drain electrode depending on the TFT of grid voltage（Conducting resistance）Electric current linearly changes.In other words
Say, TFT is not in the starting state of binary condition, but reaches middle starting state（Wherein drain current is according to grid
Voltage changes in an analogue form）.
In the present embodiment, the raising and lowering slope of scanning signal can be controlled so that when TFT is in above-mentioned linear change
The state of change（Middle on-state）When slope be affected.Because such control causes the raising and lowering of scanning signal
Become to tilt, at the same TFT also according to voltage-current characteristic from conducting state linear displacement to off-state, it is possible to certainly
Ground, each level deviation from pixel potential caused by parasitic capacitance will can be made to reduce really.
It is more optional, scanning signal can be controlled with grid voltage-drain current characteristics based on TFT signal delay transmission
Caused waveform voltage includes rising to the acclivitous sloping portion of non-perpendicular fashion of high level by low level, maintains
The horizontal component of high level, and the sloping portion that low level non-perpendicular fashion tilts down is dropped to by high level.This
In the case of, it can make the waveform near the input of scan signal line and near terminal will not by scan signal line parasitics
The influence of possessed signal delay propagation characteristic, and as production that is roughly the same, and reducing pixel potential Vd level displacement
It is raw.In this manner, it can make the waveform near the input of scan signal line and near terminal will not be by scan signal line
The influence of signal delay propagation characteristic possessed by parasitics ground, and as level that is roughly the same, and reducing pixel potential Vd
The generation of displacement, realize the display device bad without the display such as image retention is printed off.As a result, the level deviation of pixel potential is made substantially
It is equal to each other, and reduces each level deviation.
In addition, the voltage level VT shown in Figure 14 is the threshold voltage of the TFT shown in Figure 13, and due to scanning signal from
During scanning voltage Vgh drops to threshold V T, TFT keeps starting state, so hardly occurring within the above-mentioned time
The level deviation as caused by parasitic capacitance Cgd.On the other hand, due to making TFT cause the scanning signal line skew of off state
（VT-Vgl）Influenceed by parasitic capacitance Cgd, level deviation occurs.
Due to meeting VT-Vgl in the present embodiment<Vgh-Vgl, it can not only eliminate by the parasitism on whole display plane
The difference of level deviation caused by electric capacity, and each level deviation as caused by parasitic capacitance Cgd can be reduced.
Here, by prior art scan signal line drive circuit side scan signal line end near pixel post
Level deviation caused by raw electric capacity Cgd and pixel potential Vd is Vd（1）, in the electricity that the pixel of the other end of prior art occurs
Flat skew is Vd（N）In the case of, and then make pixel potential Vd level deviation this implementation near the end of scan signal line
The side of the scan signal line drive circuit of example is Vdx（1）, and what the pixel potential Vd of its other end in the present embodiment occurred
Level deviation is Vdx（N）.In this case, because the rate of change SxF1 of rising waveform, SxFN are substantially identical, and due to
Due to the rate of change SxE1 of rising waveform, SxEN is substantially identical, without being passed by the parasitic signal delay of said scanning signals line
The influence of defeated characteristic, therefore the level deviation that the pixel potential Vd as caused by parasitic capacitance Cgd occurs is on whole display plane
Become substantially uniform, and meet following relation（See Fig. 2 and Figure 15）：
Vdx(1)=Vdx(N)<Vd(N)<Vd(1)
Therefore, the counter potential VCOM of opposite electrode conventional scheme is biased by application so that from level caused by parasitic capacitance
Skew is tentatively reduced, and can provide a kind of display device with relatively low bias level, less flicker and display defect, example
Such as, aging afterimage is reduced, and there is less power consumption.
Figure 15 and Figure 16 shows output waveform VG (j-1), the VG according to the scan signal line drive circuit of the present embodiment
And VG (j+1), scan signal line waveform Vg (j)（1, j）Near the input side of scan signal line, scan signal line waveform Vg
（N, j）Near the other end of scan signal line, also, each pixel potential Vd（1, j）And Vd（N, j）Before scan signal line
Near end.In the output waveform VG of scan signal line drive circuit（j）In, from scanning voltage Vgh to the upper of Non-scanning mode voltage Vgl
Liter and the slope that decline is to be represented by rate of change SxF and SxE（Gradient）Rise and fall, it is the change of time per unit
Amount, as shown in figure 15.
In the present embodiment, it is as shown in figure 15 in the rise and fall of activating control scanning signal, and by suitable
Locality sets rate of change SxF and SxE to realize the control of rise and fall.
Specifically, waveform voltage caused by gate drivers is to be risen to by low level with the parabolical curvature of convex
High level, then including dropping to the sloping portion that low level non-perpendicular fashion tilts down by high level.In order to reach this mesh
, it is necessary to by suitably setting rate of change SxF and SxE, the change of the rising waveform near the input side of scan signal line
Rate SxF1 and the rate of change SxFN scan signal lines of the rising waveform near the other end of scan signal line become basic phase
Deng, scan signal line input side near falling waveform rate of change SxE1 and near the other end of scan signal line
The rate of change SxEN scan signal lines of rising waveform become of substantially equal, without being passed by the parasitic signal delay of scan signal line
The influence of defeated characteristic, such as scan signal line waveform Vg（1, j）And Vg（N, j）（See Figure 15 and Figure 16）.Similar, this equally can be with
The level deviation that the pixel potential Vd caused by parasitic capacitance Cgd in scan signal line occurs becomes on whole display plane
Obtain substantially uniform.
In order that the rate of change SxF1 and SxFN of rising waveform are substantially identical, and make the rate of change SxE1 of falling waveform
Be substantially identical with SxEN, without being influenceed by its position in scan line, can be based on signal delay transmission characteristic come
Carry out the control of rise and fall.The slope that control by this way makes it possible to scanning signal is any in scan line
Position is all of substantially equal, so that the level shift of pixel electrode is of substantially equal.
Based on signal delay transmission characteristic rather than it is above-mentioned rise or fall control, can the grid voltage based on TFT-
Drain current characteristics control the raising and lowering slope of scanning signal.In TFT, the voltage in application threshold voltage ranges
To its grid conducting voltage when, the drain electrode depending on the TFT of grid voltage（Conducting resistance）Electric current linearly changes.In other words
Say, TFT is not in the starting state of binary condition, but reaches middle starting state（Wherein drain current is according to grid
Voltage changes in an analogue form）.
In the present embodiment, the raising and lowering slope of scanning signal can be controlled so that when TFT is in above-mentioned linear change
The state of change（Middle on-state）When slope be affected.Because such control causes the raising and lowering of scanning signal
Become to tilt, at the same TFT also according to voltage-current characteristic from conducting state linear displacement to off-state, it is possible to certainly
Ground, each level deviation from pixel potential caused by parasitic capacitance will can be made to reduce really.
It is more optional, in a scan period, control the rate of change SxF of rising waveform to change over time, for example, by big
To small, then control the rate of change SxE of falling waveform to only occur in scanning signal and drop to low level non-perpendicular side from high level
In the sloping portion that formula tilts down, the waveform near the input of scan signal line and near terminal can be made not swept
The influence of signal delay propagation characteristic possessed by signal wire parasitics ground is retouched, and turns into roughly the same, and reduces pixel potential
The generation of Vd level displacement, realize the display device bad without the display such as image retention is printed off.As a result, make the level of pixel potential inclined
Move substantially mutually equal, and reduce each level deviation.
In addition, the voltage level VT shown in Figure 16 is the threshold voltage of the TFT shown in Figure 15, and due to scanning signal from
During scanning voltage Vgh drops to threshold V T, TFT keeps starting state, so hardly occurring within the above-mentioned time
The level deviation as caused by parasitic capacitance Cgd.On the other hand, due to making TFT cause the scanning signal line skew of off state
（VT-Vgl）Influenceed by parasitic capacitance Cgd, level deviation occurs.
Due to meeting VT-Vgl in the present embodiment<Vgh-Vgl, it can not only eliminate by the parasitism on whole display plane
The difference of level deviation caused by electric capacity, and each level deviation as caused by parasitic capacitance Cgd can be reduced.
Here, by prior art scan signal line drive circuit side scan signal line end near pixel post
Level deviation caused by raw electric capacity Cgd and pixel potential Vd is Vd（1）, in the electricity that the pixel of the other end of prior art occurs
Flat skew is Vd（N）In the case of, and then make pixel potential Vd level deviation this implementation near the end of scan signal line
The side of the scan signal line drive circuit of example is Vdx（1）, and what the pixel potential Vd of its other end in the present embodiment occurred
Level deviation is Vdx（N）.In this case, because the rate of change SxF1 of rising waveform, SxFN are substantially identical, and due to
Due to the rate of change SxE1 of rising waveform, SxEN is substantially identical, without being passed by the parasitic signal delay of said scanning signals line
The influence of defeated characteristic, therefore the level deviation that the pixel potential Vd as caused by parasitic capacitance Cgd occurs is on whole display plane
Become substantially uniform, and meet following relation（See Figure 15 and Figure 16）：
Vdx(1)=Vdx(N)<Vd(N)<Vd(1)
Therefore, the counter potential VCOM of opposite electrode conventional scheme is biased by application so that from level caused by parasitic capacitance
Skew is tentatively reduced, and can provide a kind of display device with relatively low bias level, less flicker and display defect, example
Such as, aging afterimage is reduced, and there is less power consumption.
Figure 17 and Figure 18 shows output waveform VG (j-1), the VG according to the scan signal line drive circuit of the present embodiment
And VG (j+1), scan signal line waveform Vg (j)（1, j）Near the input side of scan signal line, scan signal line waveform Vg
（N, j）Near the other end of scan signal line, also, each pixel potential Vd（1, j）And Vd（N, j）Before scan signal line
Near end.In the output waveform VG of scan signal line drive circuit（j）In, from scanning voltage Vgh to the upper of Non-scanning mode voltage Vgl
Liter and the slope that decline is to be represented by rate of change SxF and SxE（Gradient）Rise and fall, it is the change of time per unit
Amount, as shown in figure 17.
In the present embodiment, it is as shown in figure 17 in the rise and fall of activating control scanning signal, and by suitable
Locality sets rate of change SxF and SxE to realize the control of rise and fall.Specifically, waveform caused by gate drivers
Voltage is the acclivitous sloping portion of non-perpendicular fashion for including being risen to high level by low level, then by high level with matrix
Parabolical curvature drops to low level (as shown in figure 17).In order to reach this purpose, it is necessary to by suitably setting rate of change
SxF and SxE, scan signal line input side near rising waveform rate of change SxF1 and in the another of scan signal line
The rate of change SxFN scan signal lines of rising waveform near end become of substantially equal, near the input side of scan signal line
The rate of change SxE1 of falling waveform and the rate of change SxEN scanning letters of the rising waveform near the other end of scan signal line
Number line becomes of substantially equal, without being influenceed by the parasitic signal delay transmission characteristic of scan signal line, such as scan signal line ripple
Shape Vg（1, j）And Vg（N, j）（See Figure 17 and Figure 18）.Similar, this can equally make due to parasitic capacitance in scan signal line
The level deviation that pixel potential Vd caused by Cgd occurs becomes substantially uniform on whole display plane.
In order that the rate of change SxF1 and SxFN of rising waveform are substantially identical, and make the rate of change SxE1 of falling waveform
Be substantially identical with SxEN, without being influenceed by its position in scan line, can be based on signal delay transmission characteristic come
Carry out the control of rise and fall.The slope that control by this way makes it possible to scanning signal is any in scan line
Position is all of substantially equal, so that the level shift of pixel electrode is of substantially equal.
Based on signal delay transmission characteristic rather than it is above-mentioned rise or fall control, can the grid voltage based on TFT-
Drain current characteristics control the raising and lowering slope of scanning signal.In TFT, the voltage in application threshold voltage ranges
To its grid conducting voltage when, the drain electrode depending on the TFT of grid voltage（Conducting resistance）Electric current linearly changes.In other words
Say, TFT is not in the starting state of binary condition, but reaches middle starting state（Wherein drain current is according to grid
Voltage changes in an analogue form）.
In the present embodiment, it can control the raising and lowering slope of scanning signal so that when TFT is in above-mentioned linear change
State（Middle on-state）When slope be affected.Because such control causes the raising and lowering of scanning signal to become
Must tilt, at the same TFT also according to voltage-current characteristic from conducting state linear displacement to off-state, it is possible to for certain,
Each level deviation from pixel potential caused by parasitic capacitance will can be made to reduce really.It is more optional, in a scan period
In, control rising waveform rate of change SxF only occur in scanning signal from low level rise to the non-perpendicular fashion of high level to
In upper inclined sloping portion, then the rate of change SxE of falling waveform is controlled to change over time, for example, it is ascending, therefore,
The end of one scan period, it can produce and low level scanning signal is dropped to the parabolical curvature of matrix by high level.Such as
This, can be such that the waveform near the input of scan signal line and near terminal is not had by scan signal line parasitics
The influence of some signal delay propagation characteristics, and as generation that is roughly the same, and reducing pixel potential Vd level displacement, it is real
The now display device bad without the display such as image retention is printed off.As a result, make the level deviation of pixel potential substantially mutually equal, and
Reduce each level deviation.
In addition, the voltage level VT shown in Figure 18 is the threshold voltage of the TFT shown in Figure 17, and due to scanning signal from
During scanning voltage Vgh drops to threshold V T, TFT keeps starting state, so hardly occurring within the above-mentioned time
The level deviation as caused by parasitic capacitance Cgd.On the other hand, due to making TFT cause the scanning signal line skew of off state
（VT-Vgl）Influenceed by parasitic capacitance Cgd, level deviation occurs.Due to meeting VT-Vgl in the present embodiment<Vgh-
Vgl, can not only eliminate the difference of the level deviation as caused by the parasitic capacitance on whole display plane, and can reduce by
Each level deviation caused by parasitic capacitance Cgd.In this case, because the rate of change SxF1, SxFN of rising waveform are basic
It is upper equal, and due to the rate of change SxE1 due to rising waveform, SxEN is substantially identical, without parasitic by said scanning signals line
Signal delay transmission characteristic influence, therefore as caused by parasitic capacitance Cgd pixel potential Vd occur level deviation whole
Become substantially uniform on individual display plane, and meet following relation（See Fig. 2 and Figure 15）：
Vdx(1)=Vdx(N)<Vd(N)<Vd(1)
Therefore, the counter potential VCOM of opposite electrode conventional scheme is biased by application so that from level caused by parasitic capacitance
Skew is tentatively reduced, and can provide a kind of display device with relatively low bias level, less flicker and display defect, example
Such as, aging afterimage is reduced, and there is less power consumption.
Figure 19 and Figure 20 shows output waveform VG (j-1), the VG according to the scan signal line drive circuit of the present embodiment
And VG (j+1), scan signal line waveform Vg (j)（1, j）Near the input side of scan signal line, scan signal line waveform Vg
（N, j）Near the other end of scan signal line, also, each pixel potential Vd（1, j）And Vd（N, j）Before scan signal line
Near end.In the output waveform VG of scan signal line drive circuit（j）In, from scanning voltage Vgh to the upper of Non-scanning mode voltage Vgl
Liter and the slope that decline is to be represented by rate of change SxF and SxE（Gradient）Rise and fall, it is the change of time per unit
Amount, as shown in figure 19.
In the present embodiment, it is as shown in figure 19 in the rise and fall of activating control scanning signal, and by suitable
Locality sets rate of change SxF and SxE to realize the control of rise and fall.Specifically, waveform caused by gate drivers
Voltage is to rise to high level by low level with the parabolical curvature of convex, then is declined by high level with the parabolical curvature of matrix
To low level.In order to reach this purpose, it is necessary to by suitably setting rate of change SxF and SxE, the input side of scan signal line
The rate of change SxF1 of the neighbouring rising waveform and rate of change SxFN of the rising waveform near the other end of scan signal line
Scan signal line becomes of substantially equal, the rate of change SxE1 of the falling waveform near the input side of scan signal line and is sweeping
Retouching the rate of change SxEN scan signal lines of the rising waveform near the other end of signal wire becomes of substantially equal, without being believed by scanning
The influence of the parasitic signal delay transmission characteristic of number line, such as scan signal line waveform Vg（1, j）And Vg（N, j）（See Figure 19 and figure
20）.Similar, this can equally make the level that the pixel potential Vd caused by parasitic capacitance Cgd in scan signal line occurs
Skew becomes substantially uniform on whole display plane.
In order that the rate of change SxF1 and SxFN of rising waveform are substantially identical, and make the rate of change SxE1 of falling waveform
Be substantially identical with SxEN, without being influenceed by its position in scan line, can be based on signal delay transmission characteristic come
Carry out the control of rise and fall.The slope that control by this way makes it possible to scanning signal is any in scan line
Position is all of substantially equal, so that the level shift of pixel electrode is of substantially equal.Based on signal delay transmission characteristic rather than on
That states rises or falls control, can based on TFT grid voltage-drain current characteristics come control the rising of scanning signal and under
Drop angle rate.In TFT, when the conducting voltage of the voltage in application threshold voltage ranges to its grid, depending on grid voltage
TFT drain electrode（Conducting resistance）Electric current linearly changes.In other words, TFT is not in the starting state of binary condition,
But reach middle starting state（Wherein drain current changes in an analogue form according to grid voltage）.
In the present embodiment, the raising and lowering slope of scanning signal can be controlled so that when TFT is in above-mentioned linear change
The state of change（Middle on-state）When slope be affected.Because such control causes the raising and lowering of scanning signal
Become to tilt, at the same TFT also according to voltage-current characteristic from conducting state linear displacement to off-state, it is possible to certainly
Ground, each level deviation from pixel potential caused by parasitic capacitance will can be made to reduce really.It is more optional, a scanning week
It is interim, control the rate of change SxF of rising waveform to change over time, for example, it is descending, therefore before a scan period
It end, can produce by rising to the scanning signal of high level by low level with the parabolical curvature of convex, then control falling waveform
Rate of change SxE is changed over time, for example, ascending, therefore, in the end of a scan period, can produce by high level with
The parabolical curvature of matrix drops to low level scanning signal.In this way, it can more reduce the production of pixel potential Vd level displacement
It is raw, and can make waveform of the input nearby and near terminal positioned at scan signal line will not by scan signal line parasitics institute
The influence for the signal delay propagation characteristic having, and turn into roughly the same, and the generation of pixel potential Vd level displacement is reduced,
Realize the display device bad without the display such as image retention is printed off.As a result, make the level deviation of pixel potential substantially mutually equal, and
And reduce each level deviation.
In addition, the voltage level VT shown in Figure 18 is the threshold voltage of the TFT shown in Fig. 1, and due to scanning signal from
During scanning voltage Vgh drops to threshold V T, TFT keeps starting state, so hardly occurring within the above-mentioned time
The level deviation as caused by parasitic capacitance Cgd.On the other hand, due to making TFT cause the scanning signal line skew of off state
（VT-Vgl）Influenceed by parasitic capacitance Cgd, level deviation occurs.Due to meeting VT-Vgl in the present embodiment<Vgh-
Vgl, can not only eliminate the difference of the level deviation as caused by the parasitic capacitance on whole display plane, and can reduce by
Each level deviation caused by parasitic capacitance Cgd.
In this case, because the rate of change SxF1 of rising waveform, SxFN are substantially identical, and due to due to ascending wave
The rate of change SxE1 of shape, SxEN is substantially identical, without the shadow by the parasitic signal delay transmission characteristic of said scanning signals line
Ring, therefore the level deviation that the pixel potential Vd as caused by parasitic capacitance Cgd occurs becomes substantially equal on whole display plane
It is even, and meet following relation（See Fig. 2 and Figure 15）：
Vdx(1)=Vdx(N)<Vd(N)<Vd(1)
Therefore, the counter potential VCOM of opposite electrode conventional scheme is biased by application so that from level caused by parasitic capacitance
Skew is tentatively reduced, and can provide a kind of display device with relatively low bias level, less flicker and display defect, example
Such as, aging afterimage is reduced, and there is less power consumption.
In display device of the present invention, scan signal line drive circuit controls the decline of scan signal line so that is showing
Make pixel potential that substantially uniform level deviation occur on face, level deviation is caused by the electric capacity colonized on scan signal line.
The falling waveform of scanning signal is changed with the rate of change Sx of the variable quantity of time per unit, and it is desirable that rate of change Sx is set as
Rate of change Sx1 near the input side end of scan signal line, as scan signal line waveform Vg（1, j）And Vg（N, j）Equally, its
Rate of change SxN near the other end is of substantially equal, is not influenceed by signal delay transmission characteristic possessed by scan signal line）.
In the respective embodiments described above, the display device that so forms, suitable for liquid crystal display, OLED display devices,
QLED display devices, curved-surface display equipment or other display equipment, are not limited thereto.
It should be noted that in the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, in some embodiment
The part being not described in, it may refer to the associated description of other embodiment.
Described above, the only embodiment of the application, but the protection domain of the application is not limited thereto is any
Those familiar with the art can readily occur in various equivalent modifications or replace in the technical scope that the application discloses
Change, these modifications or substitutions should all cover within the protection domain of the application.Therefore, the protection domain of the application should be with right
It is required that protection domain be defined.
Claims (5)
- A kind of 1. display device, it is characterised in that including：It is arranged to rectangular multiple pixels；For providing the image signal line of data-signal to the multiple pixel；The scan signal line intersected with described image signal wire；Gate driving circuit, scanning signal is output to the scan signal line by it, and exports scanning signal to drive described sweep Retouch signal wire；AndControl circuit, it controls the gate driving circuit by control signal, and the control signal has with voltage change Cycle waveform voltage；Wherein, at the beginning of at least one of which scan period of the scanning signal, the voltage of the scanning signal rises, and High level is tilted to from low level with the parabolical curvature of convex, it is described at the end of during at least one of which scans The voltage of scanning signal declines, and tilts to the low level from the high level with the parabolical curvature of matrix.
- 2. display device as claimed in claim 1, it is characterised in that the control circuit is by the way that the control signal is inputted To the gate driving circuit, to cause the part change of the change between the high level of the scanning signal and low level.
- 3. display device according to claim 1, it is characterised in that the gate driving circuit is included by multiple triggers The shift register portion of composition, and selecting switch are cascaded, is switched on or off individually according to the output of the multiple trigger.
- 4. display device according to claim 1, it is characterised in that the display device also includes being connected to the grid The capacitor of the input of driver, voltage source is connected to the input of the gate drivers by first switch, and resistance leads to Cross second switch and be parallel-connected to the capacitor.
- A kind of 5. display device, it is characterised in that including：It is arranged to rectangular multiple pixels；For providing the image signal line of data-signal to the multiple pixel；The scan signal line intersected with described image signal wire；Gate driving circuit, scanning signal is output to the scan signal line by it, and exports scanning signal to drive described sweep Retouch signal wire；Control circuit, it controls the gate driving circuit by control signal, and the control signal has with voltage change Cycle waveform voltage；AndCapacitor, the input of the gate drivers is connected to, wherein voltage source is connected to the grid by first switch and driven The input of dynamic device, and resistance is parallel-connected to the capacitor by second switch,At the beginning of at least one of which scan period of wherein described scanning signal, the voltage of the scanning signal rises, and High level is tilted to from low level with the parabolical curvature of convex, it is described at the end of during at least one of which scans The voltage of scanning signal declines, and tilts to the low level from the high level with the parabolical curvature of matrix,Wherein described control circuit by the control signal by being input to the gate driving circuit, to cause the scanning letter Number high level and low level between change a part change,Wherein described gate driving circuit includes the shift register portion being made up of the cascade of multiple triggers, and selection is opened Close, be switched on or off individually according to the output of the multiple trigger.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711023283.1A CN107689222A (en) | 2017-10-26 | 2017-10-26 | A kind of display device |
| PCT/CN2017/116244 WO2019080302A1 (en) | 2017-10-26 | 2017-12-14 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711023283.1A CN107689222A (en) | 2017-10-26 | 2017-10-26 | A kind of display device |
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| Publication Number | Publication Date |
|---|---|
| CN107689222A true CN107689222A (en) | 2018-02-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711023283.1A Withdrawn CN107689222A (en) | 2017-10-26 | 2017-10-26 | A kind of display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107689222A (en) |
| WO (1) | WO2019080302A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019080300A1 (en) * | 2017-10-26 | 2019-05-02 | 惠科股份有限公司 | Display device |
| WO2019080301A1 (en) * | 2017-10-26 | 2019-05-02 | 惠科股份有限公司 | Display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100194726A1 (en) * | 1998-03-27 | 2010-08-05 | Sharp Kabushiki Kaisha | Display device and display method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3135810B2 (en) * | 1995-01-31 | 2001-02-19 | シャープ株式会社 | Image display device |
| CN100407281C (en) * | 2005-01-31 | 2008-07-30 | 友达光电股份有限公司 | Grid driving method and circuit of liquid crystal displaying device |
| US20100289785A1 (en) * | 2006-09-15 | 2010-11-18 | Daiichi Sawabe | Display apparatus |
| CN107545872A (en) * | 2017-10-26 | 2018-01-05 | 惠科股份有限公司 | A kind of display device |
| CN107545873A (en) * | 2017-10-26 | 2018-01-05 | 惠科股份有限公司 | A kind of display device |
| CN107665688A (en) * | 2017-10-26 | 2018-02-06 | 惠科股份有限公司 | A kind of display device |
| CN107665687A (en) * | 2017-10-26 | 2018-02-06 | 惠科股份有限公司 | A kind of display device |
-
2017
- 2017-10-26 CN CN201711023283.1A patent/CN107689222A/en not_active Withdrawn
- 2017-12-14 WO PCT/CN2017/116244 patent/WO2019080302A1/en active Application Filing
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100194726A1 (en) * | 1998-03-27 | 2010-08-05 | Sharp Kabushiki Kaisha | Display device and display method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019080300A1 (en) * | 2017-10-26 | 2019-05-02 | 惠科股份有限公司 | Display device |
| WO2019080301A1 (en) * | 2017-10-26 | 2019-05-02 | 惠科股份有限公司 | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2019080302A1 (en) | 2019-05-02 |
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Application publication date: 20180213 |