CN107679262A - A kind of modeling method of MOS device its periphery dead resistance - Google Patents
A kind of modeling method of MOS device its periphery dead resistance Download PDFInfo
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Abstract
The invention discloses a kind of modeling method of MOS device its periphery dead resistance, comprise the following steps：S01 establishes the ring-shaped resistor test structure corresponding with MOS device, and S02 establishes termination resistance subtest structure, and S03 establishes the scalable model of termination resistance, and S04 tests the resistance R of ring-type resistance test structuretot2, the girth of inner loop and external rings is brought into the scalable model of termination resistance and draws R1And R2Resistance, so as to Rsti=Rtot2‑R1‑R2, R under different layout sizes can be obtained by converting the domain factorstiValue, analyze RstiWith the variation relation of above-mentioned layout size, the scalable model of MOS device its periphery dead resistance is established.A kind of modeling method of MOS device its periphery dead resistance provided by the invention, the dead resistance of MOS device active area periphery introducing can be directly characterized by this method, and the scalable model for modeling the MOS device its periphery dead resistance drawn is applied to the laying out pattern mode under different situations.
Description
Technical field
The present invention relates to test of semiconductor integrated circuit and modeling field, and in particular to a kind of MOS device its periphery is posted
The modeling method of raw resistance.
Background technology
In field of radio frequency integrated circuits, the resistance substrate of MOS device largely determines the output characteristics of device,
Its influence be can not ignore in RF IC design.The resistance substrate of MOS device can be divided into using device active region as boundary
Two large divisions, a part are the substrate portions that active area is below MOS device source-drain area and channel region, and another part has for device
Source region periphery, i.e., the substrate portions below STI (shallow-trench isolation) region between substrate exit and exit and active area.
For the latter, the calculating of its substrate portions resistance is relevant with the domain factor and arrangement mode of device, wherein, domain
The factor and layout design size are corresponding.During the active radio frequency organs weight of prior art, using two-port test structure
Sign is modeled to it, but in two-port test structure, the part is difficult by accurate definition and characterized, so as to lead
The precision deficiency of resistance substrate model is caused, and then influences the result of circuit design.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of modeling method of MOS device its periphery dead resistance,
The dead resistance of MOS device active area periphery introducing can be directly characterized by this method, and models the MOS device lining drawn
The scalable model of bottom periphery dead resistance is applied to the laying out pattern mode under different situations.
To achieve these goals, the present invention adopts the following technical scheme that：A kind of MOS device its periphery dead resistance
Modeling method, comprise the following steps：
S01, foundation and the corresponding ring-shaped resistor test structure of MOS device, wherein, MOS device includes being located at the device
The active area at center, the grid being evenly distributed in active area, body end ring-type outside active area and grid draw and
Substrate trap outside the extraction of body end ring-type, the width that the body end ring-type is drawn be rw, substrate trap be used for MOS device and
External world's isolation；
The ring-shaped resistor test structure is followed successively by inner loop, external rings and annular substrate trap outward from interior, inner loop and
Outside ring width is rw, and the region and inner loop interior zone between inner loop and external rings are sti region, the electricity of inner loop
Hinder for R2, the resistance of external rings is R1, the resistance of sti region is Rsti, substrate trap be used for by ring-shaped resistor test structure with it is extraneous
Isolation；
The layout design size of ring-shaped resistor test structure is identical with the layout design size of MOS device；
S02, termination resistance subtest structure is established, wherein, the termination resistance subtest structure includes being located at square
Rectangle termination on two relative edges of shape and the substrate trap on the outside of termination；The width of two terminations is rw, termination institute
The a length of w of rectangular edges, distance is l between two terminations, the part of two terminations and the ring-shaped resistor test structure
Middle inner loop is identical with the part of external rings, and the layout type of both contact holes is identical；
S03, establish the scalable model of termination resistance：Fixed w, change l value, it is auxiliary to measure a series of corresponding termination resistance
Help the resistance value R of test structuretot1, with Rtot1For ordinate, l/w is abscissa, draws curve, and the curve is cut ordinate
All-in resistance away from as two terminations, both sides termination resistance is identical in the resistance subtest structure of termination, termination resistance RendTo cut
Away from half, choose multigroup w, obtain R in the resistance subtest structure of terminationendThe scalable model of termination resistance between w；
S04, the scalable model for establishing MOS device its periphery dead resistance：Test the electricity of ring-type resistance test structure
Hinder Rtot2, by the w in the girth of the inner loop and external rings substitution scalable model of termination resistance, draw R2And R1Resistance, Rsti
=Rtot2-R1-R2, R under different layout sizes can be obtained by converting the domain factorstiValue, analyze RstiWith above-mentioned layout size
Variation relation, establish the scalable model of MOS device its periphery dead resistance.
Further, the scalable model of termination resistance subtest structure is in the step S03
Wherein, RconFor the resistance of a contact hole, NconThe number of the contact hole introduced for the termination of one end, a are that termination resistance can be stretched
Contracting model parameter.
Further, the girth of inner loop selects the average value of its lateral perimeter and inner side girth in the step S04.
Further, the girth of external rings selects the average value of its lateral perimeter and inner side girth in the step S04.
Further, it is rectangle that the MOS device active area is drawn with body end ring-type, and accordingly, ring-shaped resistor is surveyed
It is rectangle to try inner loop and external rings in structure.
Further, inner loop and external rings are injection active area and contact hole structure in the ring-shaped resistor test structure
Into rectangular ring structure.
Further, injected in the ring-shaped resistor test structure in inner loop and external rings active area injection type and
The injection type of MOS device active area is opposite.
Further, the MOS device domain factor be MOS device active area width waa, length laa, active area with
Body end ring-type draws the distance s on four direction1、s2、s3And s4, accordingly, domain in the ring-shaped resistor test structure
The factor includes the width waa of inner loop, length laa, inner loop and distance s of the external rings on four direction1、s2、s3And s4。
Further, the scalable model of MOS device its periphery dead resistance is in the step S04：
Wherein, asti, a1, a2, a3, b1, b2, b3, b4For the mould of the scalable model of MOS device its periphery dead resistance
Shape parameter, above-mentioned model parameter is determined by the Rsti values being fitted under the different domain factors.
Beneficial effects of the present invention are：Can directly it be characterized using the ring-shaped resistor test structure in modeling method of the present invention
The dead resistance that MOS device active area periphery introduces, do not filled so as to avoid conventional MOS test structure and the partial information is characterized
The problem of dividing.And modeling method of the present invention establishes the scalable of MOS device its periphery dead resistance based on the domain factor
Model, the laying out pattern mode for making model be applicable under different situations.
Brief description of the drawings
Fig. 1 is a kind of modeling method flow chart of MOS device its periphery dead resistance of the present invention.
Fig. 2 is NMOS domains part hierarchical structure schematic diagram.
Fig. 3 is NMOS cross-sectional views.
Fig. 4 is ring resistance test structure domain part level schematic diagram.
Fig. 5 is ring resistance test structure diagrammatic cross-section.
Fig. 6 is termination resistance subtest structure domain part level schematic diagram.
Fig. 7 is the domain part level schematic diagram of different connected modes.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the accompanying drawings to the specific reality of the present invention
The mode of applying is described in further detail.
It should be noted that in following embodiments, when embodiments of the present invention are described in detail, in order to clear
Ground represents the structure of the present invention in order to illustrate, spy does not draw to the structure in accompanying drawing according to general proportion, and has carried out part
Method, deformation and simplified processing, therefore, should avoid being explained in this, as limitation of the invention.
MOS device is divided into PMOS device and nmos device, and the following drawings and explanation are by taking nmos device as an example, when device is
During PMIOS, used modeling method is similar with nmos device, it is only necessary to changes type and inner loop and the outside of substrate trap
The injection type of active area in ring, do not make tired state herein.
As shown in figure 1, a kind of modeling method of MOS device its periphery dead resistance, comprises the following steps：
S01, foundation and the corresponding ring-shaped resistor test structure of MOS device, wherein, MOS device includes being located at the device
The active area at center, the grid being evenly distributed in active area, body end ring-type outside active area and grid draw and
Substrate trap outside the extraction of body end ring-type, the width that body end ring-type is drawn are rw, and substrate trap NW is for by MOS device and outside
Boundary keeps apart；Ring-shaped resistor test structure is followed successively by inner loop, external rings and annular substrate trap outward from interior, inner loop and outer
Portion's ring width is rw, and the region and inner loop interior zone between inner loop and external rings are sti region, the resistance of inner loop
For R2, the resistance of external rings is R1, the resistance of sti region is Rsti, substrate trap be used for by ring-shaped resistor test structure with it is extraneous every
Leave and；The convertible domain factor of ring-shaped resistor test structure is identical with MOS device.
Wherein, the MOS device shape that active area and body end ring-type are drawn in actual production can be variously-shaped, and
Shape in its corresponding ring-shaped resistor test structure in the shape and MOS device of inner loop and external rings is consistent, for
MOS device of different shapes, the domain factor corresponding to setting, can establish corresponding its periphery dead resistance to it can
Flexible model.
In order to more clearly illustrate beneficial effects of the present invention, active area and body end ring-type in MOS device is used to draw at this
The shape gone out is rectangle to describe the present invention in detail, when active area and body end ring-type draw when being shaped as other shapes, build
The scalable model method of vertical ring-shaped resistor test structure and its periphery dead resistance is similar, no longer carries out in the present invention
Illustrate one by one.
As shown in Fig. 2 Fig. 4, it is rectangle that nmos device active area is drawn with body end ring-type, and accordingly, ring-shaped resistor is surveyed
It is rectangle to try inner loop and external rings in structure, also, inner loop and external rings are injection in ring-shaped resistor test structure
The rectangular ring structure that active area and contact hole are formed.Inner loop and external rings are drawn out to upper strata metal by contact hole respectively
Pole, tested.The width that body end ring-type is drawn in MOS device is rw, corresponding, inner loop in ring-shaped resistor test structure
Width with external rings is also rw, but in ion implantation process is carried out to inner loop and external rings, the width meeting of injection region
More than rw.When it is rectangle that MOS device active area and body end ring-type, which are drawn, its corresponding domain factor is the width of active area
Waa, length laa, it is s1, s2, s3 and s4 that active area draws the distance on four direction with body end ring-type.Corresponding, ring
The domain factor includes the width waa of inner loop in shape resistance test structure, and length laa, inner loop is with external rings in four direction
On distance s1, s2, s3 and s4.As shown in figure 4, the resistance of inner loop is R in ring-shaped resistor test structure2, the electricity of external rings
Hinder for R1, the resistance of sti region is Rsti.Inner loop inner ring are drawn out to upper strata metal pole, external rings by contact hole
Outer ring are drawn out to upper strata metal pole by contact hole.
As shown in Figure 3 and Figure 5, the resistance of nmos device by active area and body end ring-type draw between the STI resistance that introduces
RstiAnd the ring-shaped resistor R that body end ring-type is drawn1Composition, the resistance of ring-shaped resistor test structure is by internal loop resistance R2, it is outside
Loop resistance R1Annular STI resistance composition between inner loop and external rings.
S02, termination resistance subtest structure is established, wherein, termination resistance subtest structure includes being located at rectangle two
Rectangle termination on individual relative edge and the substrate trap on the outside of termination；The width of two terminations is rw, where termination
The a length of w of rectangular edges, distance is l between two terminations.
As shown in fig. 6, be termination resistance subtest structure domain part level schematic diagram, the part of two terminations
It is identical with the part of external rings with inner loop in ring-shaped resistor test structure.
S03, as shown in fig. 6, establishing the scalable model of termination resistance：Fixed w, change l value, measure a series of corresponding
The resistance value R of termination resistance subtest structuretot1, with Rtot1For ordinate, l/w is abscissa, draws curve, and the curve exists
The intercept of ordinate is the all-in resistance of two terminations, and both sides termination resistance is identical in the resistance subtest structure of termination, intercept
Half be introduce termination resistance Rend, choose multigroup w, you can obtain termination resistance subtest structure in Rend and w
Between the scalable model of termination resistance.
When establishing the scalable model of termination resistance, it can be simulated using equation below：Wherein,
RendFor the half of intercept, RconFor the resistance of a contact hole, NconThe number of the contact hole introduced for the termination of one end, a are end
The head scalable model parameter of resistance.
S04, the scalable model for establishing nmos device its periphery dead resistance：Test the electricity of ring-type resistance test structure
Hinder Rtot2, w that the girth of inner loop and external rings is brought into the scalable model of termination resistance draws R2And R1Resistance, Rsti
=Rtot2-R1-R2, R under different layout sizes can be obtained by converting the domain factorstiValue, analyze RstiWith above-mentioned layout size
Variation relation, establish the scalable model of nmos device its periphery dead resistance.
Wherein, the girth of inner loop selects it from its lateral perimeter and the average value of inner side girth, the girth of external rings
The average value of lateral perimeter and inner side girth.It is rectangle to be drawn when nmos device active area and body end ring-type, and ring-shaped resistor is surveyed
, can be by the girth of inner loop center line, R when inner loop and external rings are rectangle in examination structurecon、NconBring above-mentioned termination into
In the scalable model of resistance, the R that is calculatedendThe resistance for being equivalent to inner loop is R2, by the girth of external rings center line,
Rcon、NconBring into the above-mentioned scalable model of termination resistance, the R being calculatedendThe resistance for being equivalent to external rings is R1, test
The resistance R of ring-shaped resistor test structuretot2, you can the resistance for obtaining sti region is Rsti=Rtot2-R1-R2。
The domain factor is converted, the R under the different domain factors can be obtainedsti, analyze RstiBetween the above-mentioned domain factor
Variation relation, propose the model of fit of its periphery dead resistance.In the present invention, the domain factor is area width waa, length
Laa, it is s that active area draws the distance on four direction with body end ring-type1、s2、s3And s4.Nmos device its periphery is parasitic
The scalable model of resistance is：
Wherein, asti, a1, a2, a3, b1, b2, b3, b4For the mould of the scalable model of MOS device its periphery dead resistance
Shape parameter, above-mentioned model parameter is determined by the Rsti values being fitted under the different domain factors.
Modeling method of the present invention establishes the scalable model of MOS device its periphery dead resistance based on the domain factor,
The laying out pattern mode being applicable under different situations, as shown in fig. 7, the laying out pattern of different connected modes can use this hair
Bright model carries out the calculating of peripheral dead resistance.
The preferred embodiments of the present invention are the foregoing is only, the embodiment is not intended to limit the patent protection of the present invention
Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made, similarly should be included in this
In the protection domain of invention appended claims.
Claims (9)
1. a kind of modeling method of MOS device its periphery dead resistance, it is characterised in that comprise the following steps：
S01, foundation and the corresponding ring-shaped resistor test structure of MOS device, wherein, MOS device includes being located at the device center
Active area, the grid that is evenly distributed in active area, body end ring-type outside active area and grid draw and be located at
Substrate trap outside the extraction of body end ring-type, the width that the body end ring-type is drawn are rw, and substrate trap is used for MOS device and the external world
Isolation；
The ring-shaped resistor test structure is followed successively by inner loop, external rings and annular substrate trap, inner loop and outside outward from interior
Ring width is rw, and the region and inner loop interior zone between inner loop and external rings are sti region, and the resistance of inner loop is
R2, the resistance of external rings is R1, the resistance of sti region is Rsti, substrate trap is for ring-shaped resistor test structure to be isolated from the outside；
The layout design size of ring-shaped resistor test structure is identical with the layout design size of MOS device；
S02, termination resistance subtest structure is established, wherein, the termination resistance subtest structure includes being located at rectangle two
Rectangle termination on individual relative edge and the substrate trap on the outside of termination；The width of two terminations is rw, where termination
The a length of w of rectangular edges, distance is l between two terminations, in the part of two terminations and the ring-shaped resistor test structure in
Portion's ring is identical with the part of external rings, and the layout type of both contact holes is identical；
S03, establish the scalable model of termination resistance：Fixed w, change l value, measure a series of corresponding termination resistance auxiliary and survey
Try the resistance value R of structuretot1, with Rtot1For ordinate, l/w is abscissa, draws curve, and the curve is in the intercept of ordinate
For the all-in resistance of two terminations, both sides termination resistance is identical in the resistance subtest structure of termination, termination resistance RendFor intercept
Half, multigroup w is chosen, obtain R in the resistance subtest structure of terminationendThe scalable model of termination resistance between w；
S04, the scalable model for establishing MOS device its periphery dead resistance：Test the resistance of ring-type resistance test structure
Rtot2, w that the girth of inner loop and external rings is brought into the scalable model of termination resistance draws R2And R1Resistance, Rsti=
Rtot2-R1-R2, R under different layout sizes can be obtained from the domain factor that layout design size is corresponding by convertingstiValue, point
Analyse RstiWith the variation relation of above-mentioned layout size, the scalable model of MOS device its periphery dead resistance is established.
A kind of 2. modeling method of MOS device its periphery dead resistance according to claim 1, it is characterised in that institute
The scalable model for stating resistance subtest structure in termination in step S03 isWherein, RconFor a contact
The resistance in hole, NconThe number of the contact hole introduced for the termination of one end, a is the scalable model parameter of termination resistance.
A kind of 3. modeling method of MOS device its periphery dead resistance according to claim 1, it is characterised in that institute
The girth of inner loop in step S04 is stated from its lateral perimeter and the average value of inner side girth.
A kind of 4. modeling method of MOS device its periphery dead resistance according to claim 1, it is characterised in that institute
The girth of external rings in step S04 is stated from its lateral perimeter and the average value of inner side girth.
A kind of 5. modeling method of MOS device its periphery dead resistance according to claim 1, it is characterised in that institute
It is rectangle to state MOS device active area and drawn with body end ring-type, accordingly, inner loop and outside in ring-shaped resistor test structure
Ring is rectangle.
A kind of 6. modeling method of MOS device its periphery dead resistance according to claim 5, it is characterised in that institute
It is to inject the rectangular ring structure that active area and contact hole are formed to state inner loop and external rings in ring-shaped resistor test structure.
A kind of 7. modeling method of MOS device its periphery dead resistance according to claim 6, it is characterised in that institute
State in ring-shaped resistor test structure and inject the injection type of active area and the injection of MOS device active area in inner loop and external rings
Type is opposite.
A kind of 8. modeling method of MOS device its periphery dead resistance according to claim 5, it is characterised in that institute
The width waa that the MOS device domain factor is MOS device active area, length laa are stated, active area is drawn at four with body end ring-type
Distance s on direction1、s2、s3And s4, accordingly, the domain factor includes the width of inner loop in the ring-shaped resistor test structure
Spend waa, length laa, inner loop and distance s of the external rings on four direction1、s2、s3And s4。
A kind of 9. modeling method of MOS device its periphery dead resistance according to claim 8, it is characterised in that institute
The scalable model for stating MOS device its periphery dead resistance in step S04 is：
Wherein, asti, a1, a2, a3, b1, b2, b3, b4For the model ginseng of the scalable model of MOS device its periphery dead resistance
Number, above-mentioned model parameter is determined by the Rsti values being fitted under the different domain factors.
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