CN107666323B - Switch button scanning circuit and electric equipment - Google Patents

Switch button scanning circuit and electric equipment Download PDF

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Publication number
CN107666323B
CN107666323B CN201610604766.XA CN201610604766A CN107666323B CN 107666323 B CN107666323 B CN 107666323B CN 201610604766 A CN201610604766 A CN 201610604766A CN 107666323 B CN107666323 B CN 107666323B
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interface
switch key
level signal
microprocessor
detected
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CN107666323A (en
Inventor
冯江平
王志锋
区达理
刘志才
马志海
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Foshan Shunde Midea Electrical Heating Appliances Manufacturing Co Ltd
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Foshan Shunde Midea Electrical Heating Appliances Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/20—Dynamic coding, i.e. by key scanning

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

The invention provides a switch key scanning circuit and electric equipment, the switch key scanning circuit includes: the microprocessor is provided with a first interface and a second interface; the microprocessor is used for: after entering a key scanning mode, the first interface and the second interface are pull-up inputs; detecting whether the first interface or the second interface is a low level signal; when the first interface is detected to be a low-level signal, determining that a first switch key of a switch key scanning circuit is in a pressed closed state; when the second interface is detected to be a low-level signal, determining that a second switch key of the switch key scanning circuit is in a pressed closed state; and performing cyclic scanning on the switch key scanning circuit according to a preset period. By the technical scheme, the interface occupation of the microprocessor is reduced.

Description

Switch button scanning circuit and electric equipment
Technical Field
The invention relates to the technical field of circuit design, in particular to a switch key scanning circuit and electric equipment.
Background
In the related art, in a switch key scanning array of an m×m (M is a positive integer) array, M interfaces of a microprocessor need to be called as array detection interfaces, in addition, M interfaces of the microprocessor need to be called as row array detection interfaces, when a row array detection interface M1 (0 < M1 < M) and a row array detection interface M2 (0 < M2 < M) simultaneously detect a pressing signal, a key for determining the (M1, M2) position in the array is pressed, that is, 2M interfaces need to be called to realize M 2 And a large amount of MCU resources are occupied by detecting the keys.
Therefore, how to design a new switch key scanning circuit to reduce the occupation of the MCU interface is a current urgent problem to be solved.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art or related art.
Therefore, an object of the present invention is to provide a switch key scanning circuit.
Another object of the present invention is to propose a powered device.
To solve at least one of the above problems, an embodiment of a first aspect of the present invention provides a switch key scanning circuit, including: the microprocessor is provided with a first interface and a second interface; the first end of the first resistor is connected to the output end of the direct-current power supply, the second end of the first resistor is connected to the first end of the first switch key, the second end of the first switch key is grounded, and the second end of the first resistor is connected to the first interface; the first end of the second resistor is connected to the output end of the direct-current power supply, the second end of the second resistor is connected to the first end of the second switch key, the second end of the second switch key is grounded, and the second end of the second resistor is connected to the second interface; the first end of the third switch key is connected to the first interface, the second end of the third switch key is connected to the cathode of the first diode, and the anode of the first diode is connected to the first end of the second switch key; the first end of the fourth switch key is connected to the second interface, the second end of the fourth switch key is connected to the cathode of the second diode, and the anode of the second diode is connected to the first end of the first switch key; the microprocessor is also configured to: after entering a key scanning mode, switching a first interface and a second interface of a key scanning circuit; the microprocessor is also configured to: detecting whether the first interface or the second interface is a low level signal; the microprocessor is also configured to: when the first interface is detected to be a low-level signal, determining that a first switch key of a switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: when the second interface is detected to be a low-level signal, determining that a second switch key of the switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: and performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit.
In this technical scheme, through above-mentioned switch button scanning circuit, button array is 2×2, only occupies two interfaces of microprocessor and can realize the button location, and wherein, first resistance and second resistance are pull-up resistance, for example, when setting up first interface for pull-up input, first interface is equivalent to concatenating a great resistance in microprocessor inboard, and first interface is high level normality for detect the incoming signal and be high level or low level, in order to avoid the interface unsettled, improved circuit reliability.
Preferably, the microprocessor is further configured to: setting a first interface of the switch key circuit as output 0, and setting a second interface as pull-up input; the microprocessor is also configured to: detecting whether the second interface is a low level signal; the microprocessor is also configured to: when the second interface is detected to be a low-level signal, the first interface is set to be a pull-up input, and when the second interface is detected to be a high-level signal, the third switch key of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor is further configured to: setting a second interface of the switch key circuit as output 0, and setting a first interface as pull-up input; the microprocessor is also configured to: detecting whether the first interface is a low level signal; the microprocessor is also configured to: and when the first interface is detected to be a low-level signal, setting the second interface as a pull-up input, and when the first interface is detected to be a high-level signal, determining that a fourth switch key of the switch key scanning circuit is in a pressed state.
An embodiment of a second aspect of the present invention provides a switch key scanning circuit, including: the microprocessor is provided with a first interface, a second interface and a third interface; the first end of the first resistor is connected to the output end of the direct-current power supply, the second end of the first resistor is connected to the first end of the first switch key, the second end of the first switch key is grounded, and the second end of the first resistor is connected to the first interface; the first end of the second resistor is connected to the output end of the direct-current power supply, the second end of the second resistor is connected to the first end of the second switch key, the second end of the second switch key is grounded, and the second end of the second resistor is connected to the second interface; the first end of the third resistor is connected to the output end of the direct-current power supply, the second end of the third resistor is connected to the first end of the third switch key, the second end of the third switch key is grounded, and the second end of the third resistor is connected to the third interface; the first end of the fourth switch key is connected to the first interface, the second end of the fourth switch key is connected to the cathode of the first diode, and the anode of the first diode is connected to the first end of the third switch key; a fifth switch key, a first end of which is connected to the second interface, and a second end of which is connected to the cathode of the first diode; the first end of the sixth switch key is connected to the first interface, the second end of the sixth switch key is connected to the cathode of the second diode, and the anode of the second diode is connected to the first end of the second switch key; a seventh switch key, the first end of which is connected to the third interface, and the second end of which is connected to the cathode of the second diode; the first end of the eighth switch key is connected to the second interface, the second end of the eighth switch key is connected to the cathode of the third diode, and the anode of the third diode is connected to the first end of the first switch key; a ninth switch button, a first end of the ninth switch button is connected to the third interface, and a second end of the ninth switch button is connected to the cathode of the third diode; the microprocessor is also configured to: after entering a key scanning mode, setting a first interface, a second interface and a third interface of a switch key scanning circuit as pull-up inputs; the microprocessor is also configured to: detecting whether any one of the first interface, the second interface and the third interface is a low-level signal; the microprocessor is also configured to: when the first interface is detected to be a low-level signal, determining that a first switch key of a switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: when the second interface is detected to be a low-level signal, determining that a second switch key of the switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: when the third interface is detected to be a low-level signal, determining that a third switch key of the switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: and performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit.
In this technical scheme, through above-mentioned switch button scanning circuit, button array is 3×4, only occupies three interfaces of microprocessor and can realize the button location, and wherein, first resistance, second resistance and third resistance are pull-up resistance, for example, when setting up first interface for pull-up input, first interface is equivalent to concatenating a great resistance in microprocessor inboard, and first interface is high level normality for detect the incoming signal for high level or low level, so as to avoid the interface unsettled, improved circuit reliability.
Preferably, the microprocessor is further configured to: setting a first interface of the switch key circuit as output 0, and setting a second interface as pull-up input; the microprocessor is also configured to: detecting whether the second interface or the third interface is a low level signal; the microprocessor is also configured to: setting the first interface as pull-up input when the second interface is detected to be a low-level signal, and determining a sixth switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal; the microprocessor is also configured to: when the third interface is detected to be a low-level signal, the first interface is set as a pull-up input, and when the third interface is detected to be a high-level signal, a fourth switch key of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor is further configured to: setting a second interface of the switch key circuit as output 0, and setting the first interface and a third interface as pull-up inputs; the microprocessor is also configured to: detecting whether the first interface or the third interface is a low level signal; the microprocessor is also configured to: setting the second interface as a pull-up input when the first interface is detected to be a low-level signal, and determining an eighth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal; the microprocessor is also configured to: and when the third interface is detected to be a low-level signal, setting the second interface as a pull-up input, and when the third interface is detected to be a high-level signal, determining that a fifth switch key of the switch key scanning circuit is in a pressed state.
Preferably, the microprocessor is further configured to: setting a third interface of the switch key circuit as output 0, and setting the first interface and the second interface as pull-up inputs; the microprocessor is also configured to: detecting whether the first interface or the second interface is a low level signal; the microprocessor is also configured to: setting a third interface as a pull-up input when the first interface is detected to be a low-level signal, and determining a ninth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal; the microprocessor is also configured to: and when the second interface is detected to be a low-level signal, setting the third interface as a pull-up input, and when the second interface is detected to be a high-level signal, determining that a seventh switch key of the switch key scanning circuit is in a pressed state.
An embodiment of a third aspect of the present invention provides a switch key scanning circuit, including: the microprocessor is provided with a first interface, a second interface, a third interface and a fourth interface; the first end of the first resistor is connected to the output end of the direct-current power supply, the second end of the first resistor is connected to the first end of the first switch key, the second end of the first switch key is grounded, and the second end of the first resistor is connected to the first interface; the first end of the second resistor is connected to the output end of the direct-current power supply, the second end of the second resistor is connected to the first end of the second switch key, the second end of the second switch key is grounded, and the second end of the second resistor is connected to the second interface; the first end of the third resistor is connected to the output end of the direct-current power supply, the second end of the third resistor is connected to the first end of the third switch key, the second end of the third switch key is grounded, and the second end of the third resistor is connected to the third interface; the first end of the fourth resistor is connected to the output end of the direct-current power supply, the second end of the fourth resistor is connected to the first end of the fourth switch key, the second end of the fourth switch key is grounded, and the second end of the fourth resistor is connected to the fourth interface; the first end of the fifth switch key is connected to the first interface, the second end of the fifth switch key is connected to the cathode of the first diode, and the anode of the first diode is connected to the first end of the fourth switch key; the first end of the sixth switch key is connected to the second interface, and the second end of the sixth switch key is connected to the cathode of the first diode; a seventh switch key, the first end of which is connected to the third interface, and the second end of which is connected to the cathode of the first diode; the first end of the eighth switch key is connected to the first interface, the second end of the eighth switch key is connected to the cathode of the second diode, and the anode of the second diode is connected to the first end of the third switch key; a ninth switch button, a first end of the ninth switch button is connected to the second interface, and a second end of the ninth switch button is connected to the cathode of the second diode; a tenth switch key, the first end of the tenth switch key is connected to the fourth interface, and the second end of the tenth switch key is connected to the cathode of the second diode; an eleventh switch key and a third diode, wherein a first end of the eleventh switch key is connected to the first interface, a second end of the eleventh switch key is connected to a cathode of the third diode, and an anode of the third diode is connected to a first end of the second switch key; a twelfth switch key, the first end of which is connected to the third interface, and the second end of which is connected to the cathode of the third diode; a thirteenth switch key, the first end of the thirteenth switch key is connected to the fourth interface, and the second end of the fifth switch key is connected to the cathode of the third diode; a fourteenth switch button and a fourth diode, wherein the first end of the fourteenth switch button is connected to the second interface, the second end of the fourteenth switch button is connected to the cathode of the fourth diode, and the anode of the fourth diode is connected to the first end of the first switch button; a fifteenth switch button, a first end of the fifteenth switch button is connected to the third interface, and a second end of the fifteenth switch button is connected to the cathode of the fourth diode; a sixteenth switch key, a first end of which is connected to the fourth interface, and a second end of which is connected to the cathode of the fourth diode; the microprocessor is also configured to: after the key scanning mode is entered, the first interface, the second interface, the third interface and the fourth interface of the switch key scanning circuit are all set as pull-up inputs; the microprocessor is also configured to: detecting whether any one of the first interface, the second interface, the third interface and the fourth interface is a low-level signal; the microprocessor is also configured to: when the first interface is detected to be a low-level signal, determining that a first switch key of a switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: when the second interface is detected to be a low-level signal, determining that a second switch key of the switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: when the third interface is detected to be a low-level signal, determining that a third switch key of the switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: when the fourth interface is detected to be a low-level signal, determining that a fourth switch key of the switch key scanning circuit is in a pressed closed state; the microprocessor is also configured to: and performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit.
In this technical scheme, through above-mentioned switch button scanning circuit, button array is 4×5, only occupies four interfaces of microprocessor and can realize the button location, and wherein, first resistance and second resistance are pull-up resistance, for example, when setting up first interface for pull-up input, first interface is equivalent to concatenating a great resistance in microprocessor inboard, and first interface is high level normality for detect the incoming signal and be high level or low level, in order to avoid the interface unsettled, has promoted circuit reliability.
Preferably, the microprocessor is further configured to: setting a first interface of the switch key circuit as output 0, and setting a second interface, a third interface and a fourth interface as pull-up inputs; the microprocessor is also configured to: detecting whether any one of the second interface, the third interface and the fourth interface is a low-level signal; the microprocessor is also configured to: setting the first interface as a pull-up input when the second interface is detected to be a low-level signal, and determining an eleventh switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal; the microprocessor is also configured to: setting the first interface as a pull-up input when the third interface is detected as a low-level signal, and determining an eighth switch key of the switch key scanning circuit to be in a pressed state when the third interface is detected as a high-level signal; the microprocessor is also configured to: when the fourth interface is detected to be a low-level signal, the first interface is set to be a pull-up input, and when the fourth interface is detected to be a high-level signal, a fifth switch key of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor is further configured to: setting a second interface of the switch key circuit as output 0, and setting a first interface, a third interface and a fourth interface as pull-up inputs; the microprocessor is also configured to: detecting whether any one of the first interface, the third interface and the fourth interface is a low-level signal; the microprocessor is also configured to: setting the second interface as a pull-up input when the first interface is detected to be a low-level signal, and determining a fourteenth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal; the microprocessor is also configured to: setting the second interface as a pull-up input when the third interface is detected to be a low-level signal, and determining a ninth switch key of the switch key scanning circuit to be in a pressed state when the third interface is detected to be a high-level signal; the microprocessor is also configured to: and when the fourth interface is detected to be a low-level signal, setting the second interface as a pull-up input, and when the fourth interface is detected to be a high-level signal, determining that a sixth switch key of the switch key scanning circuit is in a pressed state.
Preferably, the microprocessor is further configured to: setting a third interface of the switch key circuit as output 0, and setting a first interface, a second interface and a fourth interface as pull-up inputs; the microprocessor is also configured to: detecting whether any one of the first interface, the second interface and the fourth interface is a low-level signal; the microprocessor is also configured to: setting the first interface as a pull-up input when the first interface is detected to be a low-level signal, and determining a fifteenth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal; the microprocessor is also configured to: setting the first interface as a pull-up input when the second interface is detected to be a low-level signal, and determining a twelfth switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal; the microprocessor is also configured to: when the fourth interface is detected to be a low-level signal, the first interface is set to be a pull-up input, and when the fourth interface is detected to be a high-level signal, a seventh switch key of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor is further configured to: setting a fourth interface of the switch key circuit as output 0, and setting the first interface, the second interface and the third interface as pull-up inputs; the microprocessor is also configured to: detecting whether any one of the first interface, the second interface and the third interface is a low-level signal; the microprocessor is also configured to: setting a fourth interface as a pull-up input when the first interface is detected to be a low-level signal, and determining a sixteenth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal; the microprocessor is also configured to: setting the first interface as a pull-up input when the second interface is detected to be a low-level signal, and determining a thirteenth switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal; the microprocessor is also configured to: when the third interface is detected to be a low-level signal, the first interface is set as a pull-up input, and when the third interface is detected to be a high-level signal, a tenth switch key of the switch key scanning circuit is determined to be in a pressed state.
Preferably, whether any switch key of the switch key scanning circuit is in a pressed closed state is detected; when any switch key is detected to be in a pressed closed state, the key identifier is set to be 1, and the switch key scanning circuit is controlled not to enter a key scanning mode; when no switch key is detected to be in a pressed closed state, the key identifier is set to 0, and the switch key scanning circuit is controlled to enter a key scanning mode.
An embodiment of a fourth aspect of the present invention provides an electric device, including a switch key scanning circuit according to any one of the foregoing technical solutions.
The electric equipment can be household appliances with switch keys, such as electric rice cookers, electromagnetic ovens, pressure cookers, soymilk machines, electric kettles and the like.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 shows a schematic diagram of a switch key scan circuit according to one embodiment of the invention;
FIG. 2 shows a schematic diagram of a switch key scan circuit according to another embodiment of the invention;
FIG. 3 shows a schematic diagram of a switch key scan circuit according to yet another embodiment of the invention;
FIG. 4 is a flow chart of a scanning method of a switch key scanning circuit according to an embodiment of the invention;
FIG. 5 is a flow chart of a scanning method of a switch key scanning circuit according to another embodiment of the invention;
FIG. 6 is a flow chart of a scanning method of a switch key scanning circuit according to another embodiment of the application;
FIG. 7 is a flow chart of a scanning method of a switch key scanning circuit according to another embodiment of the application;
FIG. 8 is a flow chart of a scanning method of a switch key scanning circuit according to another embodiment of the application;
FIG. 9 is a flow chart of a scanning method of a switch key scanning circuit according to another embodiment of the application;
fig. 10 is a flowchart of a scanning method of the switch key scanning circuit according to another embodiment of the present application.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, without conflict, the embodiments of the present application and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, however, the present application may be practiced otherwise than as described herein, and therefore the scope of the present application is not limited to the specific embodiments disclosed below.
A switch key scan circuit and a powered device according to various embodiments of the present invention are described in detail below with reference to fig. 1-3.
Embodiment one:
fig. 1 shows a schematic diagram of a switch key scan circuit according to an embodiment of the invention.
As shown in fig. 1, a switch key scan circuit according to an embodiment of the present invention includes: the microprocessor MCU is provided with a first interface IO1 and a second interface IO2; the first resistor R1 and the first switch key K1 are connected, a first end of the first resistor R1 is connected to the output end of the direct-current power supply VCC, a second end of the first resistor R1 is connected to the first end of the first switch key K1, a second end of the first switch key K1 is grounded, and a second end of the first resistor R1 is connected to the first interface IO1; the first end of the second resistor R2 is connected to the output end of the direct-current power supply VCC, the second end of the second resistor R2 is connected to the first end of the second switch key K2, the second end of the second switch key K2 is grounded, and the second end of the second resistor R2 is connected to the second interface IO2; the first end of the third switch key K3 is connected to the first interface IO1, the second end of the third switch key K3 is connected to the cathode of the first diode D1, and the anode of the first diode D1 is connected to the first end of the second switch key K2; the first end of the fourth switch key K4 is connected to the second interface IO2, the second end of the fourth switch key K4 is connected to the cathode of the second diode D2, and the anode of the second diode D2 is connected to the first end of the first switch key K1; the microprocessor MCU is also used for: after entering a key scanning mode, switching a first interface IO1 and a second interface IO2 of a key scanning circuit; the microprocessor MCU is also used for: detecting whether the first interface IO1 or the second interface IO2 is a low-level signal; the microprocessor MCU is also used for: when the first interface IO1 is detected to be a low-level signal, determining that a first switch key K1 of a switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: when the second interface IO2 is detected to be a low-level signal, determining that a second switch key K2 of the switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: and performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit.
In this technical scheme, through above-mentioned switch button scanning circuit, button array is 2×2, only occupies two interfaces of microprocessor MCU and can realize the button location, wherein, first resistance R1 and second resistance R2 are pull-up resistance, for example, when setting up first interface IO1 for pull-up input, first interface IO1 is equivalent to concatenating a great resistance in microprocessor MCU inboard, first interface IO1 is high level normality for detect the incoming signal and be high level or low level, in order to avoid the interface unsettled, circuit reliability has been promoted.
Wherein the preset period is of the order of microseconds or nanoseconds, depending on the user's need for the scanning frequency.
Preferably, the microprocessor MCU is further configured to: setting a first interface IO1 of a switch key circuit as output 0, and setting a second interface IO2 as pull-up input; the microprocessor MCU is also used for: detecting whether the second interface IO2 is a low level signal or not; the microprocessor MCU is also used for: when the second interface IO2 is detected to be a low-level signal, the first interface IO1 is set to be a pull-up input, and when the second interface IO2 is detected to be a high-level signal, the third switch key K3 of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor MCU is further configured to: setting a second interface IO2 of the switch key circuit as output 0, and setting a first interface IO1 as pull-up input; the microprocessor MCU is also used for: detecting whether the first interface IO1 is a low level signal or not; the microprocessor MCU is also used for: when the first interface IO1 is detected to be a low-level signal, the second interface IO2 is set to be a pull-up input, and when the first interface IO1 is detected to be a high-level signal, the fourth switch key K4 of the switch key scanning circuit is determined to be in a pressed state.
Embodiment two:
fig. 2 shows a schematic diagram of a switch key scan circuit according to another embodiment of the invention.
As shown in fig. 2, a switch key scan circuit according to another embodiment of the present invention includes: the microprocessor MCU is provided with a first interface IO1, a second interface IO2 and a third interface IO3; the first resistor R1 and the first switch key K1 are connected, a first end of the first resistor R1 is connected to the output end of the direct-current power supply VCC, a second end of the first resistor R1 is connected to the first end of the first switch key K1, a second end of the first switch key K1 is grounded, and a second end of the first resistor R1 is connected to the first interface IO1; the first end of the second resistor R2 is connected to the output end of the direct-current power supply VCC, the second end of the second resistor R2 is connected to the first end of the second switch key K2, the second end of the second switch key K2 is grounded, and the second end of the second resistor R2 is connected to the second interface IO2; the first end of the third resistor R3 is connected to the output end of the direct-current power supply VCC, the second end of the third resistor R3 is connected to the first end of the third switch key K3, the second end of the third switch key K3 is grounded, and the second end of the third resistor R3 is connected to the third interface IO3; the first end of the fourth switch key K4 is connected to the first interface IO1, the second end of the fourth switch key K4 is connected to the cathode of the first diode D1, and the anode of the first diode D1 is connected to the first end of the third switch key K3; the first end of the fifth switch key K5 is connected to the second interface IO2, and the second end of the fifth switch key K5 is connected to the cathode of the first diode D1; a sixth switch key K6 and a second diode D2, wherein a first end of the sixth switch key K6 is connected to the first interface IO1, a second end of the sixth switch key K6 is connected to a cathode of the second diode D2, and an anode of the second diode D2 is connected to a first end of the second switch key K2; a seventh switch key K7, wherein a first end of the seventh switch key K7 is connected to the third interface IO3, and a second end of the seventh switch key K7 is connected to the cathode of the second diode D2; an eighth switch key K8 and a third diode D3, wherein a first end of the eighth switch key K8 is connected to the second interface IO2, a second end of the eighth switch key K8 is connected to a cathode of the third diode D3, and an anode of the third diode D3 is connected to a first end of the first switch key K1; a ninth switch key K9, a first end of the ninth switch key K9 is connected to the third interface IO3, and a second end of the ninth switch key K9 is connected to the cathode of the third diode D3; the microprocessor MCU is also used for: after entering a key scanning mode, setting a first interface IO1, a second interface IO2 and a third interface IO3 of a switch key scanning circuit as pull-up inputs; the microprocessor MCU is also used for: detecting whether any one of the first interface IO1, the second interface IO2 and the third interface IO3 is a low-level signal; the microprocessor MCU is also used for: when the first interface IO1 is detected to be a low-level signal, determining that a first switch key K1 of a switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: when the second interface IO2 is detected to be a low-level signal, determining that a second switch key K2 of the switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: when the third interface IO3 is detected to be a low-level signal, determining that a third switch key K3 of the switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: and performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit.
In this technical scheme, through above-mentioned switch button scanning circuit, button array is 3×4, only occupies microprocessor MCU's three interface and can realize the button location, wherein, first resistance R1, second resistance R2 and third resistance R3 are pull-up resistance, for example, when setting up first interface IO1 for pull-up input, first interface IO1 is equivalent to concatenating a great resistance in microprocessor MCU inboard, first interface IO1 is high level normality for detect the input signal and be high level or low level, in order to avoid the interface unsettled, circuit reliability has been promoted.
Preferably, the microprocessor MCU is further configured to: setting a first interface IO1 of a switch key circuit as output 0, and setting a second interface IO2 as pull-up input; the microprocessor MCU is also used for: detecting whether the second interface IO2 or the third interface IO3 is a low-level signal or not; the microprocessor MCU is also used for: setting the first interface IO1 as a pull-up input when the second interface IO2 is detected to be a low-level signal, and determining a sixth switch key K6 of the switch key scanning circuit to be in a pressed state when the second interface IO2 is detected to be a high-level signal; the microprocessor MCU is also used for: when the third interface IO3 is detected to be a low-level signal, the first interface IO1 is set as a pull-up input, and when the third interface IO3 is detected to be a high-level signal, the fourth switch key K4 of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor MCU is further configured to: setting a second interface IO2 of the switch key circuit as output 0, and setting a first interface IO1 and a third interface IO3 as pull-up inputs; the microprocessor MCU is also used for: detecting whether the first interface IO1 or the third interface IO3 is a low-level signal or not; the microprocessor MCU is also used for: setting the second interface IO2 as a pull-up input when the first interface IO1 is detected to be a low-level signal, and determining an eighth switch key K8 of the switch key scanning circuit to be in a pressed state when the first interface IO1 is detected to be a high-level signal; the microprocessor MCU is also used for: when the third interface IO3 is detected to be a low-level signal, the second interface IO2 is set to be a pull-up input, and when the third interface IO3 is detected to be a high-level signal, the fifth switch key K5 of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor MCU is further configured to: setting a third interface IO3 of the switch key circuit as output 0, and setting a first interface IO1 and a second interface IO2 as pull-up inputs; the microprocessor MCU is also used for: detecting whether the first interface IO1 or the second interface IO2 is a low-level signal; the microprocessor MCU is also used for: setting a third interface IO3 as a pull-up input when the first interface IO1 is detected to be a low-level signal, and determining a ninth switch key K9 of the switch key scanning circuit to be in a pressed state when the first interface IO1 is detected to be a high-level signal; the microprocessor MCU is also used for: when the second interface IO2 is detected to be a low-level signal, the third interface IO3 is set to be a pull-up input, and when the second interface IO2 is detected to be a high-level signal, the seventh switch key K7 of the switch key scanning circuit is determined to be in a pressed state.
Embodiment III:
fig. 3 shows a schematic diagram of a switch key scan circuit according to yet another embodiment of the invention.
As shown in fig. 3, a switch key scan circuit according to still another embodiment of the present invention includes: the microprocessor MCU is provided with a first interface IO1, a second interface IO2, a third interface IO3 and a fourth interface; the first resistor R1 and the first switch key K1 are connected, a first end of the first resistor R1 is connected to the output end of the direct-current power supply VCC, a second end of the first resistor R1 is connected to the first end of the first switch key K1, a second end of the first switch key K1 is grounded, and a second end of the first resistor R1 is connected to the first interface IO1; the first end of the second resistor R2 is connected to the output end of the direct-current power supply VCC, the second end of the second resistor R2 is connected to the first end of the second switch key K2, the second end of the second switch key K2 is grounded, and the second end of the second resistor R2 is connected to the second interface IO2; the first end of the third resistor R3 is connected to the output end of the direct-current power supply VCC, the second end of the third resistor R3 is connected to the first end of the third switch key K3, the second end of the third switch key K3 is grounded, and the second end of the third resistor R3 is connected to the third interface IO3; the first end of the fourth resistor is connected to the output end of the direct-current power supply VCC, the second end of the fourth resistor is connected to the first end of the fourth switch key K4, the second end of the fourth switch key K4 is grounded, and the second end of the fourth resistor is connected to the fourth interface; the first end of the fifth switch key K5 is connected to the first interface IO1, the second end of the fifth switch key K5 is connected to the cathode of the first diode D1, and the anode of the first diode D1 is connected to the first end of the fourth switch key K4; the first end of the sixth switch key K6 is connected to the second interface IO2, and the second end of the sixth switch key K6 is connected to the cathode of the first diode D1; a seventh switch key K7, wherein a first end of the seventh switch key K7 is connected to the third interface IO3, and a second end of the fifth switch key K5 is connected to the cathode of the first diode D1; an eighth switch key K8 and a second diode D2, wherein a first end of the eighth switch key K8 is connected to the first interface IO1, a second end of the eighth switch key K8 is connected to a cathode of the second diode D2, and an anode of the second diode D2 is connected to a first end of the third switch key K3; a ninth switch key K9, a first end of the ninth switch key K9 is connected to the second interface IO2, and a second end of the ninth switch key K9 is connected to the cathode of the second diode D2; a tenth switch key K10, a first end of the tenth switch key K10 is connected to the fourth interface, and a second end of the tenth switch key K10 is connected to the cathode of the second diode D2; an eleventh switch key K11 and a third diode D3, wherein a first end of the eleventh switch key K11 is connected to the first interface IO1, a second end of the eleventh switch key K11 is connected to a cathode of the third diode D3, and an anode of the third diode D3 is connected to a first end of the second switch key K2; a twelfth switch key K12, wherein a first end of the twelfth switch key K12 is connected to the third interface IO3, and a second end of the twelfth switch key K12 is connected to the cathode of the third diode D3; a thirteenth switch key K13, a first end of the thirteenth switch key K13 is connected to the fourth interface, and a second end of the fifth switch key K5 is connected to the cathode of the third diode D3; a fourteenth switch key K14 and a fourth diode, the first end of the fourteenth switch key K14 is connected to the second interface IO2, the second end of the fourteenth switch key K14 is connected to the cathode of the fourth diode, and the anode of the fourth diode is connected to the first end of the first switch key K1; a fifteenth switch key K15, a first end of the fifteenth switch key K15 is connected to the third interface IO3, and a second end of the fifteenth switch key K15 is connected to the cathode of the fourth diode; a sixteenth switch key K16, wherein a first end of the sixteenth switch key K16 is connected to the fourth interface, and a second end of the sixteenth switch key K16 is connected to the cathode of the fourth diode; the microprocessor MCU is also used for: after the key scanning mode is entered, the first interface IO1, the second interface IO2, the third interface IO3 and the fourth interface of the switch key scanning circuit are all set as pull-up inputs; the microprocessor MCU is also used for: detecting whether any one of the first interface IO1, the second interface IO2, the third interface IO3 and the fourth interface is a low-level signal; the microprocessor MCU is also used for: when the first interface IO1 is detected to be a low-level signal, determining that a first switch key K1 of a switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: when the second interface IO2 is detected to be a low-level signal, determining that a second switch key K2 of the switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: when the third interface IO3 is detected to be a low-level signal, determining that a third switch key K3 of the switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: when the fourth interface is detected to be a low-level signal, determining that a fourth switch key K4 of the switch key scanning circuit is in a pressed closed state; the microprocessor MCU is also used for: and performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit.
In this technical scheme, through above-mentioned switch button scanning circuit, button array is 4×5, only occupies microprocessor MCU's four interfaces and can realize the button location, wherein, first resistance R1 and second resistance R2 are pull-up resistance, for example, when setting up first interface IO1 for pull-up input, first interface IO1 is equivalent to concatenating a great resistance in microprocessor MCU inboard, first interface IO1 is high level normality for detect the incoming signal and be high level or low level, in order to avoid the interface unsettled, circuit reliability has been promoted.
Preferably, the microprocessor MCU is further configured to: setting a first interface IO1 of a switch key circuit as output 0, and setting a second interface IO2, a third interface IO3 and a fourth interface as pull-up inputs; the microprocessor MCU is also used for: detecting whether any one of the second interface IO2, the third interface IO3 and the fourth interface is a low-level signal; the microprocessor MCU is also used for: setting the first interface IO1 as a pull-up input when the second interface IO2 is detected to be a low-level signal, and determining an eleventh switch key K11 of the switch key scanning circuit to be in a pressed state when the second interface IO2 is detected to be a high-level signal; the microprocessor MCU is also used for: setting the first interface IO1 as a pull-up input when the third interface IO3 is detected to be a low-level signal, and determining an eighth switch key K8 of the switch key scanning circuit to be in a pressed state when the third interface IO3 is detected to be a high-level signal; the microprocessor MCU is also used for: when the fourth interface is detected to be a low-level signal, the first interface IO1 is set as a pull-up input, and when the fourth interface is detected to be a high-level signal, the fifth switch key K5 of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor MCU is further configured to: setting a second interface IO2 of the switch key circuit as output 0, and setting a first interface IO1, a third interface IO3 and a fourth interface as pull-up inputs; the microprocessor MCU is also used for: detecting whether any one of the first interface IO1, the third interface IO3 and the fourth interface is a low-level signal; the microprocessor MCU is also used for: setting the second interface IO2 as a pull-up input when the first interface IO1 is detected to be a low-level signal, and determining a fourteenth switch key K14 of the switch key scanning circuit to be in a pressed state when the first interface IO1 is detected to be a high-level signal; the microprocessor MCU is also used for: setting the second interface IO2 as a pull-up input when the third interface IO3 is detected to be a low-level signal, and determining a ninth switch key K9 of the switch key scanning circuit to be in a pressed state when the third interface IO3 is detected to be a high-level signal; the microprocessor MCU is also used for: when the fourth interface is detected to be a low-level signal, the second interface IO2 is set as a pull-up input, and when the fourth interface is detected to be a high-level signal, a sixth switch key K6 of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor MCU is further configured to: setting a third interface IO3 of the switch key circuit as output 0, and setting a first interface IO1, a second interface IO2 and a fourth interface as pull-up inputs; the microprocessor MCU is also used for: detecting whether any one of the first interface IO1, the second interface IO2 and the fourth interface is a low-level signal; the microprocessor MCU is also used for: setting the first interface IO1 as a pull-up input when the first interface IO1 is detected to be a low-level signal, and determining a fifteenth switch key K15 of the switch key scanning circuit to be in a pressed state when the first interface IO1 is detected to be a high-level signal; the microprocessor MCU is also used for: setting the first interface IO1 as a pull-up input when the second interface IO2 is detected to be a low-level signal, and determining the twelfth switch key K12 of the switch key scanning circuit to be in a pressed state when the second interface IO2 is detected to be a high-level signal; the microprocessor MCU is also used for: when the fourth interface is detected to be a low-level signal, the first interface IO1 is set as a pull-up input, and when the fourth interface is detected to be a high-level signal, the seventh switch key K7 of the switch key scanning circuit is determined to be in a pressed state.
Preferably, the microprocessor MCU is further configured to: setting a fourth interface of the switch key circuit as output 0, and setting a first interface IO1, a second interface IO2 and a third interface IO3 as pull-up inputs; the microprocessor MCU is also used for: detecting whether any one of the first interface IO1, the second interface IO2 and the third interface IO3 is a low-level signal; the microprocessor MCU is also used for: setting a fourth interface as a pull-up input when the first interface IO1 is detected to be a low-level signal, and determining a sixteenth switch key K16 of the switch key scanning circuit to be in a pressed state when the first interface IO1 is detected to be a high-level signal; the microprocessor MCU is also used for: setting the first interface IO1 as a pull-up input when the second interface IO2 is detected to be a low-level signal, and determining a thirteenth switch key K13 of the switch key scanning circuit to be in a pressed state when the second interface IO2 is detected to be a high-level signal; the microprocessor MCU is also used for: when the third interface IO3 is detected to be a low-level signal, the first interface IO1 is set to be a pull-up input, and when the third interface IO3 is detected to be a high-level signal, the tenth switch key K10 of the switch key scanning circuit is determined to be in a pressed state.
Preferably, whether any switch key of the switch key scanning circuit is in a pressed closed state is detected; when any switch key is detected to be in a pressed closed state, the key identifier is set to be 1, and the switch key scanning circuit is controlled not to enter a key scanning mode; when no switch key is detected to be in a pressed closed state, the key identifier is set to 0, and the switch key scanning circuit is controlled to enter a key scanning mode.
The following describes a scanning method of the switch key scanning circuit according to various embodiments of the present invention in detail with reference to fig. 4 to 10.
Embodiment one:
fig. 4 shows a flow diagram of a scanning method of a switch key scanning circuit according to an embodiment of the invention.
As shown in fig. 4, a scanning method of a switch key scanning circuit according to an embodiment of the present invention includes: step 402, determining whether a key-down program key_down=0 is satisfied, wherein when any one of the scan switch keys is not pressed, the microprocessor writes the identification bit key_down=0, when any one of the scan switch keys is pressed, the microprocessor writes the identification bit key_down=1, if yes, then step 404 is executed, if no, then step 404 is ended; step 404, K1, K2, K3, K4 key scan is started; step 406, judging whether a key is pressed, if yes, ending, otherwise executing 408; step 408, K2, K3, K4, K5, K8, K11 key scan is started; step 410, judging whether a key is pressed, if yes, ending, otherwise executing 412; step 412, K1, K3, K4, K6, K9, K14 key scan begins; step 414, determining whether a key is pressed, if yes, ending, if not, executing 416; step 416, K1, K2, K4, K7, K12, K15 key scan begins; step 418, judging whether a key is pressed, if yes, ending, otherwise executing 420; step 420, K1, K2, K3, K10, K13, K16 key scan is started; step 422, judging whether a key is pressed, if yes, ending, otherwise executing step 424; in step 424, a key handling procedure is performed, which includes writing the identification bit key_down, prompting the user for key information, etc.
Embodiment two:
fig. 5 shows a flow chart of a scanning method of a switch key scanning circuit according to another embodiment of the invention.
As shown in fig. 5, a scanning method of a switch key scanning circuit according to another embodiment of the present invention includes: step 502, judging whether key_down=1, if yes, executing step 504, and if several, ending; step 504, IO1 to IO4 set pull-up inputs; step 506, reading IO1 to IO4, if both are high level, executing step 508 if yes, and ending if not; step 508, setting IO1 output 0, IO2-IO 4 set pull-up inputs; step 510, read IO 2-IO 4, whether all are high level, if yes, go to step 512, if no, end; step 512, set IO2 output 0, IO1, IO3, IO4 set pull-up input; step 514, read IO1, IO3, IO4, if all are high level, execute step 516 if yes, if no, end; step 516, set IO3 output 0, IO1, IO2, IO4 set pull-up input; step 518, read IO1, IO2, IO4, whether all are high level, if yes, go to step 520, if no, end; step 520, set IO4 output 0, IO1, IO2, IO3 set pull-up input; step 522, read IO1, IO2, IO3, if they are all high level, execute step 524 if they are, if they are not, end; in step 524, key_down=0 is written.
Embodiment III:
fig. 6 shows a flow chart of a scanning method of a switch key scanning circuit according to another embodiment of the invention.
As shown in fig. 6, a scanning method of a switch key scanning circuit according to another embodiment of the present invention includes: k1 Beginning K2, K3 and K4 key scanning, and setting pull-up inputs by IO1 to IO4 in step 602; step 604, reading IO 1-IO 4, and judging whether the read IO 1-IO 4 are not all high level; step 606, judging whether IO1 is low level, if so, executing step 614, if not, ending; step 608, determining whether IO2 is at a low level, if so, executing step 616, if not, ending; step 610, determining whether IO3 is at a low level, if so, executing step 618, if not, ending; step 612, judging whether IO4 is low level, if so, executing step 620, if not, ending; step 614, determining that the K1 key is pressed; step 616, determining that the K2 key is pressed; step 618, judging that the K3 key is pressed; step 620 determines that the K4 key is pressed.
Embodiment four:
fig. 7 is a flowchart of a scanning method of the switch key scanning circuit according to another embodiment of the present invention.
As shown in fig. 7, a scanning method of a switch key scanning circuit according to another embodiment of the present invention includes: k2 The scanning of the keys K3, K4, K5, K6 and K11 is started, and in step 702, IO1 is set to output 0, IO2 to IO4 are set to input; step 704, if any of the read IO2 to IO4 is low level or is low level, if yes, step 706 is executed, if no, ending;
(1) Step 706, read IO2, if it is low level, execute step 708 if it is low level, if it is not low level, execute step 706; step 708, setting IO 1-IO 4 input; step 710, read IO2, if it is low, execute step 714 if it is, if it is not, execute step 712; step 712, determining that K4 is pressed; step 714, determining that K2 is pressed;
(2) Step 716, read IO3, if it is low level, execute step 718 if it is low level, if it is not low level, execute step 726; step 718, setting IO 1-IO 4 input; step 720, read IO3, if it is low level, go to step 722 if it is low level, and go to step 724 if it is not low level; step 722, judging that K3 is pressed down; step 724, judging that K8 is pressed down;
(3) Step 726, read IO4, whether it is low level, if yes, go to step 728, if no, end; step 728, setting IO 1-IO 4 inputs; step 730, read IO4, if it is low, execute step 734 if it is, and execute step 732 if it is not; step 732, determining that K5 is pressed; step 734, determine that K4 is pressed.
Fifth embodiment:
fig. 8 is a flow chart of a scanning method of the switch key scanning circuit according to another embodiment of the invention.
As shown in fig. 8, a scanning method of a switch key scanning circuit according to another embodiment of the present invention includes: k6 The K9, K14, K1, K3, K4 key scan begins, step 802, IO2 set output 0, IO1, IO3, and IO4 set inputs; step 804, read IO1, IO3, and IO4, if any one is low level, or both are low level, if yes, go to step 806, if no, end;
(1) Step 806, read IO1, if it is low level, execute step 808 if it is low level, if not, execute step 806; step 808, setting IO 1-IO 4 inputs; step 810, read IO1, if it is low level, execute step 814 if it is low level, if it is not low level, execute step 812; step 812, determining that K14 is pressed; step 814, determining that K1 is pressed;
(2) Step 816, read IO3, if it is low, execute step 818 if it is, and execute step 826 if it is not; step 818, setting IO 1-IO 4 inputs; step 820, read IO3, if it is low level, go to step 822 if it is low level, and go to step 824 if it is not low level; step 822, determining that K3 is pressed; step 824, determining that K9 is pressed;
(3) Step 826, read IO4, if it is low, go to step 828 if it is, if it is not, end; step 828, setting IO 1-IO 4 inputs; step 830, read IO4, if it is low level, execute step 834 if it is low level, and execute step 832 if it is not low level; step 832, judging that K,6 is pressed down; step 834, determining that K4 is pressed.
Example six:
fig. 9 is a flowchart of a scanning method of the switch key scanning circuit according to another embodiment of the present invention.
As shown in fig. 9, a scanning method of a switch key scanning circuit according to another embodiment of the present invention includes: k7 K12, K15, K1, K2, K4 key scan begins, step 902, IO1 set output 0, IO1, IO2, and IO4 set inputs; step 904, read IO1, IO2, and IO4, if any one is low level, or all is low level, if yes, go to step 906, if no, end;
(1) Step 906, read IO1, if it is low level, execute step 908 if it is, if it is not, execute step 906; step 908, setting IO 1-IO 4 inputs; step 910, read IO1, if it is low level, execute step 914 if it is low level, if it is not low level, execute step 912; step 912, determining that K15 is pressed; step 914, judging that K1 is pressed down;
(2) Step 916, read IO2, if it is low level, execute step 918 if it is low level, and execute step 926 if it is not low level; step 918, setting IO 1-IO 4 inputs; step 920, read IO2, if it is low level, execute step 922 if it is low level, otherwise execute step 924; step 922, judging that K2 is pressed down; step 924, judging that K12 is pressed down;
(3) Step 926, read IO4, if it is low level, execute step 928 if it is, if not, end; step 928, setting IO 1-IO 4 inputs; step 930, read IO4, if it is low, execute step 934 if it is low, and execute step 932 if it is not low; step 932, determining that K7 is pressed; step 934, determine that K4 is pressed.
Embodiment seven:
fig. 10 is a flowchart of a scanning method of the switch key scanning circuit according to another embodiment of the present invention.
As shown in fig. 10, a scanning method of a switch key scanning circuit according to another embodiment of the present invention includes: k10 The K13, K16, K1, K2, K3 key scan begins, step 1002, IO1 set output 0, IO1-IO 3 set input; step 1004, if any one of the read IO1 to IO3 is low level or is low level, if yes, step 1006 is executed, if no, ending;
(1) Step 1006, read IO1, if it is low level, execute step 1008 if it is low level, if it is not low level, execute step 1006; step 1008, setting IO 1-IO 4 inputs; step 1010, read IO1, if it is low level, go to step 1014 if it is, and go to step 1012 if it is not; step 1012, judging that K16 is pressed; step 1014, determining that K1 is pressed;
(2) Step 1016, read IO2, if it is low, execute step 1018 if it is, and execute step 1026 if it is not; step 1018, setting IO 1-IO 4 inputs; step 1020, read IO2, if it is low level, execute step 1022 if it is low level, if it is not low level, execute step 1024; step 1022, determining that K2 is pressed; step 1024, determining that K13 is pressed;
(3) Step 1026, read IO3, if it is low level, execute step 1028 if it is low level, if it is not, end; step 1028, setting IO 1-IO 4 input; step 1030, read IO3, if it is low, execute step 1034 if it is, and execute step 1032 if it is not; step 1032, judging that K10 is pressed; step 1034, determine that K3 is pressed.
In the description of the present specification, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the terms "coupled," "mounted," "secured," and the like are to be construed broadly, and may be fixedly coupled, detachably coupled, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, the terms "one embodiment" and the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (14)

1. A switch key scan circuit, comprising:
the microprocessor is provided with a first interface and a second interface;
the first resistor and the first switch key are connected with the output end of the direct-current power supply, the second end of the first resistor is connected with the first end of the first switch key, the second end of the first switch key is grounded, and the second end of the first resistor is connected with the first interface;
The first end of the second resistor is connected to the output end of the direct-current power supply, the second end of the second resistor is connected to the first end of the second switch key, the second end of the second switch key is grounded, and the second end of the second resistor is connected to the second interface;
the first end of the third switch key is connected to the first interface, the second end of the third switch key is connected to the cathode of the first diode, and the anode of the first diode is connected to the first end of the second switch key;
the first end of the fourth switch key is connected to the second interface, the second end of the fourth switch key is connected to the cathode of the second diode, and the anode of the second diode is connected to the first end of the first switch key;
the microprocessor is used for: after entering a key scanning mode, the first interface and the second interface are pull-up inputs;
the microprocessor is further configured to: detecting whether the first interface or the second interface is a low level signal;
The microprocessor is further configured to: when the first interface is detected to be a low-level signal, determining that a first switch key of the switch key scanning circuit is in a pressed closed state;
the microprocessor is further configured to: when the second interface is detected to be a low-level signal, determining that a second switch key of the switch key scanning circuit is in a pressed closed state;
the microprocessor is further configured to: and performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit.
2. The switch key scan circuit of claim 1, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a first interface of the switch key circuit as output 0, and setting a second interface as pull-up input;
the microprocessor is further configured to: detecting whether the second interface is a low level signal;
the microprocessor is further configured to: and when the second interface is detected to be a low-level signal, setting the first interface as a pull-up input, and when the second interface is detected to be a high-level signal, determining that a third switch key of the switch key scanning circuit is in a pressed state.
3. The switch key scan circuit of claim 1, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a second interface of the switch key circuit as output 0, and setting the first interface as pull-up input;
the microprocessor is further configured to: detecting whether the first interface is a low level signal;
the microprocessor is further configured to: and when the first interface is detected to be a low-level signal, setting the second interface as a pull-up input, and when the first interface is detected to be a high-level signal, determining that a fourth switch key of the switch key scanning circuit is in a pressed state.
4. A switch key scan circuit, comprising:
the microprocessor is provided with a first interface, a second interface and a third interface;
the first resistor and the first switch key are connected with the output end of the direct-current power supply, the second end of the first resistor is connected with the first end of the first switch key, the second end of the first switch key is grounded, and the second end of the first resistor is connected with the first interface;
the first end of the second resistor is connected to the output end of the direct-current power supply, the second end of the second resistor is connected to the first end of the second switch key, the second end of the second switch key is grounded, and the second end of the second resistor is connected to the second interface;
The first end of the third resistor is connected to the output end of the direct-current power supply, the second end of the third resistor is connected to the first end of the third switch key, the second end of the third switch key is grounded, and the second end of the third resistor is connected to the third interface;
the first end of the fourth switch key is connected to the first interface, the second end of the fourth switch key is connected to the cathode of the first diode, and the anode of the first diode is connected to the first end of the third switch key;
a fifth switch button, a first end of which is connected to the second interface, and a second end of which is connected to the cathode of the first diode;
a sixth switch key and a second diode, wherein a first end of the sixth switch key is connected to the first interface, a second end of the sixth switch key is connected to a cathode of the second diode, and an anode of the second diode is connected to a first end of the second switch key;
a seventh switch button, a first end of the seventh switch button being connected to the third interface, a second end of the seventh switch button being connected to a cathode of the second diode;
An eighth switch key and a third diode, wherein a first end of the eighth switch key is connected to the second interface, a second end of the eighth switch key is connected to a cathode of the third diode, and an anode of the third diode is connected to a first end of the first switch key;
a ninth switch button, a first end of the ninth switch button being connected to the third interface, a second end of the ninth switch button being connected to a cathode of the third diode;
the microprocessor is further configured to: after entering a key scanning mode, setting a first interface, a second interface and a third interface of the switch key scanning circuit as pull-up inputs;
the microprocessor is further configured to: detecting whether any one of the first interface, the second interface and the third interface is a low-level signal;
the microprocessor is further configured to: when the first interface is detected to be a low-level signal, determining that a first switch key of the switch key scanning circuit is in a pressed closed state;
the microprocessor is further configured to: when the second interface is detected to be a low-level signal, determining that a second switch key of the switch key scanning circuit is in a pressed closed state;
The microprocessor is further configured to: when the third interface is detected to be a low-level signal, determining that a third switch key of the switch key scanning circuit is in a pressed closed state;
the microprocessor is further configured to: performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit;
the first resistor and the second resistor are pull-up resistors.
5. The switch key scan circuit of claim 4, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a first interface of the switch key circuit as output 0, and setting a second interface as pull-up input;
the microprocessor is further configured to: detecting whether the second interface or the third interface is a low level signal;
the microprocessor is further configured to: setting the first interface as a pull-up input when the second interface is detected to be a low-level signal, and determining a sixth switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal;
the microprocessor is further configured to: and when the third interface is detected to be a low-level signal, setting the first interface as a pull-up input, and when the third interface is detected to be a high-level signal, determining that a fourth switch key of the switch key scanning circuit is in a pressed state.
6. The switch key scan circuit of claim 4, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a second interface of the switch key circuit as output 0, and setting the first interface and the third interface as pull-up inputs;
the microprocessor is further configured to: detecting whether the first interface or the third interface is a low level signal;
the microprocessor is further configured to: setting the second interface as a pull-up input when the first interface is detected to be a low-level signal, and determining an eighth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal;
the microprocessor is further configured to: and setting the second interface as a pull-up input when the third interface is detected to be a low-level signal, and determining a fifth switch key of the switch key scanning circuit to be in a pressed state when the third interface is detected to be a high-level signal.
7. The switch key scan circuit of claim 4, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a third interface of the switch key circuit as output 0, and setting the first interface and the second interface as pull-up inputs;
The microprocessor is further configured to: detecting whether the first interface or the second interface is a low level signal;
the microprocessor is further configured to: setting the third interface as a pull-up input when the first interface is detected to be a low-level signal, and determining a ninth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal;
the microprocessor is further configured to: and setting the third interface as a pull-up input when the second interface is detected to be a low-level signal, and determining a seventh switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal.
8. A switch key scan circuit, comprising:
the microprocessor is provided with a first interface, a second interface, a third interface and a fourth interface;
the first resistor and the first switch key are connected with the output end of the direct-current power supply, the second end of the first resistor is connected with the first end of the first switch key, the second end of the first switch key is grounded, and the second end of the first resistor is connected with the first interface;
The first end of the second resistor is connected to the output end of the direct-current power supply, the second end of the second resistor is connected to the first end of the second switch key, the second end of the second switch key is grounded, and the second end of the second resistor is connected to the second interface;
the first end of the third resistor is connected to the output end of the direct-current power supply, the second end of the third resistor is connected to the first end of the third switch key, the second end of the third switch key is grounded, and the second end of the third resistor is connected to the third interface;
the first end of the fourth resistor is connected to the output end of the direct-current power supply, the second end of the fourth resistor is connected to the first end of the fourth switch key, the second end of the fourth switch key is grounded, and the second end of the fourth resistor is connected to the fourth interface;
a fifth switch key and a first diode, wherein a first end of the fifth switch key is connected to the first interface, a second end of the fifth switch key is connected to a cathode of the first diode, and an anode of the first diode is connected to a first end of the fourth switch key;
A sixth switch key, a first end of which is connected to the second interface, and a second end of which is connected to the cathode of the first diode;
a seventh switch key, a first end of which is connected to the third interface, and a second end of which is connected to the cathode of the first diode;
an eighth switch key and a second diode, wherein a first end of the eighth switch key is connected to the first interface, a second end of the eighth switch key is connected to a cathode of the second diode, and an anode of the second diode is connected to a first end of the third switch key;
a ninth switch button, a first end of the ninth switch button being connected to the second interface, a second end of the ninth switch button being connected to a cathode of the second diode;
a tenth switch button, a first end of the tenth switch button being connected to the fourth interface, a second end of the tenth switch button being connected to a cathode of the second diode;
an eleventh switch key and a third diode, a first end of the eleventh switch key being connected to the first interface, a second end of the eleventh switch key being connected to a cathode of the third diode, an anode of the third diode being connected to a first end of the second switch key;
A twelfth switch button, a first end of the twelfth switch button is connected to the third interface, and a second end of the twelfth switch button is connected to the cathode of the third diode;
a thirteenth switch button, a first end of the thirteenth switch button is connected to the fourth interface, and a second end of the fifth switch button is connected to a cathode of the third diode;
a fourteenth switch key and a fourth diode, a first end of the fourteenth switch key being connected to the second interface, a second end of the fourteenth switch key being connected to a cathode of the fourth diode, an anode of the fourth diode being connected to a first end of the first switch key;
a fifteenth switch key, a first end of the fifteenth switch key is connected to the third interface, and a second end of the fifteenth switch key is connected to a cathode of the fourth diode;
a sixteenth switch button, a first end of the sixteenth switch button being connected to the fourth interface, a second end of the sixteenth switch button being connected to a cathode of the fourth diode;
the microprocessor is further configured to: after entering a key scanning mode, setting a first interface, a second interface, a third interface and a fourth interface of the switch key scanning circuit as pull-up inputs;
The microprocessor is further configured to: detecting whether any one of the first interface, the second interface, the third interface and the fourth interface is a low-level signal;
the microprocessor is further configured to: when the first interface is detected to be a low-level signal, determining that a first switch key of the switch key scanning circuit is in a pressed closed state;
the microprocessor is further configured to: when the second interface is detected to be a low-level signal, determining that a second switch key of the switch key scanning circuit is in a pressed closed state;
the microprocessor is further configured to: when the third interface is detected to be a low-level signal, determining that a third switch key of the switch key scanning circuit is in a pressed closed state;
the microprocessor is further configured to: when the fourth interface is detected to be a low-level signal, determining that a fourth switch key of the switch key scanning circuit is in a pressed closed state;
the microprocessor is further configured to: performing cyclic scanning on the switch key scanning circuit according to a preset period to determine a key in a pressed closed state in the switch key scanning circuit;
the first resistor and the second resistor are pull-up resistors.
9. The switch key scan circuit of claim 8, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a first interface of the switch key circuit as output 0, and setting the second interface, the third interface and the fourth interface as pull-up inputs;
the microprocessor is further configured to: detecting whether any one of the second interface, the third interface and the fourth interface is a low-level signal;
the microprocessor is further configured to: setting the first interface as a pull-up input when the second interface is detected to be a low-level signal, and determining an eleventh switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal;
the microprocessor is further configured to: setting the first interface as a pull-up input when the third interface is detected to be a low-level signal, and determining an eighth switch key of the switch key scanning circuit to be in a pressed state when the third interface is detected to be a high-level signal;
the microprocessor is further configured to: and when the fourth interface is detected to be a low-level signal, setting the first interface as a pull-up input, and when the fourth interface is detected to be a high-level signal, determining that a fifth switch key of the switch key scanning circuit is in a pressed state.
10. The switch key scan circuit of claim 8, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a second interface of the switch key circuit as output 0, and setting the first interface, the third interface and the fourth interface as pull-up inputs;
the microprocessor is further configured to: detecting whether any one of the first interface, the third interface and the fourth interface is a low-level signal;
the microprocessor is further configured to: setting the second interface as a pull-up input when the first interface is detected to be a low-level signal, and determining a fourteenth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal;
the microprocessor is further configured to: setting the second interface as a pull-up input when the third interface is detected to be a low-level signal, and determining a ninth switch key of the switch key scanning circuit to be in a pressed state when the third interface is detected to be a high-level signal;
the microprocessor is further configured to: and setting the second interface as a pull-up input when the fourth interface is detected to be a low-level signal, and determining a sixth switch key of the switch key scanning circuit to be in a pressed state when the fourth interface is detected to be a high-level signal.
11. The switch key scan circuit of claim 8, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a third interface of the switch key circuit as output 0, and setting the first interface, the second interface and the fourth interface as pull-up inputs;
the microprocessor is further configured to: detecting whether any one of the first interface, the second interface and the fourth interface is a low-level signal;
the microprocessor is further configured to: setting the first interface as a pull-up input when the first interface is detected to be a low-level signal, and determining a fifteenth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal;
the microprocessor is further configured to: setting the first interface as a pull-up input when the second interface is detected to be a low-level signal, and determining a twelfth switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal;
the microprocessor is further configured to: and when the fourth interface is detected to be a low-level signal, setting the first interface as a pull-up input, and when the fourth interface is detected to be a high-level signal, determining that a seventh switch key of the switch key scanning circuit is in a pressed state.
12. The switch key scan circuit of claim 8, wherein the scan circuit comprises a scan circuit,
the microprocessor is further configured to: setting a fourth interface of the switch key circuit as output 0, and setting the first interface, the second interface and the third interface as pull-up inputs;
the microprocessor is further configured to: detecting whether any one of the first interface, the second interface and the third interface is a low-level signal;
the microprocessor is further configured to: setting the fourth interface as a pull-up input when the first interface is detected to be a low-level signal, and determining a sixteenth switch key of the switch key scanning circuit to be in a pressed state when the first interface is detected to be a high-level signal;
the microprocessor is further configured to: setting the first interface as a pull-up input when the second interface is detected to be a low-level signal, and determining a thirteenth switch key of the switch key scanning circuit to be in a pressed state when the second interface is detected to be a high-level signal;
the microprocessor is further configured to: and setting the first interface as a pull-up input when the third interface is detected to be a low-level signal, and determining a tenth switch key of the switch key scanning circuit to be in a pressed state when the third interface is detected to be a high-level signal.
13. The switch key scan circuit of any one of claims 1 to 12 wherein,
detecting whether any switch key of the switch key scanning circuit is in a pressed closed state;
when any switch key is detected to be in a pressed closed state, a key identifier is set to be 1, and the switch key scanning circuit is controlled not to enter the key scanning mode;
and when detecting that no switch key is in a pressed closed state, setting a key identifier to 0, and controlling a switch key scanning circuit to enter the key scanning mode.
14. A powered device, comprising:
the switch key scan circuit of any of claims 1 to 13.
CN201610604766.XA 2016-07-27 2016-07-27 Switch button scanning circuit and electric equipment Active CN107666323B (en)

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CN109634434A (en) * 2019-01-18 2019-04-16 深圳市富励逻辑科技有限公司 Multi-point combination scanning keyboard, the equipment with keyboard and recognition by pressing keys method
CN111340983B (en) * 2020-02-21 2022-02-11 德施曼机电（中国）有限公司 Intelligent lock verification system and method for preventing Tesla coil from being opened

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