CN107659818A - A kind of video decoder - Google Patents
A kind of video decoder Download PDFInfo
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- CN107659818A CN107659818A CN201710900869.5A CN201710900869A CN107659818A CN 107659818 A CN107659818 A CN 107659818A CN 201710900869 A CN201710900869 A CN 201710900869A CN 107659818 A CN107659818 A CN 107659818A
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- 238000004891 communication Methods 0.000 claims description 4
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- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
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- 241000023320 Luma <angiosperm> Species 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
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- 238000013500 data storage Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/30—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/44008—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving operations for analysing video streams, e.g. detecting features or characteristics in the video stream
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4405—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video stream decryption
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The present invention relates to video decoding filed, more particularly to a kind of video decoder.A kind of video decoder, including：Decoder and decoding accelerator, decoder include：Header syntax parsing unit and hardware register generation unit；Header syntax parsing unit is arranged at SOS layer, and hardware register generation unit is arranged at normal operating system layer；Header syntax parsing unit is used for：The video flowing compressed after decryption is parsed, obtains video flowing header information data, and send to hardware register generation unit；Hardware register generation unit is used for：Under User space pattern, video flowing header information data is parsed.Solve in available frame and hardware register generation unit is arranged in SOS layer, without all codes of whole decoder are carried out to be transplanted to SOS layer, greatly reduce code migrating amount, improve software development efficiency so that product can put into market as early as possible.
Description
Technical field
The present invention relates to video decoding filed, more particularly to a kind of video decoder.
Background technology
With now pirate more and more savage on the market, the enhancing of additional copyright protection consciousness, to increasing video
It is encrypted to obtain security video, after so-called security video refers to the video with copyright, it is necessary to there is key to be decrypted,
It could be played out on ordinary playing device.
When security video plays out, after it is decrypted the decoding video stream of video flowing for compressing and compression into YUV
The space that image is stored can not be accessed by common cpu, therefore security video common at present decoding way is：Will be whole
Video Decoder is transplanted to inside SOS (Secure OS).It is as shown in Figure 1 the playing frame of ordinary video, Fig. 2
Video to support security video to play on the market at present decodes framework, because the video flowing after security video decryption is stored
Internal memory is that common cpu can not be accessed directly, therefore is needed when security video decodes by the phase of Fig. 1 Video Decoder
SOS (Secure OS) in code integral transplanting to Fig. 2 is closed below, but due to SOS
(Secure OS) is within kernel, only supports C operations, and debugs trouble, if whole decoder is transplanted
Words are, it is necessary to expend for a long time, not only efficiency is low, and decoder is entirely transplanted to bottom, and some error handles are more difficult
With control, the stability of a system can be caused poor.
The content of the invention
For this reason, it may be necessary to provide a kind of video decoder, to solve in security video decoding process, time-consuming, efficiency
The problem of low and stability of a system difference.
To achieve the above object, a kind of video decoder is inventor provided, specific implementation technical scheme is as follows：
A kind of video decoder, including：Decoder and decoding accelerator, the decoder communication connection decoding accelerate
Device；The decoder includes：Header syntax parsing unit and hardware register generation unit；The header syntax parsing list
Member communicates to connect the hardware register generation unit；The header syntax parsing unit is arranged at SOS layer,
The hardware register generation unit is arranged at normal operating system layer；The header syntax parsing unit is used for：In step
After " encrypted video being decrypted, the video flowing compressed after being decrypted ", the video flowing compressed after decryption is parsed, obtained
Video flowing header information data is obtained, and sends the video flowing header information data to hardware register generation unit, the video flowing
Header information data includes：Video flowing reference frame information and decoding frame type；The hardware register generation unit is used for：Reception regards
Frequency stream header information data, and under User space pattern, video flowing header information data is parsed, hardware configuration information is obtained,
And the hardware configuration information is sent to the decoding accelerator；The decoding accelerator is used for：Receive the hardware configuration letter
Breath, and the video flowing compressed after decryption is decoded according to the hardware configuration information, obtain decoded video data.
Further, the decoder also includes：Frame administrative unit, the frame administrative unit are arranged at normal operating system
Layer；The frame administrative unit communicates to connect the header syntax parsing unit；The frame administrative unit is used for：In user's morphotype
Under formula, the video flowing reference frame information that the header syntax parsing unit is sent is received, and manage video flowing reference frame information
Further, in addition to：Multimedia accelerator, the multimedia accelerator communicate to connect the decoder；It is described
Multimedia accelerator is used for：The distribution and use of the buffering area of the video flowing compressed after control decryption.
Further, the decoded video data includes：YUV image data.
Further, in addition to：Stream decoder, the stream decoder are used for：Encrypted video is decrypted, obtained
The video flowing compressed after decryption.
The beneficial effects of the invention are as follows：Header syntax parsing unit is arranged at SOS layer, therefore it has permission
The video flowing compressed after decryption is read, and it is parsed, obtains video flowing header information data, and send the video flowing head
Information data is to hardware register generation unit；Hardware register generation unit is arranged at normal operating system layer, because of the unit
Without reading the video flowing compressed after decryption, normal operating system layer is positioned in, it is single can both to have protected hardware register generation
Member is used for：Video flowing header information data is received, and under User space pattern, video flowing header information data is parsed, is obtained
Hardware configuration information, and the hardware configuration information is sent to the function of the decoding accelerator, decoding accelerator is according to
Hardware configuration information decodes to the video flowing compressed after decryption, obtains decoded video data, solves existing frame again
Hardware register generation unit is arranged in SOS layer in frame, code migrating amount is big, and software development efficiency is low
Problem.In the present invention, without carrying out all codes of whole decoder to be transplanted to SOS layer, generation is greatly reduced
Code transplanting amount, simplifies the software development of security video decoding apparatus, so as to improve software development efficiency so that product can be as early as possible
Put into market.
Further, frame administrative unit is arranged at normal operating system layer, you can ensure frame administrative unit in User space
Under pattern, the effect of video flowing reference frame information is managed, and frame data subtract without passing to SOS layer by User space
Few many interactions, improve the stability of a system；And frame administrative unit is arranged at normal operating system layer, decreases and is transplanted to safety
The code migrating amount of operating system layer, greatly improves running efficiency of system.
Brief description of the drawings
Fig. 1 is the schematic diagram of the playing frame of ordinary video described in background technology；
Fig. 2 is the schematic diagram for the video decoding framework for supporting security video to play described in background technology on the market at present；
Fig. 3 is a kind of module diagram of video decoder described in embodiment；
Fig. 4 is the module diagram that a kind of video decoder described in embodiment includes frame administrative unit.
Description of reference numerals：
300th, video decoder；
301st, decoder；
302nd, decoding accelerator；
3010th, hardware register generation unit；
3011st, header syntax parsing unit；
3012nd, frame administrative unit.
Embodiment
To describe the technology contents of technical scheme, construction feature, the objects and the effects in detail, below in conjunction with specific reality
Apply example and coordinate accompanying drawing to be explained in detail.
First, some terms being related in present embodiment are illustrated：
Security video：After video with copyright protection is, it is necessary to there is key to be decrypted, it could be carried out on ordinary playing device
Play；And the locus that the video flowing compressed after decrypting is deposited is the internal memory with protection, common cpu can not be visited directly
Ask, only under safe mode, the internal memory of band protection could be accessed.
Normal operating system：Resource can be divided into protected and non-protected two types in one system, start in system
When some resources can be arranged to safety (i.e. protected type), such as shielded internal memory.Under normal operating system,
It is that can not access shielded internal memory under User space.
SOS：Under SOS, shielded internal memory can be directly accessed.
YUV image data：YUV, it is divided into three components, Y：Represent lightness (Luminance or Luma), that is, gray scale
Value；And U and V：That represent is then colourity (Chrominance or Chroma), and effect is description colors of image and saturation degree, is used for
The color of specified pixel.
Referring to Fig. 3, in the present embodiment, a kind of realization of video decoder 300 is as follows:
A kind of video decoder 300, including：Decoder 301 and decoding accelerator 302, the communication link of decoder 301
Connect decoding accelerator 302；The decoder 301 includes：Header syntax parsing unit 3011 and hardware register generation unit
3010；The header syntax parsing unit 3011 communicates to connect the hardware register generation unit 3010；The header
Syntax parsing unit 3011 is arranged at SOS layer, and the hardware register generation unit 3010 is arranged at normal operations
System layer；The header syntax parsing unit 3011 is used for：In step " encrypted video is decrypted, pressed after being decrypted
After the video flowing of contracting ", the video flowing compressed after decryption is parsed, obtains video flowing header information data, and regarded described in transmission
Frequency stream header information data to hardware register generation unit 3010, the video flowing header information data includes：Video flowing reference frame
Information and decoding frame type；The hardware register generation unit 3010 is used for：Video flowing header information data is received, and in user
Under morphotype formula, video flowing header information data is parsed, obtains hardware configuration information, and send the hardware configuration information extremely
The decoding accelerator 302；The decoding accelerator 302 is used for：The hardware configuration information is received, and is matched somebody with somebody according to the hardware
Confidence breath decodes to the video flowing compressed after decryption, obtains decoded video data.
In the present embodiment, in actual decoding process, security video is decrypted first, compressed after being decrypted
Video flowing, the core position of video flowing storage is that common cpu (i.e. normal operating system layer) has no idea access, and is solved
Header syntax parsing unit 3011 in code device 301 is related to the access of the video flowing to being compressed after decryption, therefore the head is believed
Breath syntax parsing unit 3011 is arranged at SOS layer, therefore header syntax parsing unit 3011 has authority to decryption
The video flowing compressed afterwards is parsed, and obtains video flowing header information data.Because the communication link of header syntax parsing unit 3011
Hardware register generation unit 3010 is connect, therefore the video flowing header information data can be transmitted to hardware register generation unit in it
3010, hardware register generation unit 3010 has no the access for being related to the video flowing to being compressed after decryption, therefore is positioned in general
Logical operating system layer, therefore it is parsed under User space pattern to video flowing header information data, obtains hardware configuration letter
Breath.Decoding accelerator 302 receives the hardware configuration information, and according to the hardware configuration information to the video that is compressed after decryption
Stream is decoded, and obtains decoded video data, and in the present embodiment, the decoding accelerator 302 is arranged at safe behaviour
Make system layer.In the present embodiment, decoded video data is deposited core position and the video flowing compressed after decryption
The position deposited is the same, is equally that common cpu can not be accessed.
Header syntax parsing unit 3011 is arranged at SOS layer, therefore it has permission what is compressed after reading is decrypted
Video flowing, and it is parsed, video flowing header information data is obtained, and send the video flowing header information data to hardware and post
Storage generation unit 3010；Hardware register generation unit 3010 is arranged at normal operating system layer, because the unit is without reading
The video flowing compressed after decryption, normal operating system layer is positioned in, can both protect hardware register generation unit 3010 and use
In：Video flowing header information data is received, and under User space pattern, video flowing header information data is parsed, obtains hardware
Configuration information, and the hardware configuration information is sent to the function of the decoding accelerator 302, decoding accelerator 302 is according to institute
State hardware configuration information to decode the video flowing compressed after decryption, obtain decoded video data, solve again existing
Hardware register generation unit 3010 is arranged in SOS layer in framework, causing need to be by its code migrating to safety
Operating system layer, the problem of code migrating amount is big, and software development efficiency is low.In the present invention, without by the whole institute of decoder 301
There is code to carry out being transplanted to SOS layer, greatly reduce code migrating amount, simplify security video decoding apparatus
Software development, so as to improve software development efficiency so that product can put into market as early as possible.
Referring to Fig. 4, in other embodiments, the decoder 301 also includes：Frame administrative unit 3012, the frame
Administrative unit 3012 is arranged at normal operating system layer；The frame administrative unit 3012 communicates to connect the header syntax parsing
Unit 3011；The frame administrative unit 3012 is used for：Under User space pattern, the header syntax parsing unit 3011 is received
The video flowing reference frame information of transmission, and manage video flowing reference frame information.
By the way that frame administrative unit 3012 is arranged at into normal operating system layer, you can ensure frame administrative unit 3012 in user
Under morphotype formula, the function of video flowing reference frame information is managed, and frame data by User space without passing to SOS layer
(frame administrative unit 3012 in the prior art, is arranged at SOS layer, then the transmission of frame data, which will be related to, passes through user
State is to SOS layer), many interactions are reduced, so as to reduce wrong probability of happening, improve the stability of a system；And frame management
Unit 3012 is arranged at normal operating system layer, decreases the code migrating amount for being transplanted to SOS layer, carries significantly
High running efficiency of system.
In other embodiments, the video decoder 300 also includes：Multimedia accelerator, the multimedia add
Fast device communicates to connect the decoder 301；The multimedia accelerator is used for：The buffering area of the video flowing compressed after control decryption
Distribution and use.In the present embodiment, the multimedia accelerator may be disposed at normal operating system layer, and it not only can use
To control the distribution and use of the buffering area of the video flowing compressed after decryption, equally may also be used for controlling decoded video counts
According to buffering area distribution and use.In the present embodiment, frame administrative unit 3012 also communicates to connect hardware register generation
Unit 3010, the video flowing and decoded video data that multimedia accelerator compresses after respectively decrypting distribute buffering respectively
Qu Hou, the distribution information is sent to frame administrative unit 3012, frame administrative unit 3012 by the distribution information of buffering area send to
The distribution information of the buffering area is then sent through decoding by hardware register generation unit 3010, hardware register generation unit 3010
In accelerator 302, decoded video data is finally written in the buffering area allocated in advance by decoding accelerator 302.
In present embodiment, to ensure the safety of decoded video data, the buffering area of decoded video data storage falls within peace
Full buffer area (i.e. shielded buffering area), therefore in the present embodiment, to ensure decoding accelerator 302 by video data decoding
To shielded buffering area, the decoding accelerator 302 is arranged at SOS layer.Meanwhile because of the decoding accelerator
302 are arranged at SOS layer, thus hardware register generation unit 3010 by the distribution information transmission of the buffering area extremely
Decoding accelerator 302, that is, it is sent to SOS layer and carries out validation of information, and in SOS layer according to described slow
The distribution information for rushing area carries out configuration hardware, it is ensured that the security of hardware configuration information.
In other embodiments, the decoded video data includes：YUV image data.YUV image data only need
Take few frequency range.
In other embodiments, the video decoder 300 also includes：Stream decoder, the stream decoder
For：Encrypted video is decrypted, the video flowing compressed after being decrypted.
It should be noted that although the various embodiments described above have been described herein, but not thereby limit
The scope of patent protection of the present invention.Therefore, based on the present invention innovative idea, to embodiment described herein carry out change and repair
Change, or the equivalent structure or equivalent flow conversion made using description of the invention and accompanying drawing content, directly or indirectly will be with
Upper technical scheme is used in other related technical areas, is included within the scope of patent protection of the present invention.
Claims (5)
- A kind of 1. video decoder, it is characterised in that including：Decoder and decoding accelerator, the decoder communication connection Decoding accelerator；The decoder includes：Header syntax parsing unit and hardware register generation unit；The header syntax parsing unit communicates to connect the hardware register generation unit；The header syntax parsing unit is arranged at SOS layer, and the hardware register generation unit is arranged at general Logical operating system layer；The header syntax parsing unit is used for：" encrypted video is decrypted, the video compressed after being decrypted in step After stream ", the video flowing compressed after decryption is parsed, obtains video flowing header information data, and sends the video flowing head letter Breath data to hardware register generation unit, the video flowing header information data includes：Video flowing reference frame information and decoding frame Type；The hardware register generation unit is used for：Video flowing header information data is received, and under User space pattern, to video flowing Header information data is parsed, and obtains hardware configuration information, and send the hardware configuration information to the decoding accelerator；The decoding accelerator is used for：The hardware configuration information is received, and according to the hardware configuration information to being pressed after decryption The video flowing of contracting is decoded, and obtains decoded video data.
- 2. a kind of video decoder according to claim 1, it is characterised in that the decoder also includes：Frame management Unit, the frame administrative unit are arranged at normal operating system layer；The frame administrative unit communicates to connect the header syntax parsing unit；The frame administrative unit is used for：Under User space pattern, the video flowing that the header syntax parsing unit is sent is received Reference frame information, and manage video flowing reference frame information.
- 3. a kind of video decoder according to claim 1, it is characterised in that also include：Multimedia accelerator, it is described Multimedia accelerator communicates to connect the decoder；The multimedia accelerator is used for：The distribution and use of the buffering area of the video flowing compressed after control decryption.
- A kind of 4. video decoder according to claim 1, it is characterised in thatThe decoded video data includes：YUV image data.
- 5. a kind of video decoder according to claim 1, it is characterised in that also include：Stream decoder, the code Stream decoder is used for：Encrypted video is decrypted, the video flowing compressed after being decrypted.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710900869.5A CN107659818A (en) | 2017-09-28 | 2017-09-28 | A kind of video decoder |
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| CN201710900869.5A CN107659818A (en) | 2017-09-28 | 2017-09-28 | A kind of video decoder |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109656715A (en) * | 2018-12-10 | 2019-04-19 | 晶晨半导体(上海)股份有限公司 | A kind of broadcasting EMS memory management process |
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| CN103780959A (en) * | 2012-10-18 | 2014-05-07 | 美国博通公司 | Integration of untrusted applications and frameworks with a secure operating system environment |
| CN105453094A (en) * | 2013-04-23 | 2016-03-30 | 微软技术许可有限责任公司 | Protected media decoding using a secure operating system |
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Application publication date: 20180202 |