CN107659280A - A kind of time amplifier and semiconductor memory - Google Patents
A kind of time amplifier and semiconductor memory Download PDFInfo
- Publication number
- CN107659280A CN107659280A CN201711125182.5A CN201711125182A CN107659280A CN 107659280 A CN107659280 A CN 107659280A CN 201711125182 A CN201711125182 A CN 201711125182A CN 107659280 A CN107659280 A CN 107659280A
- Authority
- CN
- China
- Prior art keywords
- electric capacity
- type flip
- flip flop
- buffer
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000003111 delayed effect Effects 0.000 claims abstract description 7
- 239000000872 buffer Substances 0.000 claims description 55
- 235000006508 Nelumbo nucifera Nutrition 0.000 claims description 6
- 240000002853 Nelumbo nucifera Species 0.000 claims description 6
- 210000001367 artery Anatomy 0.000 claims description 2
- 210000003462 vein Anatomy 0.000 claims description 2
- 238000004080 punching Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract 1
- 230000005611 electricity Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000013139 quantization Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
Landscapes
- Amplifiers (AREA)
Abstract
The invention provides a kind of time amplifier, embedded at least one d type flip flop in time amplifier, if the time point that the delayed predetermined time interval of very first time pulse reaches the first d type flip flop is different from the time point of the second time pulse the first d type flip flop of arrival, the logical signal of first d type flip flop output controls to adjust capacitance of the capacitance less than the first electric capacity of the second electric capacity so that the gain amplifier of time amplifier reduces；Or first the logical signal of d type flip flop output control to adjust the capacitance of the first electric capacity and be less than the capacitance of the second electric capacity so that the gain amplifier increase of time amplifier, realize the purpose of the adjustable gain of time amplifier.Present invention also offers a kind of semiconductor memory, has above-mentioned technique effect.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of time amplifier, further relates to a kind of semiconductor storage
Device.
Background technology
Delay phase-locked loop (DLL, Delay-Locked Loop) is typically used in DDR3/DDR4 dynamic random access memories
In device, delay phase-locked loop is used for the delay for automatically adjusting signal all the way, makes the phase of two paths of signals consistent (edge alignment).Specifically
Ground, in the case where needing some data signals synchronous with system clock, delay phase-locked loop aligns the edge of two-way clock, uses
The clock being conditioned does control signal, it is possible to produces the signal with system clock stringent synchronization, and this is synchronous not with extraneous bar
The part such as change of temperature, voltage and change, therefore be widely used.
In order to measure fine-time interval, time-to-digit converter (TDC, Time-to-Digital are embedded with DLL
Converter while), in recent years, in order to improve TDC time precisions, its switching rate is improved, time amplifier thought meets the tendency of
And give birth to, based on time amplifier, " thick quantization-amplification-thin quantization " can be carried out to time interval, only using only coarse quantization
Device just can obtain higher temporal resolution.Polytype time amplifier (TA, Time can be embedded in TDC
Amplifier), such as time amplifier based on S/R latch, door time amplifier, 1x/4x delay buffer time amplifiers.
Wherein, it is made up of based on the time amplifier of S/R latch two S/R latches and a gate, its gain and S/R latch are defeated
It is directly proportional to go out the additional capacitor that end is set, however, the major defect of the time amplifier based on S/R latch is time-reversal mirror
Gain can not be adjusted according to the actual requirements, and then cause DLL time interval measurement precision relatively low.
Therefore, how to make the adjustable gain of time amplifier, be ability so as to improve DLL time detecting measurement precision
Field technique personnel are badly in need of technical problems to be solved.
The content of the invention
The present invention provides a kind of time amplifier and a kind of semiconductor memory, is deposited with overcoming or alleviated by background technology
One or more problem, provide at a kind of beneficial selection.
As one aspect of the present invention, there is provided a kind of time amplifier, including：
First latch unit and the first buffer, first buffer is used for the input for receiving very first time pulse, described
First breech lock input of the first latch unit is connected with the output end of first buffer, the second door bolt of first latch unit
Lock input and receive the second time pulse, the Q output lotus root of first latch unit is connected to the first electric capacity, first latch unit
'sOutput end is coupled with the second electric capacity；And
First d type flip flop, the first triggering input of first d type flip flop cache from the buffer from described first
Device receives the very first time pulse of delayed predetermined time interval, the second triggering input termination of first d type flip flop
Receive second time pulse, the first trigger output end of first d type flip flop and first electric capacity and second electricity
At least one connection in appearance, for controlling to adjust the capacitance of first electric capacity and second electric capacity.
Preferably, in time amplifier described above, first buffer includes multiple first be serially connected
Buffer unit, signal of each first buffer unit for postponing input first buffer, the multiple described first
One or more first buffer units in buffer unit are jointly by pre- timing described in the very first time pulse daley
Between be spaced.
Preferably, in time amplifier described above, in addition to：
Second latch unit and the second buffer, second buffer is used for the input for receiving the second time pulse, described
3rd breech lock input of the second latch unit is connected with the output end of second buffer, the 4th door bolt of second latch unit
Lock input and receive very first time pulse, the Q output lotus root of second latch unit is connected to the 3rd electric capacity, second latch unit
'sOutput end is coupled with the 4th electric capacity；
Second d type flip flop, the first breech lock input of second d type flip flop are delayed from second buffer reception
Second time pulse of the predetermined time interval, the second breech lock input of second d type flip flop receive described the
One time pulse, the output end of second d type flip flop and at least one company in the 3rd electric capacity and the 4th electric capacity
Connect.
Preferably, in time amplifier described above, second buffer includes multiple second be serially connected
Buffer unit, each second buffer unit are used to postpone the signal for inputting the buffer unit, the multiple second buffer unit
In one or more second buffer units second time pulse is postponed into the predetermined time interval jointly.
Preferably, in time amplifier described above, in addition to：
OR gate, the first input end of the OR gate are connected with first trigger output end of first d type flip flop, institute
State the second input of OR gate to be connected with second trigger output end of second d type flip flop, the output end of the OR gate
With first electric capacity, second electric capacity, the 3rd electric capacity or the 4th capacitance connection.
Preferably, in time amplifier described above, in addition to the Q output of first latch unit andIt is defeated
Go out end connection the first nor gate, and with the Q output of second latch unit andSecond nor gate of output end connection.
Preferably, in time amplifier described above, first electric capacity, second electric capacity, the 3rd electricity
Hold and one of electric capacity of the 4th electric capacity comprises at least：
At least two branch roads, in parallel between the branch road, the input of the branch road and corresponding first latch unit
Output end or second latch unit output end connection, the output head grounding of the branch road；
Wherein, branch route branch road electric capacity and switch composition connect with the branch road electric capacity, it is described switch by
First d type flip flop of corresponding connection or second d type flip flop or logic control.
Preferably, in time amplifier described above, the switch includes：
NAND gate, as first d type flip flop that correspondingly connects or second d type flip flop or logic control described in
Whether the contact pin of NOT gate accesses the branch road.
Preferably, in time amplifier described above, when the contact pin accesses the branch road, corresponding connection
First d type flip flop or second d type flip flop send a control signal to the controlling switch of the NAND gate.
On the other hand, a kind of semiconductor memory, including the time amplifier described in any of the above-described are additionally provided.
The present invention uses above-mentioned technical proposal, has the following advantages that：This programme embedded at least one D in time amplifier
Trigger, if the delayed predetermined time interval of very first time pulse reaches time point and the second time pulse of the first d type flip flop
Reach the capacitance for logical signal the second electric capacity of control and regulation that the time point of the first d type flip flop is different, and the first d type flip flop exports
Less than the capacitance of the first electric capacity so that the gain amplifier of time amplifier reduces；Or first d type flip flop output logic letter
Number control to adjust the first electric capacity capacitance be less than the second electric capacity capacitance so that time amplifier gain amplifier increase,
Realize the purpose of the adjustable gain of time amplifier.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to is limited in any way.Except foregoing description
Schematical aspect, outside embodiment and feature, it is further by reference to accompanying drawing and the following detailed description, the present invention
Aspect, embodiment and feature would is that what is be readily apparent that.
Brief description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent same or analogous through multiple accompanying drawing identical references
Part or element.What these accompanying drawings were not necessarily to scale.It should be understood that these accompanying drawings depict only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is a kind of time amplifier internal circuit schematic diagram that embodiment of the present invention provides.
Fig. 2 is the internal circuit schematic diagram of the first electric capacity of capacitance coarse adjustment provided in an embodiment of the present invention.
Fig. 3 is the internal circuit schematic diagram of the first electric capacity of capacitance provided in an embodiment of the present invention fine setting.
Reference：
100 first latch units；
First NAND gate of 110 first latch units；Second NAND gate of 120 first latch units；
111 first breech lock inputs；121 second breech lock inputs；
The Q output of 112 first latch units；122 first latch unitsOutput end；
300 first d type flip flops；
311 first triggering inputs；312 second triggering inputs；
313 first trigger output ends；
410 first electric capacity；420 second electric capacity；
TIN1Very first time pulse；TIN2Second time pulse；
200 second latch units；
First NAND gate of 210 second latch units；Second NAND gate of 220 second latch units；
211 the 3rd breech lock inputs；221 the 4th breech lock inputs；
212 first latch unitsOutput end；The Q output of 222 first latch units；
300 ' second d type flip flops；
321 the 3rd triggering inputs；322 the 4th triggering inputs；
323 second trigger output ends；
430 the 3rd electric capacity；440 the 4th electric capacity；
330 OR gates；
411 branch roads；412 branch road electric capacity；
413 switches；413 ' NAND gates；
413 ' A contact pin；413 ' B controlling switch；
510 first nor gates；520 second nor gates；
600 first buffers；610 first buffer units；
600 ' second buffers；610 ' second buffer units.
Embodiment
Hereinafter, some exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, accompanying drawing and description are considered essentially illustrative rather than restrictive.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", " on ", " under ", "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer ", " up time
The orientation or position relationship of the instruction such as pin ", " counterclockwise ", " axial direction ", " radial direction ", " circumference " be based on orientation shown in the drawings or
Position relationship, it is for only for ease of and describes the present invention and simplify description, rather than indicates or imply that signified device or element must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are only used for describing purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the invention, " multiple " are meant that two or more,
Unless otherwise specifically defined.
In the present invention, unless otherwise clearly defined and limited, term " installation ", " connected ", " connection ", " fixation " etc.
Term should be interpreted broadly, for example, it may be fixedly connected or be detachably connected, or integrally；Can be that machinery connects
Connect or electrically connect, can also be communication；Can be joined directly together, can also be indirectly connected by intermediary, can be with
It is connection or the interaction relationship of two elements of two element internals.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or it " under "
Can directly it be contacted including the first and second features, it is not directly to contact but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " include fisrt feature
Directly over second feature and oblique upper, or it is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " fisrt feature that includes are directly over second feature and oblique upper, or be merely representative of the
One characteristic level is highly less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.Certainly, they are only example, and
And purpose does not lie in the limitation present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, between itself not indicating discussed various embodiments and/or setting
Relation.In addition, the invention provides various specific techniques and material examples, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
Embodiment one
In a kind of embodiment, there is provided a kind of time amplifier, including：
First latch unit 100, the first buffer 600, the first buffer 600 are used to receive very first time pulse TIN1It is defeated
Entering, the first breech lock input 111 of the first latch unit is connected with the output end of the first buffer 600, and the second of the first latch unit
Breech lock input 121 receives the second time pulse TIN2, the lotus root of Q output 112 of the first latch unit is connected to the first electric capacity 410, and first
Latch unitOutput end 122 is coupled with the second electric capacity 420；
First d type flip flop 300, the first triggering input 311 of the first d type flip flop are received through prolonging from the first buffer 600
The very first time pulse T of slow predetermined time intervalIN1, the second triggering the second time arteries and veins of reception of input 312 of the first d type flip flop
Rush TIN2, at least one company in the first trigger output end 313 and the first electric capacity 410 and the second electric capacity 420 of the first d type flip flop
Connect, for controlling to adjust the capacitance of the first electric capacity 410 and the second electric capacity 420.
In the present embodiment, the capacitance of any one in the first electric capacity 410 and the second electric capacity 420 is adjustable, if when first
Between pulse TIN1Delayed predetermined time interval reaches time point and the second time pulse T of the first d type flip flop 300IN2Reach the
The time point of one d type flip flop 300 is different, and the logical signal of the first d type flip flop 300 output controls to adjust the electricity of the first electric capacity 410
Capacitance is more than the capacitance of the second electric capacity 420 so that the gain amplifier of time amplifier reduces；Or first d type flip flop 300 it is defeated
The logical signal gone out controls to adjust capacitance of the capacitance less than the second electric capacity 420 of the first electric capacity 410 so that time amplifier
Gain amplifier increase.
Further, the first buffer 600 includes multiple first buffer units 610 being serially connected, and each first caching is single
Member 610 is used to postpone the signal for inputting first buffer, and multiple first buffer units 610 are jointly by very first time pulse
TIN1Delay scheduled time interval.
On the basis of above-mentioned embodiment, in addition to：
Second latch unit 200 and the second buffer 600 ', the second buffer 600 ' are used to receive the defeated of the second time pulse
Enter, the first breech lock input 211 of the second latch unit 200 is connected with the output end of the second buffer 600 ', the second latch unit 200
The 4th breech lock input 221 receive very first time pulse TIN1, the lotus root of Q output 212 of the second latch unit is connected to the 3rd electric capacity
430, the second latch unitOutput end 222 is coupled with the 4th electric capacity 440；
Second d type flip flop 300 ', the 3rd triggering 321 of the second d type flip flop are delayed pre- from the reception of the second buffer 600 '
Fix time the second time pulse T at intervalIN2, the 4th triggering reception very first time pulse of input 322 of the second d type flip flop
TIN1, at least one connection in the second trigger output end 323 and the 3rd electric capacity 430 and the 4th electric capacity 440 of the second d type flip flop,
For controlling to adjust the capacitance of the 3rd electric capacity 430 and the 4th electric capacity 440.
In the present embodiment, the capacitance of any one in the 3rd electric capacity 430 and the 4th electric capacity 440 is adjustable, if first
Time pulse TIN1Reach the time point of the second d type flip flop 300 ' and the second time pulse T by predetermined time interval delayIN2
Reach logical signal the 4th electric capacity of control and regulation that the time point of the second d type flip flop 300 ' is different, and the second d type flip flop 300 ' exports
440 capacitance is more than the capacitance of the 3rd electric capacity 430 so that the gain amplifier of time amplifier reduces；Or the 2nd D triggering
The logical signal that device 300 ' exports controls to adjust capacitance of the capacitance less than the 3rd electric capacity 430 of the 4th electric capacity 440 so that when
Between amplifier gain amplifier increase.
On the basis of above-mentioned embodiment, in addition to：
OR gate 330, the first input end 331 of OR gate are connected with the first trigger output end 313 of the first d type flip flop 300, or
Second input 332 of door is connected with the second trigger output end 323 of the second d type flip flop, the electricity of output end 333 and first of OR gate
Hold the 410, second electric capacity 420, the 3rd electric capacity 430 or the 4th electric capacity 440 to connect.
On the basis of above-mentioned embodiment, including with the Q output of the first latch unit 100 andThe of output end connection
One nor gate 510, and with the Q output of the second latch unit 210 andSecond nor gate 520 of output end connection.
On the basis of above-mentioned time amplifier, Fig. 2 and 3 illustrates by taking the first electric capacity as an example, first the 410, second electricity of electric capacity
Hold one of electric capacity of the 420, the 3rd electric capacity 430 and the 4th electric capacity 440 at least, including：
At least two branch roads 411, in parallel between branch road 411, the input of branch road 411 and corresponding first latch unit 100
Output end or the second latch unit 210 output end connection, the output head grounding of branch road 411；
Wherein, branch road 411 forms by branch road electric capacity 412 and with the switch 413 that the electric capacity of branch road 411 is connected, switch 413 by
To the first d type flip flop 300 or the second d type flip flop 300 ' or the logic control for corresponding to connection.
On the basis of above-mentioned time amplifier, switch 413 includes：
NAND gate 413 ', by the first d type flip flop 300 for correspondingly connecting or the second d type flip flop 300 ' or logic control with
The A of contact pin 413 ' of NOT gate whether access leg 411, the first d type flip flop 300 or the second d type flip flop 300 ' connect for control
The A of pin 413 ' is touched to be connected or disconnected to adjust the size of the capacitance of each electric capacity with branch road 411.
On the basis of above-mentioned time amplifier, when contacting the A access leg 411 of pin 413 ', the first d type flip flop 300
Or second d type flip flop 300 ' sends a control signal to the B of controlling switch 413 ' of NAND gate 413 '.First d type flip flop 300 or
Second d type flip flop 300 ' is used to send logical signal to the B of controlling switch 413 ' to adjust the size of the capacitance of each electric capacity.
Specifically, the first d type flip flop 300 or the second d type flip flop 300 ' by the logical signal of output to access leg 411
The A of contact pin 413 ' be controlled with whether branch road 411 is connected or disconnects, now, the switch 413 of NAND gate 413 ' is suitable
Switched in common valve, coarse adjustment is carried out to the capacitance of whole tunable capacitor.It is connected to the contact A of pin 413 ' with branch road 411
In the case of, the first d type flip flop 300 or the second d type flip flop 300 ' send logical signal to the B of controlling switch 413 ' to adjust electricity
The size of capacitance is finely adjusted, and enhances the degree of regulation of capacitance.
As shown in Figures 2 and 3, illustrated so that the first d type flip flop 300 is to the regulation and control of the first electric capacity 410 as an example, if the first electricity
Three parallel branches 411 are contained in holding 410, a branch road electric capacity 412 and a switch 413 are in series with every branch road 411,
First d type flip flop 300 is controlled to the switch 413 in three branch roads 411, controls connecing for the NAND gate in three branch roads 411
The A of pin 413 ' is touched to be connected with this branch road 411, as the so far B of controlling switch 413 ' of NAND gate of input logic signal 000, first
The capacitance of electric capacity 410 is 1.324822fF, during input logic signal 001, capacitance 1.340683fF, is compared
1.324822fF differs 0.015861fF, during input logic signal 011, capacitance 1.356543fF, compared to 1.340683fF
Poor 0.015861fF, during input logic signal 111, capacitance 1.372704fF, 0.015861fF poor compared to 1.356543fF,
Therefore, the capacitance of each electric capacity is finely tuned.
Embodiment two
In another embodiment, a kind of semiconductor memory is additionally provided, including described in any of the above-described
Time amplifier.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, its various change or replacement can be readily occurred in,
These should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
Shield scope is defined.
Claims (10)
- A kind of 1. time amplifier, it is characterised in that including：First latch unit and the first buffer, input of first buffer for receiving very first time pulse, described first First breech lock input of latch unit is connected with the output end of first buffer, and the second breech lock of first latch unit is defeated Enter end and receive the second time pulse, the Q output lotus root of first latch unit is connected to the first electric capacity, first latch unit Output end is coupled with the second electric capacity；AndFirst d type flip flop, the first triggering input of first d type flip flop receive delayed make a reservation for from first buffer The very first time pulse of time interval, the second triggering input of first d type flip flop receive the second time arteries and veins Punching, the first trigger output end of first d type flip flop and at least one company in first electric capacity and second electric capacity Connect, for controlling to adjust the capacitance of first electric capacity and second electric capacity.
- 2. time amplifier as claimed in claim 1, it is characterised in that first buffer is multiple including being serially connected First buffer unit, signal of each first buffer unit for postponing input first buffer, multiple described first Buffer unit is jointly by predetermined time interval described in the very first time pulse daley.
- 3. time amplifier as claimed in claim 2, it is characterised in that also include：Second latch unit and the second buffer, input of second buffer for receiving the second time pulse, described second 3rd breech lock input of latch unit is connected with the output end of second buffer, and the 4th breech lock of second latch unit is defeated Enter end and receive very first time pulse, the Q output lotus root of second latch unit is connected to the 3rd electric capacity, second latch unit Output end is coupled with the 4th electric capacity；Second d type flip flop, the 3rd triggering input of second d type flip flop are delayed described from second buffer reception Second time pulse of predetermined time interval, when the 4th triggering input of second d type flip flop receives described first Between pulse, at least one in the second trigger output end of second d type flip flop and the 3rd electric capacity and the 4th electric capacity Individual connection, for controlling to adjust the capacitance of the 3rd electric capacity and the 4th electric capacity.
- 4. time amplifier as claimed in claim 3, it is characterised in that second buffer is multiple including being serially connected Second buffer unit, signal of each second buffer unit for postponing input second buffer, multiple described second Second time pulse is postponed the predetermined time interval by buffer unit jointly.
- 5. time amplifier as claimed in claim 4, it is characterised in that also include：OR gate, the first input end of the OR gate are connected with first trigger output end of first d type flip flop, it is described or Second input of door is connected with second trigger output end of second d type flip flop, the output end of the OR gate and institute State the first electric capacity, second electric capacity, the 3rd electric capacity or the 4th capacitance connection.
- 6. time amplifier as claimed in claim 5, it is characterised in that also include the Q output with first latch unit WithOutput end connection the first nor gate, and with the Q output of second latch unit andOutput end connection second or NOT gate.
- 7. time amplifier as claimed in claim 6, it is characterised in that first electric capacity, second electric capacity, described One of electric capacity of three electric capacity and the 4th electric capacity comprises at least：At least two branch roads, in parallel between the branch road, the input of the branch road and corresponding first latch unit or institute State the output end connection of the second latch unit, the output head grounding of the branch road；Wherein, the branch route branch road electric capacity and the switch composition connected with the branch road electric capacity, the switch is by corresponding Connection first d type flip flop or second d type flip flop or logic control.
- 8. time amplifier as claimed in claim 7, it is characterised in that the switch includes：NAND gate, as first d type flip flop that correspondingly connects or second d type flip flop or logic control described in NAND gate Contact pin whether access the branch road.
- 9. time amplifier as claimed in claim 8, it is characterised in that right when the contact pin accesses the branch road First d type flip flop or second d type flip flop that should connect send a control signal to the controlling switch of the NAND gate.
- 10. a kind of semiconductor memory, it is characterised in that including the time amplifier described in any one of claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711125182.5A CN107659280B (en) | 2017-11-14 | 2017-11-14 | Time amplifier and semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711125182.5A CN107659280B (en) | 2017-11-14 | 2017-11-14 | Time amplifier and semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107659280A true CN107659280A (en) | 2018-02-02 |
| CN107659280B CN107659280B (en) | 2023-10-20 |
Family
ID=61121351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711125182.5A Active CN107659280B (en) | 2017-11-14 | 2017-11-14 | Time amplifier and semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107659280B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113162566A (en) * | 2021-05-17 | 2021-07-23 | 合肥工业大学 | Programmable high-precision high-dynamic-range time amplifier |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1807092A1 (en) * | 1968-11-05 | 1970-06-18 | Siemens Ag | Fast pulse amplifier with stable base line for - pulse spectrography |
| JPS4854982A (en) * | 1971-11-04 | 1973-08-02 | ||
| US4618787A (en) * | 1983-12-09 | 1986-10-21 | At&T Teletype Corporation | Adjustable time delay circuit |
| TW200406986A (en) * | 2002-06-28 | 2004-05-01 | Nec Electronics Corp | Output buffer apparatus capable of adjusting output impedance in synchronization with data signal |
| US20070080735A1 (en) * | 2005-02-05 | 2007-04-12 | Neotec Semiconductor Ltd. | Method and apparatus for selection internal or external time delay |
| US20090102555A1 (en) * | 2007-10-23 | 2009-04-23 | Blum Gregory A | Automatic gain Control (AGC) with lock detection |
| CN101567666A (en) * | 2008-04-21 | 2009-10-28 | 瑞昱半导体股份有限公司 | Time amplifier for amplifying time difference and method therefor |
| CN203675066U (en) * | 2013-12-17 | 2014-06-25 | 浙江大学城市学院 | Pulse D type trigger employing floating gate MOS pipe |
-
2017
- 2017-11-14 CN CN201711125182.5A patent/CN107659280B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1807092A1 (en) * | 1968-11-05 | 1970-06-18 | Siemens Ag | Fast pulse amplifier with stable base line for - pulse spectrography |
| JPS4854982A (en) * | 1971-11-04 | 1973-08-02 | ||
| US4618787A (en) * | 1983-12-09 | 1986-10-21 | At&T Teletype Corporation | Adjustable time delay circuit |
| TW200406986A (en) * | 2002-06-28 | 2004-05-01 | Nec Electronics Corp | Output buffer apparatus capable of adjusting output impedance in synchronization with data signal |
| US20070080735A1 (en) * | 2005-02-05 | 2007-04-12 | Neotec Semiconductor Ltd. | Method and apparatus for selection internal or external time delay |
| US20090102555A1 (en) * | 2007-10-23 | 2009-04-23 | Blum Gregory A | Automatic gain Control (AGC) with lock detection |
| CN101567666A (en) * | 2008-04-21 | 2009-10-28 | 瑞昱半导体股份有限公司 | Time amplifier for amplifying time difference and method therefor |
| CN203675066U (en) * | 2013-12-17 | 2014-06-25 | 浙江大学城市学院 | Pulse D type trigger employing floating gate MOS pipe |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113162566A (en) * | 2021-05-17 | 2021-07-23 | 合肥工业大学 | Programmable high-precision high-dynamic-range time amplifier |
| CN113162566B (en) * | 2021-05-17 | 2022-12-06 | 合肥工业大学 | Programmable high-precision high-dynamic-range time amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107659280B (en) | 2023-10-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10771231B2 (en) | Signaling system with adaptive timing calibration | |
| US9041451B2 (en) | Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks | |
| US7042296B2 (en) | Digital programmable delay scheme to continuously calibrate and track delay over process, voltage and temperature | |
| US20120206181A1 (en) | Multi-function delay locked loop | |
| CN102778673B (en) | Radar return signal high-precision distance simulation method and device as well as target simulator | |
| US6437616B1 (en) | Delay lock loop with wide frequency range capability | |
| US20110163787A1 (en) | Digital phase locking loop and method for eliminating glitches | |
| WO2009137522A2 (en) | Method and apparatus for power sequence timing to mitigate supply resonance in power distribution network | |
| US20140035649A1 (en) | Tuned resonant clock distribution system | |
| US10313099B1 (en) | Multi-lane coherent transceiver with synchronized lane reset signals | |
| CN106716537B (en) | Delay circuit with parallel delay lines and internal switches between delay lines, and method and apparatus for controlling the delay circuit | |
| CN100474436C (en) | Methods and apparatus for delay circuit | |
| US6501309B1 (en) | Semiconductor device having timing stabilization circuit with overflow detection function | |
| CN107659280A (en) | A kind of time amplifier and semiconductor memory | |
| US9213657B2 (en) | Memory controller with fast reacquisition of read timing to support rank switching | |
| CN107634732A (en) | A kind of time amplifier and semiconductor memory | |
| US6756808B2 (en) | Clock edge detection circuit | |
| CN207475497U (en) | A kind of time amplifier and semiconductor memory | |
| US10698846B2 (en) | DDR SDRAM physical layer interface circuit and DDR SDRAM control device | |
| US20180309448A1 (en) | Data transmission with power supply noise compensation | |
| US7683729B2 (en) | Injection locked LC VCO clock deskewing | |
| Di Maio et al. | Comparison of hypertopologies | |
| US9590641B2 (en) | Semiconductor apparatus and regulation circuit thereof | |
| CN109120262A (en) | A kind of fast lock phase-locked loop frequency synthesis device | |
| CN207410308U (en) | A kind of time amplifier and semiconductor memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20181009 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant after: CHANGXIN MEMORY TECHNOLOGIES, Inc. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Applicant before: INNOTRON MEMORY CO.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |