CN107656895B - Orthogonal platform high-density computing architecture with standard height of 1U - Google Patents

Orthogonal platform high-density computing architecture with standard height of 1U Download PDF

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CN107656895B
CN107656895B CN201711019841.7A CN201711019841A CN107656895B CN 107656895 B CN107656895 B CN 107656895B CN 201711019841 A CN201711019841 A CN 201711019841A CN 107656895 B CN107656895 B CN 107656895B
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architecture
orthogonal
cpu
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computing architecture
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CN107656895A (en
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谭德海
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Shanghai Linuo Communication Technology Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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Abstract

The invention discloses a 1U standard height orthogonal platform high-density computing architecture, which consists of a main board design and a power supply, wherein the main board design adopts a four-star processing architecture E5-V4 computing architecture at the 1U standard height orthogonal node slot position, two sides adopt standard server main boards, each server main board is provided with two CPUs, two separated main boards are fused to the 1U height node slot position of the orthogonal architecture through a high-density network fusion card, the four-star processing architecture E5-V4 computing architecture can select up to 14 cores of CPU, each CPU is provided with two 40GE networks connected to different orthogonal exchange cards, a 40GE large-flow data path is arranged between the CPU and the exchange cards, and redundant switching can be realized through the network connection of the two 40GE networks, so that the requirements of more core numbers, larger network flow and software and hardware optimization integration of the whole system architecture are met.

Description

Orthogonal platform high-density computing architecture with standard height of 1U
Technical Field
The invention relates to the field of high-density computation of an orthogonal platform, in particular to a high-density computation architecture of the orthogonal platform with a standard height of 1U.
Background
With the continuous development of technology, especially the high-speed development of the internet and the mobile internet, network data traffic is larger and larger, protocol parsing and processing are more and more, and ports are more and more, so that requirements on hardware platforms capable of bearing the requirements are higher and higher. As the high-density calculation of X86, which is the main force carrying application processing, the main frequency of the CPU has reached the limit, and the CPU has been advancing toward the increase of the number of cores. The market naturally expects higher and higher densities of CPUs. The number of the high-end CPU cores in the current mainstream reaches 14-16; the next generation of CPU cores may support 18-20 or even more.
The current mainstream of the strong processor can support 14 cores; the next generation of the lineage processor can support more than 18 cores. Such a high-profile server, employing a dual CPU architecture, may have a throughput of up to 80G to 100G. However, the mainstream general server in the market stays in the era of 10G network, and even if the network card can be upgraded to 40GE by expanding, the capability of the existing CPU can not be fully exerted; in addition, in the aspect of matching and optimizing software and hardware, step mismatch frequently occurs. Because of the data interaction between the CPUs, the processing performance of the CPUs is virtually compromised. The same configuration is adopted in the industry, the CPU processes the network traffic respectively, and the two CPUs acquire the traffic from one network to process, and the performance of the CPU is 15-20% higher than that of the CPU in the network interface bandwidth.
How to make the next generation computing platform more nucleus, the network flow is larger, the software and hardware optimization is deeper, and the method becomes the problem that the future generation computing architecture needs to be considered.
Disclosure of Invention
Aiming at the problems in the background technology, the invention provides a 1U standard height orthogonal platform high-density computing architecture.
In order to achieve the above purpose, the present invention provides the following technical solutions: A1U standard height orthogonal platform high-density computing architecture is composed of a main board design and a power supply; the main board design adopts an E5-V4 computing architecture of a four-star processing architecture at a 1U standard height orthogonal node slot position, two sides of the main board adopt standard four-star architecture server main boards, each server main board is provided with two CPUs, two separated main boards are fused to the 1U height node slot position of the orthogonal architecture through a high-density network fusion card, the E5-V4 computing architecture of the four-star processing architecture selects 14-core CPUs, so that the total number of CPU cores of the whole computing architecture is 56, and the number of supported hardware threads is 112; in the aspect of network integration, each CPU is provided with two 40GE networks which are connected to different orthogonal exchange cards, a 40GE large-flow data path is arranged between each CPU and each exchange card, redundant switching is realized through the network connection of the two 40GE networks, the reliability of the whole system architecture is met, and the network integration card simultaneously provides a management path for each computing node and is in butt joint with the platform management path of the whole orthogonal architecture; the power supply design adopts a 12V redundant power supply, and supports an intelligent management function.
As an optimal technical scheme of the invention, the four-star architecture server mainboard is compatible with an Intel current mainstream Saint V3/V4 processor or an Intel next generation Saint expansion processor series, and the number of cores of each CPU supports Saint processors from 6 cores to 18 cores to 20 cores.
Compared with the prior art, the invention has the beneficial effects that: each CPU processor is provided with an independent network interface and is respectively connected with the orthogonal switching array and the external interface, so that all network data are completed by the own CPU, and unless the upper application software has the necessity of mutual cooperative processing and data interaction, the mode can fundamentally avoid the performance of the CPU to consume large-capacity data interaction among the CPUs, further dig the CPU capacity of high-density data processing, and if the upper application software needs cooperative processing among the CPUs, the data interaction is needed densely, and the data interaction is completed through a large amount of high-capacity and high-bandwidth QPI buses.
Drawings
FIG. 1 is a schematic diagram of a high-density computing architecture based on a Zhi Qiang E5-V4 processor according to the present invention;
FIG. 2 is a schematic diagram of a high-density computing architecture based on the most recent generation of lineage scalability in accordance with the present invention;
FIG. 3 is a schematic diagram of a management path of the E5-V4 computing architecture of the present invention;
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples:
referring to fig. 1, 2 and 3, the present invention provides a 1U standard height orthogonal platform high-density computing architecture, which is composed of a motherboard design and a power supply; the main board design adopts an E5-V4 computing architecture of a four-star processing architecture at a 1U standard height orthogonal node slot position, two sides of the main board adopt standard four-star architecture server main boards, each server main board is provided with two CPUs, two separated main boards are fused to the 1U height node slot position of the orthogonal architecture through a high-density network fusion card, the E5-V4 computing architecture of the four-star processing architecture selects 14-core CPUs, so that the total number of CPU cores of the whole computing architecture is 56, and the number of supported hardware threads is 112; in the aspect of network integration, each CPU is provided with two 40GE networks which are connected to different orthogonal exchange cards, a 40GE large-flow data path is arranged between each CPU and each exchange card, redundant switching is realized through the network connection of the two 40GE networks, the reliability of the whole system architecture is met, and the network integration card simultaneously provides a management path for each computing node and is in butt joint with the platform management path of the whole orthogonal architecture; the power supply design adopts a 12V redundant power supply, and supports an intelligent management function.
Further, the four-star architecture server motherboard is compatible with Intel current mainstream Saint V3/V4 processors or Intel next generation Saint expansion processor series, and the number of cores of each CPU supports Saint processors from 6 cores to 18 cores to 20 cores.
Based on the above, the invention has the advantages that: each CPU provides two or more 40GE/100GE capabilities. The network bandwidth bottleneck is thoroughly eliminated at the network side, and the performance of each CPU can be fully exerted. Moreover, the architecture can provide enough upgrade space according to a later stronger processor, and the overall computing capacity of the orthogonal architecture in the next years is directly dependent on the capacity of the selected CPU for the high-density computing architecture, so that other network bandwidths and CPU performance losses can be obtained through simple double-speed superposition, and the computing architecture is not a bottleneck any more.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (2)

1. The utility model provides a high-density computing architecture of quadrature platform of 1U standard height which characterized in that: the power supply consists of a main board design and a power supply;
the main board design adopts an E5-V4 computing architecture of a four-star processing architecture at a 1U standard height orthogonal node slot position, two sides of the main board adopt standard four-star architecture server main boards, each server main board is provided with two CPUs, two separated main boards are fused to the 1U height node slot position of the orthogonal architecture through a high-density network fusion card, the E5-V4 computing architecture of the four-star processing architecture selects 14-core CPUs, so that the total number of CPU cores of the whole computing architecture is 56, and the number of supported hardware threads is 112; in the aspect of network integration, each CPU is provided with two 40GE networks which are connected to different orthogonal exchange cards, a 40GE large-flow data path is arranged between each CPU and each exchange card, redundant switching is realized through the network connection of the two 40GE networks, the reliability of the whole system architecture is met, and the network integration card simultaneously provides a management path for each computing node and is in butt joint with the platform management path of the whole orthogonal architecture;
the power supply design adopts a 12V redundant power supply, and supports an intelligent management function.
2. The 1U standard height orthogonal platform high density computing architecture of claim 1, wherein: the four-star architecture server mainboard is compatible with Intel current mainstream Saint V3/V4 processors or Intel next generation Saint expansion processor series, and the number of cores of each CPU supports Saint processors from 6 cores to 18 cores to 20 cores.
CN201711019841.7A 2017-10-27 2017-10-27 Orthogonal platform high-density computing architecture with standard height of 1U Active CN107656895B (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1562124A2 (en) * 2004-02-06 2005-08-10 Samsung Electronics Co., Ltd. Apparatus and method for setting routing path between routers in chip
CN1735878A (en) * 2002-11-11 2006-02-15 克利尔斯皮德科技有限公司 State engine for data processor
CN101848154A (en) * 2010-05-17 2010-09-29 华为技术有限公司 System based on advanced telecom computation architecture
CN102306139A (en) * 2011-08-23 2012-01-04 北京科技大学 Heterogeneous multi-core digital signal processor for orthogonal frequency division multiplexing (OFDM) wireless communication system
CN204945888U (en) * 2015-09-22 2016-01-06 王剑霞 The built-in wireless router device of a kind of main frame
CN105830053A (en) * 2014-01-16 2016-08-03 英特尔公司 An apparatus, method, and system for a fast configuration mechanism
CN107220195A (en) * 2017-05-26 2017-09-29 郑州云海信息技术有限公司 A kind of multichannel computer system architecture for supporting high density NVMe to store

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9858227B2 (en) * 2015-02-08 2018-01-02 Silicom Ltd. Hybrid networking application switch

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1735878A (en) * 2002-11-11 2006-02-15 克利尔斯皮德科技有限公司 State engine for data processor
EP1562124A2 (en) * 2004-02-06 2005-08-10 Samsung Electronics Co., Ltd. Apparatus and method for setting routing path between routers in chip
CN101848154A (en) * 2010-05-17 2010-09-29 华为技术有限公司 System based on advanced telecom computation architecture
CN102306139A (en) * 2011-08-23 2012-01-04 北京科技大学 Heterogeneous multi-core digital signal processor for orthogonal frequency division multiplexing (OFDM) wireless communication system
CN105830053A (en) * 2014-01-16 2016-08-03 英特尔公司 An apparatus, method, and system for a fast configuration mechanism
CN204945888U (en) * 2015-09-22 2016-01-06 王剑霞 The built-in wireless router device of a kind of main frame
CN107220195A (en) * 2017-05-26 2017-09-29 郑州云海信息技术有限公司 A kind of multichannel computer system architecture for supporting high density NVMe to store

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Scaling Support Vector Machines on modern HPC platforms";Yang You;《Journal of Parallel and Distributed Computing》;第76卷;第16-31页 *
"空间站高性能交换单元关键技术研究与实现";周海;《中国优秀硕士学位论文全文数据库 信息科技辑》(2013年第05期);第I136-132页 *

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