CN107656892A - A kind of New Bus interconnection system - Google Patents
A kind of New Bus interconnection system Download PDFInfo
- Publication number
- CN107656892A CN107656892A CN201710943332.7A CN201710943332A CN107656892A CN 107656892 A CN107656892 A CN 107656892A CN 201710943332 A CN201710943332 A CN 201710943332A CN 107656892 A CN107656892 A CN 107656892A
- Authority
- CN
- China
- Prior art keywords
- mainboard
- signal
- connector
- pcb
- central processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/409—Mechanical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The present invention relates to a kind of New Bus interacted system, it is characterised in that including mainboard and PCB platelets, the mainboard is provided with Socket slots, and PCB platelets are communicated to connect by Socket slots and mainboard；PCB platelets are provided with central processor core and board connector；Central processor core communicates to connect with board connector；Mainboard is provided with I/O connector, and board connector is connected with I/O connector through Cable cable communications；Central processor core also communicates to connect by PCB platelets and mainboard.High and low speed signal cabling on mainboard is separated, the risk that the exploitation design cost brought with traditional PCB design method is lifted and the material procurement cycle increases is reduced, improves the competitiveness of product commercially.
Description
Technical field
The invention belongs to server product System design technology field, and in particular to a kind of New Bus interacted system.
Background technology
In server product system design, motherboard design has been intended to highly dense high speed development, signal lead speed
Lifting, the compact of board structure size all produce large effect to the transmission quality of high speed signal.
To ensure the high speed signaling quality transmitted over long distances on pcb board, when board designs, often through using very
Low loss sheet materials reduce signal transmission attenuation, increase the lamination number of plies, relax the coupling spacing between each HW High Way with this
To reduce cross talk effects or high speed signal carried out to recover to amplify again using Redriver and Retimer Signal Regulations device
The transmission quality of high speed signal is lifted etc. mode, it is ensured that the stabilization of system operation when high speed signal interconnects in plate and between each plate level
Property.
Such scheme is used, although can guarantee that the letter transmitted over long distances on pcb board after the lifting of high speed trace signal speed
Number quality, but cost can be designed and developed to board, production and procurement cycle etc. bring a certain degree of influence, such as using electricity
Property more preferable sheet material, the lifting of purchase cost and the growth of procurement cycle can be brought because of the sheet material in the industry cycle relatively low problem of utilization rate,
The increase lamination number of plies also brings along the difficulty of processing lifting of pcb board factory and production cost improves.This is the deficiencies in the prior art part.
The content of the invention
It is an object of the present invention to it is because on its pcb board when reducing mainboard high-speed signaling designs for above-mentioned prior art
Signal lead length is larger, and high frequency signal transmission is lifted by using the preferable sheet material of electrical property or increase Signal Regulation device
During quality, the caused risk for designing and developing cost and the increase of material procurement cycle, there is provided it is mutual to design a kind of New Bus
Contact system, to solve above-mentioned technical problem.
In order to achieve the above object, the technical scheme is that：
A kind of New Bus interacted system, including mainboard and PCB platelets, the mainboard are provided with Socket slots, and PCB platelets lead to
Socket slots are crossed to communicate to connect with mainboard；
PCB platelets are provided with central processor core and board connector；Central processor core and board connector communication link
Connect；
Mainboard is provided with I/O connector, and board connector is connected with I/O connector through Cable cable communications；
Central processor core communicates to connect by PCB platelets and mainboard.
Further, PCB platelets one side sets central processor core, and the another side of PCB platelets is provided with circular pad, will
PCB platelets are interconnected with the signal on mainboard by circular pad with the Socket slots grafting on mainboard and communicated.
Further, passage will be transmitted according to the height of transmission rate through the signal that central processor core transmits
Separation；
The transmission signal of different passages is connected to I/O connector or with mainboard PCB by board connector with Cable cables respectively
Plate cabling is transferred to I/O connector.
Further, through central processor core transmission signal according to the height of transmission rate be divided into first kind signal and
Second class signal；
The first kind signal of central processor core output is connected by board connector and I/O connector through Cable cable communications
Connect；
Second class signal of central processor core output communicates to connect by PCB platelets and mainboard.
Further, first kind signal is the high speed signal that transmission rate is more than or equal to 1 Gbps；Second class signal is
Transmission rate is less than 1Gbps low speed signal；
High speed signal is connected to I/O connector by board connector with Cable cables；
Low speed signal is transferred to I/O connector by mainboard pcb board cabling.
Further, the high speed signal includes PCIE3.0 interface signals, SAS3.0 interface signals and SATA3.0 interfaces
Signal.
The present invention designs the PCB platelets of one, and the board connector with external cable interconnection is set on PCB platelets；Meanwhile
This PCB platelet is as central processor core and the interconnecting channel of mainboard, so that the high speed signal transmitted on mainboard can pass through
This PCB platelet is transferred on the chip part that other communicate with central processor core interconnection on server master board.
The connector that central processor core and HW High Way communicate to external application Cable cable interconnections is all placed on PCB
On platelet, PCB platelets are provided with signal circular pad, PCB platelets are put on the Socket slots on mainboard, circular pad and master
Coherent signal on plate is interconnected communication.
Cable cables are preferable to high speed transmission of signals loss rejection ability in itself, the characteristic that can be transmitted over long distances, by center
The high speed data transfer signal and low speed control signals of processor chips output are transmitted channel separation, high speed data transfer letter
Number mainboard I/O connector is all connected in a manner of cable, and low speed control signals still continue to use mainboard pcb board cabling and are transferred to master
Plate I/O connector.So, can both ensure high speed signal over long distances transmit when signal quality simultaneously, reduce Cable cables again
Development cost and assembling complexity, the competitiveness of product in market of lifting.
The beneficial effects of the present invention are, technical solution of the present invention is separated high and low speed signal cabling on mainboard,
It is passed to respective link channel and mainboard I/O connector port interconnection, the high-frequency loss on usual Cable cables is remote low
Connect up on pcb board in signal and consumed caused by transmission, support longer signal transmission distance, ensure that signal high speed is intercommunicated
Transmission quality during letter.Reduce the exploitation design cost lifting brought with traditional PCB design method and the material procurement cycle increases
Long risk, improve the competitiveness of product commercially.
In addition, design principle of the present invention is reliable, and it is simple in construction, there is very extensive application prospect.
As can be seen here, the present invention compared with prior art, has prominent substantive distinguishing features and significantly improved, it is implemented
Beneficial effect be also obvious.
Brief description of the drawings
Fig. 1 is a kind of New Bus interacted system structural representation that the present embodiment provides.
Fig. 2 is the sheet material frequency domain Loss of High FR4 and Low Loss two loss decay waveforms.
Fig. 3 is that Cable cables and Low Loss PCB unit length insertion loss values are enumerated.
Wherein, 1- mainboards, 2-PCB platelets, 3- central processor cores, 4-IO connectors, 5- board connectors.
Embodiment
Below in conjunction with the accompanying drawings and the present invention will be described in detail by specific embodiment, and following examples are to the present invention
Explanation, and the invention is not limited in implementation below.
As shown in figure 1, a kind of New Bus interacted system that the present embodiment provides, including mainboard 1 and PCB platelets 2, it is described
Mainboard 1 is provided with Socket slots, and PCB platelets 2 are communicated to connect by Socket slots and mainboard 1；
PCB platelets 2 are provided with central processor core 3 and board connector 5；Central processor core 3 is logical with board connector 5
Letter connection；
Mainboard 1 is provided with I/O connector 4, and board connector 5 is connected with I/O connector 4 through Cable cable communications；
Central processor core 3 also communicates to connect by PCB platelets 2 with mainboard 1.
PCB platelets 2 simultaneously set central processor core 3, and the another side of PCB platelets 2 is provided with circular pad, and PCB is small
Plate 2 is interconnected with the signal on mainboard 1 by circular pad with the Socket slots grafting on mainboard 1 and communicated.
The separation of passage will be transmitted according to the height of transmission rate through the signal that central processor core 3 transmits；
The transmission signal of different passages is connected to I/O connector 4 with cable by board connector 5 respectively or walked with mainboard pcb board
Line is transferred to I/O connector 4.
First kind signal is divided into according to the height of transmission rate through the signal that central processor core 3 transmits and the second class is believed
Number；
The first kind signal that central processor core 3 exports is by board connector 5 and I/O connector 4 through Cable cable communications
Connection；
The second class signal that central processor core 3 exports communicates to connect by PCB platelets 2 with mainboard 1.
First kind signal is the high speed signal that transmission rate is more than or equal to 1 Gbps；Second class signal is that transmission rate is small
In 1Gbps low speed signal；
High speed signal is connected to I/O connector by board connector with Cable cables；
Low speed signal is transferred to I/O connector by mainboard pcb board cabling.
The high speed signal includes PCIE3.0 interface signals, SAS3.0 interface signals and SATA3.0 interface signals；
PCIE3.0 interface signal speed is that 8Gbps, SAS3.0 interface signal speed are that 12Gbps and SATA3.0 interface signal speed is
6Gbps high speed signal is communicated to connect by Cable cables and mainboard.
As shown in Fig. 2 if high speed signal, only when being transmitted on pcb board, it uses High FR4 and Low Loss two electric
During type sheet material, it is known that in Fig. 2 frequency domain signal insertion loss waveforms, Low-Loss sheet material attenuation amplitudes are significantly less than High
The influence of FR4 sheet materials, its time domain signal eye diagram waveform its with the lifting of signal rate, when it is under low-loss sheet materials,
Signal eye diagram is also better than High FR4 sheet materials.Meanwhile as shown in figure 3, from the point of view of part electrical characteristics itself, Cable cables damage
Consumption will be significantly better than the situation that Low Loss sheet materials are used on pcb board.
From the point of view of application 25Gbps high speed signal interconnecting transfers, to support the feasibility of transmission communication over long distances, from letter
From the point of view of number integrality angle, high speed signal is interconnected transmission in a manner of Cable cables.
Disclosed above is only the preferred embodiment of the present invention, but the present invention is not limited to this, any this area
What technical staff can think does not have creative change, and some improvement made without departing from the principles of the present invention and
Retouching, should all be within the scope of the present invention.
Claims (6)
1. a kind of New Bus interacted system, it is characterised in that including mainboard and PCB platelets, the mainboard is provided with Socket
Slot, PCB platelets are communicated to connect by Socket slots and mainboard；
PCB platelets are provided with central processor core and board connector；Central processor core and board connector communication link
Connect；
Mainboard is provided with I/O connector, and board connector is connected with I/O connector through Cable cable communications；
Central processor core also communicates to connect by PCB platelets and mainboard.
2. a kind of New Bus interacted system according to claim 1, it is characterised in that PCB platelets one side sets center
Processor chips, the another side of PCB platelets are provided with circular pad, and PCB platelets and the Socket slot grafting on mainboard are passed through
Circular pad is interconnected with the signal on mainboard and communicated.
3. a kind of New Bus interacted system according to claim 2, it is characterised in that will be passed through central processor core
Defeated signal is transmitted the separation of passage according to the height of transmission rate；
The transmission signal of different passages is connected to I/O connector with Cable cables by board connector respectively or passes through mainboard
Pcb board cabling is transferred to I/O connector.
4. a kind of New Bus interacted system according to claim 3, it is characterised in that transmitted through central processor core
Signal first kind signal and the second class signal are divided into according to the height of transmission rate；
The first kind signal of central processor core output is connected by board connector and I/O connector through Cable cable communications
Connect；
Second class signal of central processor core output communicates to connect by PCB platelets and mainboard.
A kind of 5. New Bus interacted system according to claim 4, it is characterised in that
First kind signal is the high speed signal that transmission rate is more than or equal to 1 Gbps；Second class signal is less than for transmission rate
1Gbps low speed signal；
High speed signal is connected to I/O connector by board connector with Cable cables；
Low speed signal is transferred to I/O connector by mainboard pcb board cabling.
A kind of 6. New Bus interacted system according to claim 5, it is characterised in that
Described high speed signal includes PCIE3.0 interface signals, SAS3.0 interface signals and SATA3.0 interface signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710943332.7A CN107656892A (en) | 2017-10-11 | 2017-10-11 | A kind of New Bus interconnection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710943332.7A CN107656892A (en) | 2017-10-11 | 2017-10-11 | A kind of New Bus interconnection system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107656892A true CN107656892A (en) | 2018-02-02 |
Family
ID=61117176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710943332.7A Pending CN107656892A (en) | 2017-10-11 | 2017-10-11 | A kind of New Bus interconnection system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107656892A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110337182A (en) * | 2019-07-31 | 2019-10-15 | 新华三技术有限公司合肥分公司 | Circuit board assemblies and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1601313A (en) * | 2003-09-24 | 2005-03-30 | 国际商业机器公司 | Apparatus and methods for integrally packaging optoelectronic devices, IC chips and optical transmission lines |
| CN2735566Y (en) * | 2004-06-21 | 2005-10-19 | 中兴通讯股份有限公司南京分公司 | A structure for high-speed interconnection between primary and secondary board |
| CN101027950A (en) * | 2004-09-27 | 2007-08-29 | 英特尔公司 | Flexible cable for high-speed interconnect |
| CN205229924U (en) * | 2015-12-16 | 2016-05-11 | 山东海量信息技术研究院 | PCIE expands integrated circuit board based on high -end server |
| CN105607708A (en) * | 2015-12-23 | 2016-05-25 | 山东海量信息技术研究院 | Electrooptic and photoelectric conversion technology based server design method |
-
2017
- 2017-10-11 CN CN201710943332.7A patent/CN107656892A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1601313A (en) * | 2003-09-24 | 2005-03-30 | 国际商业机器公司 | Apparatus and methods for integrally packaging optoelectronic devices, IC chips and optical transmission lines |
| CN2735566Y (en) * | 2004-06-21 | 2005-10-19 | 中兴通讯股份有限公司南京分公司 | A structure for high-speed interconnection between primary and secondary board |
| CN101027950A (en) * | 2004-09-27 | 2007-08-29 | 英特尔公司 | Flexible cable for high-speed interconnect |
| CN205229924U (en) * | 2015-12-16 | 2016-05-11 | 山东海量信息技术研究院 | PCIE expands integrated circuit board based on high -end server |
| CN105607708A (en) * | 2015-12-23 | 2016-05-25 | 山东海量信息技术研究院 | Electrooptic and photoelectric conversion technology based server design method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110337182A (en) * | 2019-07-31 | 2019-10-15 | 新华三技术有限公司合肥分公司 | Circuit board assemblies and electronic equipment |
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| PB01 | Publication | ||
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180202 |