CN107644622A - Drive unit and drive array - Google Patents
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- CN107644622A CN107644622A CN201711119979.4A CN201711119979A CN107644622A CN 107644622 A CN107644622 A CN 107644622A CN 201711119979 A CN201711119979 A CN 201711119979A CN 107644622 A CN107644622 A CN 107644622A
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- 230000000087 stabilizing effect Effects 0.000 claims description 51
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- 238000006073 displacement reaction Methods 0.000 claims description 7
- 230000001960 triggered effect Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 210000001367 artery Anatomy 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 210000003462 vein Anatomy 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 241000208340 Araliaceae Species 0.000 description 2
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 2
- 235000003140 Panax quinquefolius Nutrition 0.000 description 2
- 235000008434 ginseng Nutrition 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
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Abstract
The invention discloses a driving unit, which comprises a first switch unit, a shift register and a second switch unit. The shift register has a temporary storage node and an output end, wherein the temporary storage node is used for temporarily storing the shift signal and is coupled to the control end of the first switch unit. The second switch unit has an input terminal, an output terminal and a control terminal, wherein the input terminal of the second switch unit receives the first clock signal, the output terminal of the second switch unit is coupled to the input terminal of the first switch unit, and the control terminal of the second switch unit receives the control signal to control whether the second switch unit conducts the first clock signal to the first switch unit.
Description
Technical field
The present invention is on a kind of driver element, especially with regard to a kind of driving of the display panel with partial scan function
Unit and driving array.
Background technology
Display panel is driven using full scan (Full Scan) mode mostly on the market at present, that is, display panel is every
During secondary renewal frame, all can sequentially it be scanned per scan line.However, when for special power saving picture, such a full scan side
Formula simultaneously can not effective power saving.For example, when display panel, which only has part picture, to be updated, full scan mode can still continue more
New all scan lines, then being not required to the scan line of the picture part of renewal can still be updated by recharge.
Therefore, a kind of concept of partial scan (Partial Scan) is suggested, wherein being needed only for having in display panel
The scan line of part to be updated is charged to update, and remainder without charging to maintain previous frame time
Picture, thereby, it can significantly lower unnecessary power wastage.
The content of the invention
In order to realize part scan mechanism, a kind of driver element is proposed in the technology aspect of the present invention.Driver element
Include first switch unit, shift registor and second switch unit.First switch unit has input, output end and control
End.Shift registor has temporary node and output end, and wherein this temporary node is configured to temporarily store shift signal.Temporary node coupling
To the control terminal of first switch unit.Second switch unit has input, output end and control terminal, wherein second switch unit
Input receive the first clock signal, the output end of second switch unit is coupled to the input of first switch unit, second
The control terminal of switch element receives control signal and opened with controlling second switch unit whether the first clock signal to be conducted into first
Close unit.
Another driver element is proposed in another technology aspect of the present invention.Driver element include first switch unit,
Shift registor, second switch unit and the 3rd switch element.First switch unit has input, output end and control terminal.
Shift registor has an input and the first output end, and the wherein input of shift registor is receiving shift signal.The
Two switch elements have input, output end and control terminal, and the wherein input of second switch unit receives the first clock pulse letter
Number, the control terminal of the output end coupling first switch unit of second switch unit.3rd switch element has input, output end
And control terminal, wherein shift registor according to shift signal trigger with by the first shift signal via the first output end send to
The input of 3rd switch element.The output end of 3rd switch element is coupled to the control terminal of second switch unit.3rd switch
The control terminal of unit receives control signal to control whether the 3rd switch element is turned on so that the first shift signal is sent to second
The control terminal of switch element.
A kind of driving array is proposed in the another technology aspect of the present invention.Array is driven to drive display panel.Drive
Dynamic array includes multiple driver elements.This multiple driver element is respectively driving one-row pixels corresponding in display panel.
This little driver element each self-contained first switch unit, shift registor and second switch units.First switch unit has defeated
Enter end, output end and control terminal, wherein row pixel corresponding in output end coupling display panel.Shift registor has temporary
Node and output end, wherein temporary node is configured to temporarily store shift signal.Temporary node is coupled to the control terminal of first switch unit.
Second switch unit has input, output end and control terminal, and the wherein input of second switch unit receives the first clock pulse letter
Number, the output end of second switch unit is coupled to the input of first switch unit, and the control terminal of second switch unit receives control
Signal processed is to control whether second switch unit is conducted to first switch unit by the first clock signal.
By the announcement of the driver element and driving array of the present invention, a kind of novel partial scan technology is disclosed for, made
Display panel can reduce power consumption.
Brief description of the drawings
Fig. 1 is the driving array and display panel schematic diagram of one embodiment of the invention.
Fig. 2 is the driver element circuit diagram of one embodiment of the invention.
Fig. 3 is the timing waveform of the driver element of one embodiment of the invention.
Fig. 4 is the timing waveform of the driving array of one embodiment of the invention.
Fig. 5 is the driver element circuit diagram of one embodiment of the invention.
Wherein, reference：
100：Drive array
110：Display panel
C1：Electric capacity
CK1：First clock signal
CK2：Second clock signal
CK3：3rd clock signal
CT1、CT3：First control circuit
CT2、CT4：Second control circuit
Ctrl：Control signal
D[N-1]、D[N]、D[N]’：Driver element
D[N+1]、D[N+2]：Driver element
ENA、ENB：Periodic signal
G1~G6：Control terminal
G [1]~G [10], G [N-2], G [N-1]：Shift signal
G[N]、G[N+1]、G[N+2]：Shift signal
G[K]、H[N]：Shift signal
I1~I6：Input
M1~M20：Switch element
O1~O8：Output end
P1：Temporary node
PH1、PH2：Reference voltage input block
PX[N-1]、PX[N]、PX[N+1]、PX[N+2]：Row pixel
Q：Node
S1~S2：Voltage stabilizing element
S1 [3]~S1 [7], S1 [K], S1 [N-1]：First scanning signal
S1[N]、S1[N+1]、S1[N+2]：First scanning signal
S2 [3]~S2 [7], S2 [K], S2 [N-1]：Second scanning signal
S2[N]、S2[N+1]、S2[N+2]：Second scanning signal
SR1、SR2：Shift registor
T1~T9：Period
VGH：Reference voltage
VST、G[0]：Enabling signal
XCtrl：Voltage stabilizing control signal
Embodiment
Hereafter institute accompanying drawings are coordinated to elaborate for embodiment, but described specific embodiment is only explaining this
Invention, is not used to limit the present invention, and the description of structure operation is not used to limit the order that its is performed, it is any by element again
The structure of combination, it is produced that there is equal and other effects device, it is all the scope that disclosure of the present invention is covered.
In addition, accompanying drawing is only to be schematically illustrated, and drawn not according to its full-size(d).And on this
" electric connection " or " electric property coupling " used in text, can refer to two or multiple element it is physically in electrical contact or indirectly electrical
Contact.
In word (terms) used in full piece specification and claim, in addition to having and especially indicating, generally have
Each word using in the content invented in this area, at this with the usual meaning in special content.It is some describing this
The word of invention by it is lower or this specification other places discuss, to provide those skilled in the art in description for the present invention
Upper extra guiding.
Referring to Fig. 1, Fig. 1 illustrates the schematic diagram of the driving array 100 and display panel 110 of one embodiment of the invention.
In Fig. 1, driving array 100 includes multiple drive power unit, such as driver element D [N-1], D [N], D [N+1], D [N+2] etc.
It is the positive integer more than or equal to 2 Deng, wherein N.For example, when N is 2, then driver element D [N-1] is first order driving
Cells D [1], and driver element D [N] is second level driver element D [2], the rest may be inferred.
Display panel 110 includes multirow pixel, such as row pixel PX [N-1], PX [N], PX [N+1], PX [N+2] etc.,
Wherein each row pixel is driven by each self-corresponding one-level driver element respectively.For example, driver element D [N] is driving
Corresponding row pixel PX [N], driver element D [N+1] is to drive corresponding row pixel PX [N+1], and the rest may be inferred.Often row pixel
It is made up of multiple pixel electrodes, what the scanning signal and data circuit (not shown) provided with the driver element corresponding to provided
Data-signal drive it is luminous, this be display panel general principle, will not separately repeat herein.
It should be understood that the quantity of driver element and the line number of pixel in display panel 110 can be according to realities in driving array 100
Border application is adjusted, and the present invention is not any limitation as.For example, when the resolution of display panel 110 is 1024 × 768 pixels
When, then display panel 110 has 768 row pixels (PX [1]~PX [768]), or, when the resolution of display panel 110 is
During 1920 × 1080 pixel, then display panel 110 has 1080 row pixels (PX [1]~PX [1080]).In general, single drive
For moving cell to drive single one-row pixels, i.e. driver element quantity is equal with the line number of pixel, and so it is single not limit driving by the present invention
The line number of first quantity and pixel must be equal.
In Fig. 1 embodiment, display panel 110 is active matrix organic LED (Active-matrix
Organic light-emitting diode, AMOLED) panel.In AMOLED panel, pixel usually requires two (or two
More than individual) scanning signal to drive, therefore, in this example, drive each driver element in array 100 (such as D [N-1], D
[N], D [N+1], D [N+2] etc.) the first scanning signal and the second scanning signal can be produced respectively to drive each self-corresponding one
Row pixel.Specifically, first order driver element D [1] is producing the first scanning signal S1 [1] and the second scanning signal S2
[1] to row pixel PX [1], second level driver element D [2] is producing the first scanning signal S1 [2] and the second scanning signal S2
[2] to row pixel PX [2] etc., the rest may be inferred, then N levels driver element D [N] is producing the first scanning signal S1 [N] and
Two scanning signal S2 [N] to row pixel PX [N].It should be noted that it is according to face to drive the quantity of the scanning signal of one-row pixels
Plate type is adjusted, and the present invention is illustrated only by taking two scanning signals as an example with simplifying, and in practical application, drives sweeping for single one-row pixels
The quantity for retouching signal can be more than one or two.
Hold example, driver element (such as D [N-1], D [N], D [N+1], D [N+2]) shared control signals Ctrl at different levels with
And voltage stabilizing control signal XCtrl, and each receive previous stage driver element caused by shift signal, wherein control signal Ctrl with
Voltage stabilizing control signal XCtrl is anti-phase.For example, second level driver element D [2] receives first order driver element D [1] and produced
Shift signal G [1], third level driver element D [3] receives shift signal G [2] caused by second level driver element D [2], according to
This analogizes, then N levels driver element D [N] receives shift signal G [N-1] caused by (N-1) level driver element D [N-1].And
For first order driver element D [1], its shift signal received is the enabling signal that panel chip (not shown) provides
VST(G[0])。
In addition, as shown in figure 1, (N-1) level driver element D [N-1] more receives the 3rd clock signal CK3, the first clock pulse
Signal CK1 and periodic signal ENB, N level driver element D [N] receives the first clock signal CK1, the second clock signal CK2 and week
Phase signal ENA, (N+1) level driver element D [N+1] receive the second clock signal CK2, the 3rd clock signal CK3 and cycle letter
Number ENB, and (N+2) level driver element D [N+2] receives the 3rd clock signal CK3, the first clock signal CK1 and periodic signal
ENA, sequentially analogize, it is known that (N+3) level driver element D [N+3] receive the first clock signal CK1, the second clock signal CK2 and
Periodic signal ENA, (N+4) level driver element D [N+4] receive the second clock signal CK2, the 3rd clock signal CK3 and cycle
Signal ENB etc..
Wherein the second clock signal CK2 impulse waveform is substantially similar to the first clock signal CK1, and the second clock signal
CK2 pulsed time point (falling edge and rising edge) falls behind mono- unit interval of the first clock signal CK1.Yu Yishi
Apply in example, if being the second clock signal CK2 by the first clock signal CK1 one unit interval of delay.When similarly, by second
Arteries and veins signal CK2 postpone a unit interval be the 3rd clock signal CK3, and by periodic signal ENA postpone a unit when
Between be another periodic signal ENB.In addition, it is the first clock pulse that the 3rd clock signal CK3 is postponed into a unit interval i.e. reply
Signal CK1, it is periodic signal ENA that periodic signal ENB is postponed into a unit interval i.e. reply.In being illustrated more than, when first
Relation between arteries and veins signal CK1, the second clock signal CK2, the 3rd clock signal CK3, periodic signal ENA and periodic signal ENB
Merely illustrative, the present invention is not limited.
Example is held, for example, when N is 2, as first order driver element D [1] receives the 3rd clock signal CK3, the
One clock signal CK1 and periodic signal ENB；Second level driver element D [2] receives the first clock signal CK1, the second clock signal
CK2 and periodic signal ENA；Third level driver element D [3] receives the second clock signal CK2, the 3rd clock signal CK3 and cycle
Signal ENB；And fourth stage driver element D [4] receives the 3rd clock signal CK3, the first clock signal CK1 and periodic signal ENA
Etc..
First clock signal CK1, the second clock signal CK2, control signal Ctrl, voltage stabilizing control signal XCtrl, cycle letter
Number ENA and enabling signal VST is all as produced by panel chip.On each driver element in detail make mechanism please also refer to
2nd~3 figure.
Fig. 2 illustrates driver element D [N] detailed circuit diagram.In an embodiment, driver element D [N] includes shift register
Device SR1, first control circuit CT1, second control circuit CT2 and reference voltage input block PH1.Wherein first control circuit
CT1 through control to export the first scanning signal S1 [N], and second control circuit CT2 believes to be scanned through control output second
Number S2 [N].It should be understood that second control circuit CT2 is selective circuit, when row pixel PX [N] is according to panel species only need
When wanting single scanning signal can drive, then driver element D [N] and it is not required to set second control circuit CT2.
Specifically, first control circuit CT1 controls whether driver element D [N] exports first according to control signal Ctrl
Scanning signal S1 [N].Wherein first control circuit CT1 has first switch unit M1, second switch unit M2 and voltage stabilizing element
S1.First switch unit M1 has input I1, output end O1 and control terminal G1.Output end O1 couples the row of display panel 110
Pixel PX [N].Second switch unit M2 has input I2, output end O2 and control terminal G2, and wherein input I2 receives first
Clock signal CK1, output end O2 are coupled to first switch unit M1 input I1, control terminal G2 receive control signal Ctrl with
Whether control second switch unit M2 by the first clock signal CK1 is conducted to first switch unit M1.
Voltage stabilizing element S1 is connected with first switch unit M1 input I1 and receives reference voltage VGH, to according to steady
Control signal XCtrl is pressed, stable ginseng is provided when first switch unit M1 input I1 potential fluctuation (floating)
Examine voltage VGH.Wherein reference voltage VGH is to determine voltage source.Voltage stabilizing element S1 is a selection element, in some cases, because
For first switch unit M1 input I1 current potential be considered as fixation do not float, then voltage stabilizing element S1 need not can be set.
Similar to first control circuit, second control circuit CT2 is equally to control driver element D according to control signal Ctrl
Whether [N] exports the second scanning signal S2 [N].Wherein second control circuit CT2 has the 3rd switch element M3, the 4th switch single
First M4 and voltage stabilizing element S2.3rd switch element M3 has input I3, output end O3 and control terminal G3.Output end O3 and output
End O1 equally couples the same one-row pixels PX [N] of display panel 110.4th switch element M4 has input I4, output end O4
And control terminal G4, wherein input I4 receive periodic signal ENA, output end O4 is coupled to the input I3 of the 3rd switch element,
Control terminal G4 receives control signal Ctrl to control whether the 4th switch element M4 is conducted to the 3rd switch list by periodic signal ENA
First M3.Voltage stabilizing element S2 is connected with the 3rd switch element M3 input I3 and receives reference voltage VGH, and according to voltage stabilizing control
Signal XCtrl output reference voltages VGH processed to the 3rd switch element M3 input I3.Voltage stabilizing element S2 and voltage stabilizing element S1 are same
Sample is selection element.
Shift registor SR1 have temporary node P1, switch element M5, switch element M6, wherein switch element M6 to
Receive the shift signal G [N-1] of previous stage driver element D [N-1] outputs, and control terminal, first switch with switch element M5
Unit M1 control terminal G1 and the 3rd switch element M3 control terminal G3 are connected at temporary node P1.Switch element M6's is defeated
Enter end to be connected with control terminal, as a single-way switch.Wherein switch element M6 is not necessarily required to as single-way switch, can also be three
End element.When shift signal G [N-1] is produced, switch element M6 is switched on so that temporary node P1 keeps in this shift signal G
[N-1], and further turn on switch element M5, first switch unit M1 and the 3rd switch element M3.Switch element M5 receives the
One clock signal CK1, therefore when switch element M5 is switched on, the first clock signal CK1 of triggering is passed through switch element M5's
Output end O5 exports the shift signal G [N] as next stage driver element D [N+1].
Reference voltage input block PH1 has switch element M7~M12 and electric capacity C1.Wherein switch element M8 control terminal
And output end (i.e. temporary node P1) of the switch element M9 output end all with shift registor SR1 switch element M6 electrically connects
Connect, switch element M10 output end and switch element M5 output end O5 are electrically connected with, switch element M11 output end and the
One switch element M1 output end O1 is electrically connected with, and switch element M12 output end and the 3rd switch element M3 output end
O3 is electrically connected with.
Reference voltage input block PH1 is to according to the second clock signal CK2 offer reference voltage VGH to shift registor
SR1, first switch unit M1 and the 3rd switch element M3.Wherein switch element M7 control terminal is connected with input, as one
Single-way switch, and to receive the second clock signal CK2.Switch element M7 output end is defeated in node Q and switch element M8's
Go out end to be connected.Switch element M9~M12 control terminal is all connected to node Q, to be controlled by node Q current potential to turn on or close
It is disconnected.Electric capacity C1 one end also connects node Q processed.Switch element M8~M12 input and the electric capacity C1 other end all receive ginseng
Examine voltage VGH.When switch element M9~M12 is turned on, reference voltage VGH will be conducted to temporary by switch element M9~M12
Node P1, output end O5, output end O1 and output end O3, make temporary node P1, output end O5, output end O1 and output end O3
Current potential is all changed to reference voltage VGH current potential.
In an embodiment, above-mentioned each switch element M1~M12 and voltage stabilizing element S1, S2 are, for example, NMOS (n-type
MOSFET) switch or PMOS (p-type MOSFET) switches, for convenience of description, will be all with each switch element M1~M12 hereafter
Exemplified by PMOS switch.Wherein PMOS switch system turns on according to low voltage level signal, and is closed according to high-voltage level signal
It is disconnected.
It should be understood that each driver element (such as D [N-1], D [N+1], D [N+2]), which all has, is same as what Fig. 2 was illustrated
Driver element D [N] circuit framework.Wherein, in driver element D [N-1] circuit, switch element M2 and switch element M5 connect
The 3rd clock signal CK3 is received, switch element M4 receives periodic signal ENB；In driver element D [N+1] circuit, switch element
M2 and switch element M5 receives the second clock signal CK2, and switch element M4 receives periodic signal ENB；And in driver element D [N+
2] in circuit, switch element M2 and switch element M5 receive the 3rd clock signal CK3, and switch element M4 receives periodic signal
ENA.Please refer to Fig. 2 and Fig. 3.
Fig. 3 illustrates the timing waveform of the driving array 100 of one embodiment of the invention.In Fig. 3 timing waveforms, in
During period T1, driver element D [N-1] produces shift signal G [N-1] to driver element D [N].Shift signal G [N-1] is an arteries and veins
Signal is rushed, therefore, driver element D [N] shift registor SR1 switch element M6 turns in period T1, makes temporary node P1
Temporary this shift signal G [N-1] current potential.
Meanwhile first switch unit M1, the second control in driver element D [N] switch element M5 and first control circuit CT1
3rd switch element M3 is switched on according to temporary node P1 current potential in circuit CT2 processed.In addition, in period T1, workingstorage section
Point P1 current potential also causes reference voltage input block PH1 switch element M8 to turn on, and reference voltage VGH enters driver element D
The node Q of [N].In this example, reference voltage VGH is that high-voltage level determines voltage source, therefore node Q current potential is promoted to reference
Voltage VGH current potential is so that PMOS switch unit M9~M12 is turned off.In addition, reference voltage VGH can be coupled with auxiliary by electric capacity C1
Help node Q current potential stable in high-voltage level.
Then, when period T2, the first clock signal CK1 and periodic signal ENA is in low voltage level and the second clock pulse
Signal CK2 is in high-voltage level, and therefore, driver element D [N] switch element M5 is by now the first clock signal CK1 electricity
It is shift signal G [N] positioned at output end O5 outputs.Wherein, by can be seen that in Fig. 3, shift signal G [N] waveform relatively shifts letter
Number G [N-1] one unit interval of waveform delay.
And in period T2, control signal Ctrl switches to low voltage level from high-voltage level, and voltage stabilizing control signal
XCtrl switches to high-voltage level, therefore driver element D [N] second switch unit M2 conductings, voltage stabilizing member from low voltage level
Part S1 is turned off, and makes the first clock signal CK1 by second switch unit M2 and first switch unit M1 to be exported in output end O1
Produce the first scanning signal S1 [N].
In Fig. 2 embodiment, believed by second switch unit M2 and first switch unit M1 and the caused first scanning
Number S1 [N] will be sent to the effective display area domain of display panel 110 (Active Area, figure in do not show), and to drive effectively
Each pixel in viewing area, therefore, second switch unit M2 and first switch unit M1 preferably and can be provided using driving force
The transistor unit of larger output current.In an embodiment, second switch unit M2 and first switch unit M1 use element
Larger-size transistor, to reach larger output current, that is to say, that second switch unit M2 and first switch unit M1
Component size be more than switch element M5~M12 component size (as shown in Figure 2).In another embodiment, second switch list
First M2 and first switch unit M1 uses the crystalline substance of low temperature polycrystalline silicon (Low Temperature Poly-silicon, LTPS) framework
Body pipe, second switch unit M2 and first switch unit M1 is set to provide larger driving electricity using low temperature polycrystalline silicon framework
Stream.The present invention is not limited in the above described manner, and second switch unit M2 and first switch unit M1 can use other crystal
Tube elements.
Simultaneously, driver element D [N] voltage stabilizing element S2 also turns off according to voltage stabilizing control signal XCtrl, and the 4th opens
Close unit M4 then to be turned on according to control signal Ctrl, periodic signal ENA is passed through the 4th switch element M4 and the 3rd switch element
M3 produces the second scanning signal S2 [N] to be exported in output end O3.
In Fig. 2 embodiment, believed by the 4th switch element M4 and the 3rd switch element M3 and the caused second scanning
Number S2 [N] will be sent to the effective display area domain (not shown) of display panel 110, and each in effective display area domain to drive
Pixel, therefore, the 4th switch element M4 and the 3rd switch element M3 use driving force preferably and can provide larger output current
Transistor unit.Similar to above-mentioned second switch unit M2 and first switch unit M1, in an embodiment, the 4th switch is single
First M4 and the 3rd switch element M3 component size are more than switch element M5~M12 component size (as shown in Figure 2).In another
In embodiment, the 4th switch element M4 and the 3rd switch element M3 use the transistor of low temperature polycrystalline silicon (LTPS) framework.Originally take off
Show that file is not limited in the above described manner, the 4th switch element M4 and the 3rd switch element M3 can use other transistors member
Part.
In addition, during period T2, the input without shift signal G [N-1], therefore driver element D [N] switch element M8 is closed
Disconnected, node Q current potential still maintains high potential during previous period (T1), and reference voltage VGH is coupled by electric capacity C1 to aid in
Node Q current potential is stablized in high-voltage level, switch element M9~M12 in reference voltage input block PH1 is maintained shut-off.
In period T3, the first clock signal CK1 and periodic signal ENA is in high-voltage level and the second clock signal
CK2 is in low voltage level, and therefore, switch element M7 is turned in driver element D [N] reference voltage input block PH1, makes the
Two clock signal CK2 are conducted to node Q further to turn on switch element M9~M12.Because switch element M9 is switched on, with reference to electricity
Pressure VGH is conducted to temporary node P1, turns off switch element M5, first switch unit M1 and the 3rd switch element M3.And because opening
Close unit M10~M12 to be switched on, reference voltage VGH will be turned on to output end O5, output end O1, output end O3, believe displacement
Number G [N], the first scanning signal S1 [N] and the second scanning signal S2 [N] stop output.
See period T4.In period T4, previous stage driver element D [N-1] output shift signal G [N-1] are single to driving
First D [N], therefore driver element D [N] switch element M6 is turned on again, further such that switch element M5, first switch unit
M1 and the 3rd switch element M3 are also turned on again.Then, when period T5, the first clock signal CK1 is in low voltage level, because
It is shift signal G [N] that this switch element M5, which exports the first clock signal CK1,.
It should be noted that in period T5, control signal Ctrl is in high-voltage level and voltage stabilizing control signal XCtrl is in
Low voltage level, therefore driver element D [N] second switch unit M2 and the 4th switch element M4 are all turned off, and voltage stabilizing element
S1 and voltage stabilizing element S2 conductings.When voltage stabilizing element S1 and voltage stabilizing element S2 is turned on, reference voltage VGH passes through first switch unit
M1, therefore first switch unit M1 output end O1 potential change is to reference voltage VGH current potential.
Then, period T6, the second clock signal CK2 are in low voltage level, make driver element D [N] reference voltage defeated
Enter unit PH1 starts to stop shift signal G [N] output.
Driver element D [N] is same as, as period T2, when shift signal G [N] is produced, the driver element D [N+1] of next stage
It is also started up, to produce shift signal G [N+1] and the first scanning signal S1 [N+ according to the second clock signal CK2 in period T3
1], and according to periodic signal ENB the second scanning signal S2 [N+1] is produced.By can be seen that in Fig. 3, shift signal G [N+1],
Scan signal S1 [N+1] and the second scanning signal S2 [N+1] waveform fall behind shift signal G [N], the first scanning signal respectively
S1 [N] and the second scanning signal S2 [N] one unit interval of waveform.
And during period T5, driver element D [N+1] is activated also according to shift signal G [N] caused by previous stage, with
Period T6 produces shift signal G [N+1] according to the second clock signal CK2.And similarly, since control signal Ctrl is in period T6
Low voltage level is in high-voltage level and voltage stabilizing control signal XCtrl, makes driver element D [N+1] that first can not be exported
Scanning signal S1 [N+1] and the second scanning signal S2 [N+1], as shown in Figure 3.
From above-mentioned start, in period T2, T3, because control signal Ctrl is in low voltage level, therefore driver element D
[N], D [N+1] can produce respective first scanning signal (S1 [N], S1 [N+1]) and the second scanning signal (S2 [N], S2 [N+
1]), and in period T5, T6, then because control signal Ctrl is in high-voltage level, therefore driver element D [N], D [N+1] nothing
Method produces respective first scanning signal (S1 [N], S1 [N+1]) and the second scanning signal (S2 [N], S2 [N+1]).Therefore, by
By adjustment control signal Ctrl current potential, it can be achieved whether control driver elements at different levels drive corresponding row in display panel 110
Pixel.
Referring to Fig. 4, Fig. 4 illustrates the timing waveform of the driving array 100 of one embodiment of the invention.In Fig. 4, clock pulse
Signal CK1/CK2/CK3 timing waveform is shown as the first clock signal CK1, the second clock signal CK2 and the 3rd clock signal
CK3 overlapping waveform, periodic signal ENA/ENB timing waveform are shown as periodic signal ENA and ENB overlapping waveform, displacement
Signal G [K] timing waveform shows such as first order driver element D [1] to each output of such as the tenth grade of driver element D [10]
Shift signal G [1]~G [10] overlapping waveform, the first scanning signal S1 [K] timing waveform shows such as first order driving
Cells D [1] to such as the first scanning signal that the tenth grade of driver element D [10] each exports overlapping waveform, and second scanning
Signal S2 [K] timing waveform shows that such as first order driver element D [1] is each defeated to such as the tenth grade of driver element D [10]
The overlapping waveform of the second scanning signal gone out.
In Fig. 4 embodiment, the mechanism of driver elements at different levels is controlled by aforementioned control signals Ctrl, control can be achieved
Part driver element produces the first scanning signal and the second scanning signal, and suppresses remaining driver element and do not produce the first scanning letter
Number and the second scanning signal.For example, in Fig. 4, it is assumed that between period T7~T9, driver element D [1]~D [10] is sequentially
Start is produced with the clock signal (the first clock signal CK1, the second clock signal CK2 or the 3rd clock signal CK3) corresponding to
Raw shift signal G [1]~G [10].In wherein period T7 and period T9, control signal Ctrl is in high-voltage level and voltage stabilizing control
Signal XCtrl processed is in low voltage level, and in period T8, control signal Ctrl is in low voltage level and voltage stabilizing control signal
XCtrl is in high-voltage level.
In period T7 and T9, although driver element D [1]~D [2], D [8]~D [10] can still produce shift signal G [1]
~G [2], G [8]~G [10], but because control signal Ctrl is in high-voltage level, make driver element D [1] in this two period
~D [2], D [8]~D [10] respective second switch unit M2 and the 4th switch element M4 are turned off, then driver element D [1]~D
[2], D [8]~D [10] can not export the scanning letters of the first scanning signal S1 [1]~S1 [2] and S1 [8]~S1 [10] and second
Number S2 [1]~S2 [2] and S2 [8]~S2 [10].
And in the T8 periods, driver element D [3]~D [7] produces shift signal G [3]~G [7], and in this period, because
Control signal Ctrl is in low voltage level, and the switches of driver element D [3]~respective second switch unit M2 of D [7] and the 4th are single
First M4 is switched on, then driver element D [3] produces the first scanning signal according to the second clock signal CK2 and periodic signal ENB respectively
S1 [3] and the second scanning signal S2 [3], driver element D [4] produce according to the 3rd clock signal CK3 and periodic signal ENA respectively
First scanning signal S1 [4] and the second scanning signal S2 [4], driver element D [5] is respectively according to the first clock signal CK1 and week
Phase signal ENB produce the first scanning signal S1 [5] and the second scanning signal S2 [5], driver element D [6] respectively according to second when
Arteries and veins signal CK2 and periodic signal ENA produces the first scanning signal S1 [6] and the second scanning signal S2 [6], driver element D [7] points
The first scanning signal S1 [7] and the second scanning signal S2 [7] is not produced according to the 3rd clock signal CK3 and periodic signal ENB.
Thereby, by control signal Ctrl, controllable portion driver element (such as D [3]~D [7]) produces the first scanning
Signal (S1 [3]~S1 [7]) and the second scanning signal (S2 [3]~S2 [7]), and part driver element (such as D [1]~D [2],
D [8]~D [10]) the first scanning signal (S1 [1]~S1 [2], S1 [8]~S1 [10]) and the second scanning signal (S2 are not exported
[1]~S2 [2], S2 [8]~S2 [10]).Therefore, row pixel (such as the corresponding driving that can make to need in new frame to be updated
Cells D [3]~D [7] the third line pixel PX [3]~the 7th row pixel PX [7]) it is updated, remaining row pixel can not then update
To maintain the picture of previous frame, make the power consumption of display panel 110 can farthest lower.
In the present invention, driver element D [N] circuit framework is not limited with the embodiment shown in Fig. 2.Fig. 5 illustrates basis
Driver element D [the N] ' circuit framework in another embodiment of the present invention.Driver element D [N] ' equally has displacement in Fig. 5
Buffer SR2, first control circuit CT3, second control circuit CT4 and reference voltage input block PH2.Driver element D in Fig. 5
Shift registor SR2, first control circuit CT3, second control circuit CT4 and reference voltage input block PH2 in [N] ' its
Function is substantially similar to driver element D [N] shift registor SR1, first control circuit CT1, second in previous Fig. 2 with operation
Control circuit CT2 and reference voltage input block PH1 are similar.
In this instance, shift registor SR2 has switch element M7~M9.Switch element M9 is a single-way switch, to
Receive previous stage shift signal G [N-1], and switch element M7, M8 control terminal are in temporary node P1 places and switch element M9
Output end is connected.Wherein M9 is not necessarily required to as single-way switch, can also be three-terminal element, as long as specific period can be achieved in
Transmit the shift signal G [N-1] of previous stage.Switch element M7, M8 receive the first clock signal CK1 and periodic signal respectively
ENA.Wherein when switch element M9 turns on according to shift signal G [N-1], keep in node P1 receive shift signal G [N-1] so that
Switch element M7, M8 are turned on, and the first clock signal CK1 of triggering is exported as displacement letter by switch element M7 in the first output end O7
Number G [N], and triggering periodic signal ENA by switch element M8 in the second output end O8 outputs be shift signal H [N].
First control circuit CT3 controls whether driver element D [N] ' exports the first scanning signal according to control signal Ctrl
S1[N].Wherein first control circuit CT3 has first switch unit M1, second switch unit M2, the 3rd switch element M3 and steady
Press element S1.First switch unit M1 has input I1, output end O1 and control terminal G1.Input I1 receives the first clock pulse letter
Number CK1, output end O1 couple the row pixel PX [N] of display panel 110.Second switch unit M2 has input I2, output end
O2 and control terminal G2, wherein input I2 receive the first clock signal CK1, and output end O2 couples the control of first switch unit
Hold G2.
3rd switch element M3 has input I3, output end O3 and control terminal G3.Input I3 receives shift register
The shift signal G [N] of device SR2 outputs, output end O3 are coupled to second switch unit M2 control terminal G2, and control terminal G3 receives control
Whether signal Ctrl processed is sent shift signal G [N] to second switch unit M2's with controlling the 3rd switch element M3 to turn on
Control terminal G2.Voltage stabilizing element S1 is connected with second switch unit M2 control terminal G2 and receives reference voltage VGH.Wherein voltage stabilizing member
Control terminal G2s of the part S1 according to voltage stabilizing control signal XCtrl output reference voltages VGH to second switch unit M2.
Similar to first control circuit CT3, second control circuit CT4 driver element is controlled also according to control signal Ctrl
Whether D [N] ' exports the second scanning signal S2 [N].Wherein second control circuit CT4 has the 4th switch element M4, the 5th switch
Unit M5, the 6th switch element M6 and voltage stabilizing element S2.4th switch element M4 has input I4, output end O4 and control terminal
G4.Input I4 receives periodic signal ENA, and output end O4 couples the row pixel PX [N] of display panel 110.5th switch element
M5 has input I5, output end O5 and control terminal G5, and wherein input I5 receives periodic signal ENA, output end O5 couplings
4th switch element M4 control terminal G4.
6th switch element M6 has input I6, output end O6 and control terminal G6.Input I6 receives shift register
The shift signal H [N] of device SR2 outputs, output end O6 are coupled to the 5th switch element M5 control terminal G5, and control terminal G6 receives control
Whether signal Ctrl processed is sent shift signal H [N] to the 5th switch element M5's with controlling the 6th switch element M6 to turn on
Control terminal G5.Voltage stabilizing element S2 is connected with the 5th switch element M5 control terminal G5 and receives reference voltage VGH.Wherein voltage stabilizing member
Part S2 is according to voltage stabilizing control signal XCtrl output reference voltages VGH to the 5th switch element M5 control terminal G5.
Reference voltage input block PH2 has switch element M10~M20.Wherein switch element M11 control terminal and switch
Unit M10 output end is all electrically connected with shift registor SR2 switch element M9 output end (i.e. temporary node P1), is opened
Close unit M13 output end to be electrically connected with switch element M8 output end (i.e. the second output end O8), switch element M14's is defeated
Go out end and switch element M7 output end (i.e. the first output end O7) is electrically connected with, switch element M15 output end is opened with first
The control terminal G for closing unit M1 is electrically connected with, and switch element M16 and switch element M17 output end are with first switch unit M1's
Output end O1 is electrically connected with, and switch element M18 output end and the 4th switch element M4 control terminal G4 are electrically connected with, and switch is single
First M19 and switch element M20 output end is electrically connected with the 4th switch element M4 output end O4.
Reference voltage input block PH2 is to according to the second clock signal CK2 offer reference voltage VGH to shift registor
SR2, first switch unit M1 and the 4th switch element M4.Wherein switch element M10 control terminal is connected with input, as one
Single-way switch, and to receive the second clock signal CK2.Wherein M10 is not necessarily required to as single-way switch, can also be three end members
Part.Switch element M10 output end is connected in node Q with switch element M11 output end.Switch element M12~M16, M18~
M19 control terminal is all connected to node Q, and to be controlled by node Q current potential with or off, and switch element M17, M20 are then
It is controlled by voltage stabilizing control signal XCtrl.Switch element M11~M20 input all receives reference voltage VGH.Work as switch element
When M12~M20 is turned on, reference voltage VGH will be conducted to temporary node P1, output end O7, defeated by switch element M12~M20
Go out to hold O8, output end O1, control terminal G, output end O and control terminal G4, make temporary node P1, output end O7, output end O8, output
The current potential of O1, control terminal G, output end O and control terminal G4 each is held all to be changed to reference voltage VGH current potential.
It should be understood that in this example, each driver element (such as D [N-1], D [N+1], D [N+2]), which all has, to be same as
The circuit framework for the driver element D [N] ' that Fig. 5 is illustrated.Wherein, in driver element D [N-1] circuit, switch element M1, M2,
M7 receives the 3rd clock signal CK3, and switch element M4, M5, M8 receive periodic signal ENB；In driver element D [N+1] circuit
In, switch element M1, M2, M7 receive the second clock signal CK2, and switch element M4, M5, M8 receive periodic signal ENB；And driving
In moving cell D [N+2] circuit, switch element M1, M2, M7 receive the 3rd clock signal CK3, and switch element M4, M5, M8 are received
Periodic signal ENA.
Embodiment is held, each switch element M1~M20 is also said by taking PMOS switch as an example in Fig. 5 driver element D [N] '
It is bright, and Fig. 3 timing waveform is also applied to Fig. 5 driver element D [N] '.For example, when period T1, previous stage driving is single
First D [N-1] produces shift signal G [N-1] to driver element D [N] ', turns on shift registor SR2 switch element M9, temporarily
Deposit the current potential that node P1 keeps in this shift signal G [N-1].And according to temporary node P1 current potential, switch element M7, M8 are by simultaneously
Conducting, each to produce shift signal G [N] and displacement according to the first clock signal CK1 and periodic signal ENA respectively in period T2
Signal H [N] (not shown).
And during period T2, control signal Ctrl switches to low voltage level, therefore switch element M3 and switch element M6 are led
It is logical so that shift signal G [N], H [N] are respectively by the 3rd switch element M3 and switch element M6, and further conducting second is opened
Close unit M2 and the 5th switch element M5.Simultaneously as the first clock signal CK1 is in low voltage level, therefore the first clock signal
Control terminal G1s of the CK1 by second switch unit M2 to first switch unit M1, to turn on first switch unit M1.First switch
First clock signal CK1 is conducted to output end O1 to export the first scanning signal S1 [N] by unit M1.
In Fig. 5 embodiment, it will be sent to aobvious and caused first scanning signal S1 [N] by first switch unit M1
Show the effective display area domain (not shown) of panel 110, and to drive each pixel in effective display area domain, therefore, first opens
Unit M1 is closed to use driving force preferably and the transistor unit of larger output current can be provided.In an embodiment, first opens
Unit M1 is closed using the larger transistor (as shown in Figure 5) of component size, second switch unit among the embodiment compared to Fig. 2
M2 and first switch unit M1 uses the larger transistor of component size to produce the first scanning signal S1 [N], Fig. 5 implementation
Only first switch unit M1 uses the larger transistor of component size in example, more saves the space of circuit layout.In another reality
Apply in example, first switch unit M1 uses the transistor of low temperature polycrystalline silicon (LTPS) framework.The present invention is not in the above described manner
Limit, first switch unit M1 can use other transistor units.
Similarly, now periodic signal ENA is also low voltage level, therefore periodic signal ENA passes through the 5th switch element M5
To the 4th switch element M4 control terminal G4, to turn on the 4th switch element M4.4th switch element M4 leads periodic signal ENA
Output end O4 is passed to export the second scanning signal S2 [N].
In Fig. 5 embodiment, it will be sent to aobvious and caused second scanning signal S2 [N] by the 4th switch element M4
Show the effective display area domain (not shown) of panel 110, and to drive each pixel in effective display area domain, therefore, the 4th opens
Unit M4 is closed to use driving force preferably and the transistor unit of larger output current can be provided.In an embodiment, the 4th opens
Unit M4 is closed using the larger transistor (as shown in Figure 5) of component size, the 4th switch element among the embodiment compared to Fig. 2
M4 and the 3rd switch element M3 uses the larger transistor of component size to produce the second scanning signal S2 [N], Fig. 5 implementation
Only the 4th switch element M4 uses the larger transistor of component size in example, more saves the space of circuit layout.In another reality
Apply in example, the 4th switch element M4 uses the transistor of low temperature polycrystalline silicon (LTPS) framework.The present invention is not in the above described manner
Limit, the 4th switch element M4 can use other transistor units.
Then, in period T3, the first clock signal CK1 and periodic signal ENA are in high-voltage level and the second clock pulse is believed
Number CK2 is in low voltage level, and therefore, switch element M10 is turned in reference voltage input block PH2, makes the second clock signal
CK2 is conducted to node Q further to turn on switch element M12~M16, M18~M19.Because switch element M12 is switched on, reference
Voltage VGH is conducted to temporary node P1, turns off switch element M7, M8.And because switch element M13~M14 is switched on, with reference to electricity
Pressure VGH will be turned on to the first output end O7, the second output end O8, shift signal G [N], H [N] is stopped output.
In addition, reference voltage VGH is also conducted to first switch unit M1 by switch element M15~M16, M18~M19 respectively
Control terminal G1 and output end O1 and the 4th switch element M4 control terminal G4 and output end O4, first switch unit M1 and the 4th
Switch element M4 is closed end, and the first scanning signal S1 [N] and the second scanning signal S2 [N] stop output.
It should be noted that during period T3, voltage stabilizing control signal XCtrl is in low voltage level, therefore switch element M17 and opens
Unit M20 is closed to be switched on to further provide for reference voltage VGH to output end O1 and output end O4 respectively.Meanwhile voltage stabilizing element
S1 and voltage stabilizing element S2 is also switched on according to voltage stabilizing control signal XCtrl so that reference voltage VGH is by voltage stabilizing element S1 and surely
Element S2 is pressed to turn off second switch unit M2 and the 5th switch element M5.
Then, see period T4.During period T4, previous stage shift signal G [N-1] is produced again, makes driver element D [N] '
Switch element M7~M9 conductings, and displacement letter is produced according to the first clock signal CK1 and periodic signal ENA respectively in period T5
Number G [N], H [N].And control signal Ctrl during because of period T5 is in high-voltage level and voltage stabilizing control signal XCtrl is in
Low voltage level, second switch unit M3 and the 6th switch element M6 shut-offs, and voltage stabilizing element S1, S2 are turned on.Second switch list
First M2 and the 5th switch element M5 is then equally turned off because of the reference voltage VGH that voltage stabilizing element S1, S2 are provided.Meanwhile open
Close unit M17, M18 to be turned on according to voltage stabilizing control signal XCtrl, so that output end O1 and output end O4 current potential are pulled to reference
Voltage VGH current potential, the first scanning signal S1 [N] and the second scanning signal S2 [N] can not be exported.
In period T6, the second clock signal CK2 is in low voltage level, makes driver element D [N] ' reference voltage defeated
Enter unit PH2 starts to stop shift signal G [N] and H [N] output.
From the foregoing, Fig. 5 driver element D [N] ' also can decide whether that output first is swept according to control signal Ctrl
Signal S1 [N] and the second scanning signal S2 [N] are retouched with row pixel PX [N] corresponding to driving.Therefore, with Fig. 5 driver element D
The driving array 100 that [N] ' is formed can also realize partial scan technology as shown in Figure 4.
The driver element and driving array disclosed by file of the present invention, can be achieved the partial scan technology of display panel,
And because scanning signal is blocked by control circuit in advance before being generated, just hindered compared to after scanning signal is produced
The conventional art that scanning signal enters panel pixel is kept off, further reduces the consume of electric power.
Although embodiments of the invention are disclosed above, so it is not limited to the present invention, any to be familiar with this those skilled in the art,
Without departing from the spirit and scope of the present invention, when can do a little change and retouching, thus protection scope of the present invention when with
Appended claims, which define, to be defined.
Claims (12)
1. a kind of driver element, it is characterised in that include：
One first switch unit, there is an input, an output end and a control terminal；
One shift registor, there is a temporary node and an output end, wherein the temporary node is configured to temporarily store a shift signal, should
Temporary node is coupled to the control terminal of the first switch unit；And
One second switch unit, there is the input of an input, an output end and a control terminal, wherein the second switch unit
End receives one first clock signal, and the output end of the second switch unit is coupled to the input of the first switch unit,
The control terminal of the second switch unit receives a control signal to control whether the second switch unit is believed first clock pulse
Number it is conducted to the first switch unit.
2. driver element as claimed in claim 1, it is characterised in that the control signal that the second switch unit is received is consolidated
Switch due to one first level or between first level and a second electrical level, when the control signal is fixed on first level
When, the second switch unit is not turned on, when the control signal switches to the second electrical level from first level, the second switch
First clock signal is conducted to the first switch unit by unit, and the output end output one first of the first switch unit is swept
Retouch signal.
3. driver element as claimed in claim 1, it is characterised in that further include：
One voltage stabilizing element, it is connected with the input of the first switch unit, and receives a reference voltage, and according to a voltage stabilizing
Control signal exports the reference voltage to the input of the first switch unit；
Wherein the voltage stabilizing control signal is anti-phase with the control signal.
4. driver element as claimed in claim 1, it is characterised in that the shift registor is triggered according to the shift signal to incite somebody to action
First clock signal is sent to a shift registor of another driver element via the output end of the shift registor.
5. driver element as claimed in claim 1, it is characterised in that further include：
One reference voltage input block, with the temporary node of the shift registor and the output end and the first switch unit
The output end connects, to provide a reference voltage to the shift registor and the first switch list according to one second clock signal
Member；
The pulsed time point of wherein second clock signal falls behind the unit interval of the first clock signal one.
6. driver element as claimed in claim 1, it is characterised in that further include：
One the 3rd switch element, there is the control of an input, an output end and a control terminal, wherein the 3rd switch element
End is coupled to the temporary node；And
One the 4th switch element, there is the input of an input, an output end and a control terminal, wherein the 4th switch element
End receives a periodic signal, and the output end of the 4th switch element is coupled to the input of the 3rd switch element, and this
The control terminal of four switch elements receives the control signal to control whether the 4th switch element is conducted to the periodic signal
3rd switch element is so that the output end of the 3rd switch element exports one second scanning signal.
7. a kind of driver element, it is characterised in that the driver element includes：
One first switch unit, has an input, an output end and a control terminal, and the wherein input receives one first clock pulse
Signal；
One shift registor, there is a temporary node and one first output end, wherein the temporary node is configured to temporarily store displacement letter
Number；
One second switch unit, has an input, an output end and a control terminal, and this of the wherein second switch unit is defeated
Enter end and receive first clock signal, the output end of the second switch unit couples the control terminal of the first switch unit；
And
One the 3rd switch element, there is an input, an output end and a control terminal, wherein the shift registor is according to the shifting
Position signal triggering, should so that one first shift signal is sent to the input of the 3rd switch element via first output end
The output end of 3rd switch element is coupled to the control terminal of the second switch unit, the control terminal of the 3rd switch element
A control signal is received to control the 3rd switch element whether to turn on so that first shift signal is sent to the second switch
The control terminal of unit.
8. driver element as claimed in claim 7, it is characterised in that the control signal that the 3rd switch element is received is consolidated
Switch due to one first level or between first level and a second electrical level, when the control signal is fixed on first level
When, the 3rd switch element is not turned on, when the control signal switches to the second electrical level from first level, the 3rd switch
Unit sends first shift signal to the control terminal of the second switch unit, and the second switch unit is by first clock pulse
Signal conduction is to the control terminal of the first switch unit to turn on the first switch unit, the output end of the first switch unit
Export one first scanning signal.
9. driver element as claimed in claim 7, it is characterised in that further include：
One voltage stabilizing element, connect the control terminal of the second switch unit and receive a reference voltage, wherein the voltage stabilizing element root
According to a voltage stabilizing control signal by the control terminal of the reference voltage output to the second switch unit；
Wherein the voltage stabilizing control signal is anti-phase with the control signal.
10. driver element as claimed in claim 7, it is characterised in that the shift registor has more one second output end, should
Driver element further includes：
One the 4th switch element, there is the input of an input, an output end and a control terminal, wherein the 4th switch element
Receive a periodic signal；
One the 5th switch element, has an input, an output end and a control terminal, and this of wherein the 5th switch element is defeated
Enter end and receive the periodic signal, the output end of the 5th switch element couples the control terminal of the 4th switch element；And
One the 6th switch element, there is an input, an output end and a control terminal, wherein the shift registor is according to the shifting
Position signal triggering, should so that one second shift signal is sent to the input of the 6th switch element via second output end
The output end of 6th switch element is coupled to the control terminal of the 5th switch element, the control terminal of the 6th switch element
Receive the control signal and sent second shift signal to the 5th switch with controlling the 6th switch element whether to turn on
The control terminal of unit；
When five switching means conductives, the cycle clock signal is conducted to the 4th switch element by the 5th switch element
Control terminal to turn on the 4th switch element, the output end of the 4th switch element exports one second scanning signal.
11. one kind driving array, it is characterised in that to drive a display panel, the driving array includes：
Multiple driver elements, respectively to drive one-row pixels corresponding in the display panel, those driver elements each wrap
Contain：
One first switch unit, has an input, an output end and a control terminal, and the output end couples phase in the display panel
The corresponding row pixel；
One shift registor, there is a temporary node and an output end, wherein the temporary node is configured to temporarily store a shift signal, should
Temporary node is coupled to the control terminal of the first switch unit；And
One second switch unit, there is the input of an input, an output end and a control terminal, wherein the second switch unit
End receives one first clock signal, and the output end of the second switch unit is coupled to the input of the first switch unit,
The control terminal of the second switch unit receives a control signal to control whether the second switch unit is believed first clock pulse
Number it is conducted to the first switch unit.
12. driving array as claimed in claim 11, it is characterised in that respective second switch in the plurality of driver element
The control signal that unit is received is fixed on one first level or switched between first level and a second electrical level, when this
, should one of them drive when the control signal corresponding to one of multiple driver elements driver element is fixed on first level
The second switch unit of moving cell is not turned on, when this one of them control signal corresponding to driver element is from first level
When switching to the second electrical level, first clock signal is conducted to this by the second switch unit for being somebody's turn to do one of them driver element
First switch unit, the output end of the first switch unit export scan signal row corresponding into the display panel
Pixel.
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Cited By (1)
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| CN111341250A (en) * | 2019-03-07 | 2020-06-26 | 友达光电股份有限公司 | Shift register and electronic device |
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| TWI714365B (en) * | 2019-03-07 | 2020-12-21 | 友達光電股份有限公司 | Shift register and electronic apparatus having the same |
| TWI740596B (en) * | 2019-11-22 | 2021-09-21 | 友達光電股份有限公司 | Shift register and electronic apparatus having the same |
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| CN111341250A (en) * | 2019-03-07 | 2020-06-26 | 友达光电股份有限公司 | Shift register and electronic device |
| CN111341250B (en) * | 2019-03-07 | 2021-05-14 | 友达光电股份有限公司 | Shift register and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107644622B (en) | 2020-04-14 |
| TWI616866B (en) | 2018-03-01 |
| TW201913634A (en) | 2019-04-01 |
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