CN107634768B - FPGA-based (field programmable Gate array-based) MWC (Multi-media wall) compression sampling broadband digital receiver PDW (Polymer dispersed W) forming method - Google Patents
FPGA-based (field programmable Gate array-based) MWC (Multi-media wall) compression sampling broadband digital receiver PDW (Polymer dispersed W) forming method Download PDFInfo
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Abstract
The invention provides a FPGA-based (field programmable gate array-based) MWC (multi-media wire) compression sampling broadband digital receiver PDW (pulse width modulation) forming method, belonging to the field of electronic countermeasure in information and communication engineering. Firstly, signals are moved to a baseband through a frequency mixing module, baseband compression sampling signals are obtained through a low-pass filter, and then speed reduction extraction is carried out, so that the data volume is greatly reduced, and hardware implementation is facilitated. And inputting the extracted signals into a CORDIC module to extract amplitude and phase, measuring the frequency of a sub-band by using a phase difference frequency measurement method, and calculating the sub-band of the signals by using a multi-channel signal parallel channelization mode through a frequency calculation module to obtain the absolute carrier frequency of the signals. And (4) extracting the pulse by a threshold decision method, and calculating the arrival time and the disappearance time of the signal extracted by the pulse to obtain the pulse width. The invention verifies the feasibility of forming physical realization of the PDW data of the MWC compression sampling structure-based digital receiver, and lays a theoretical and hardware realization foundation for the subsequent FPGA realization of the whole system based on the novel receiver.
Description
Technical Field
The invention belongs to the field of electronic countermeasure in information and communication engineering, and particularly relates to a method for realizing a novel digital receiver based on MWC compression sampling by utilizing an FPGA (field programmable gate array), carrying out under-Nyquist sampling on a broadband intermediate-frequency signal and generating a corresponding PDW (product data word), wherein the generated PDW is used for sorting and identifying subsequent electronic reconnaissance.
Background
For the currently commonly used low interception probability (LPI) signals (including chirp modulation (LFM) signals, phase-coded (PSK) signals, frequency-coded (FSK) signals, etc.) and frequency-agile signals, the receiving bandwidth of the wideband digital receiver usually contains a plurality of sub-signals with different carrier frequency positions and different bandwidths, even the carrier frequency positions and bandwidths of the sub-signals are time-varying. In the traditional uniform channelization structure, the sub-band division is blind, and the sub-band bandwidth cannot be changed after the sub-band division is determined, so that the problem of channel crossing is caused when a signal is received, the digital signal processing is complex, the sub-band bandwidth is increased, the sensitivity of a receiver is greatly reduced, and the signal-to-noise ratio improvement effect is reduced.
From the literature on the current research of new channelization structures, most of the research is on how to solve the problems of uniform channelization structures by using non-uniform channelization structures, but the channel division is always fixed and has no adaptive capability. The theory of compressive sampling has been studied intensively in this year. The MWC structure proposed by Mishali m. et al in 2010 is the most successful compressive sampling structure at present, and was successfully expanded to the discrete digital domain by the cheng subject group of harabin engineering university in 2016, and used for the design of wideband digital receivers. The receiver structure utilizes the characteristic of frequency domain sparse signals to realize Sub-Nyquist sampling, saves storage space, reduces the number of branch paths, reduces the complexity of a system and successfully solves the problem of channel crossing. But the research is still in the stages of theoretical research and software simulation.
The MWC structure-based compressed sampling broadband digital receiver is successfully built on an FPGA of Xilinx company, carrier frequency, pulse width and arrival time obtained by an input signal are simulated and verified by utilizing Vivado software self-contained simulation capability, and the correctness and feasibility of realizing the MWC structure-based broadband digital receiver by using the FPGA and forming PDW data are verified through verification that the signal information of the input signal is basically consistent with that of the input signal.
Disclosure of Invention
The invention provides a method for forming PDW (pulse width modulation) of an MWC (multi-media wire) compression sampling broadband digital receiver based on an FPGA (field programmable gate array), which is applied to an electronic reconnaissance system and aims to provide a method for generating PDW data on the FPGA by the MWC compression sampling structure based broadband digital receiver and verify feasibility.
The purpose of the invention is realized as follows: (1) the signal is input into a frequency mixing module and multiplied by a Bernoulli pseudo-random sequence and then output to a low-pass filtering module; (2) extracting a baseband signal from the low-pass filtering module and outputting the baseband signal to a speed reduction extraction module; (3) performing corresponding multiple extraction on the signals in the speed reduction extraction module to reduce the data volume and outputting the signals to the CORDIC module; (4) calculating the amplitude and the phase of the signal in a CORDIC module; (5) outputting the amplitude to a pulse extraction module for pulse extraction and outputting to an arrival time measurement module for measuring the arrival time of the pulse; (6) then outputting the amplitude to a pulse width measurement module, and calculating the pulse width in the pulse width measurement module; (7) outputting the phase to a phase difference frequency measurement module, and measuring the relative frequency of a sub-band; (8) and inputting the DTFT of each sub-channel signal into an absolute frequency measurement module to calculate the sub-channel number of the signal, so as to calculate the true carrier frequency of the signal.
The invention is applicable to the following conditions:
(1) inputting signal pulse compression radar signals, wherein the signal pulse compression radar signals comprise conventional radar signals, two-phase encoding signals, four-phase encoding signals, linear frequency modulation signals, frequency agility signals, non-linear frequency modulation signals and frequency encoding signals;
(2) the sampling sequence of the analog signal x (n) satisfies the nyquist sampling theorem and can be AD-collected as a digital signal.
Compared with the prior art, the method provided by the invention has the beneficial effects that: the broadband digital receiver based on the MWC compression sampling structure is realized on the FPGA platform, corresponding PDW data is successfully obtained, feasibility of physical realization of the novel digital receiver structure is verified, and a certain foundation is laid for subsequent FPGA realization of the whole electronic reconnaissance system based on the novel receiver.
Drawings
FIG. 1 is a block diagram of the overall system flow;
FIG. 2 is a simulation diagram of the output of the FPGA mixing module;
FIG. 3 is a diagram of a low-pass FIR filter polyphase structure;
FIG. 4 is a simulation diagram of the output of the FPGA low pass filter module;
FIG. 5 is a simulation diagram of the output of the FPGA slowdown extraction module;
FIG. 6 is a simulation diagram of the output of the FPGA Cordic module;
FIG. 7 is a simulation diagram of FPGA phase difference frequency measurement output;
FIG. 8 is a simulation diagram of FPGA pulse extraction and pulse width measurement output.
Detailed Description
The method provided by the invention is further described with reference to the accompanying drawings:
the invention is realized based on FPGA, and the basic flow comprises the following nine modules: the device comprises a frequency mixing module, a low-pass filtering module, a speed reduction extraction module, a CORDIC module, a phase difference frequency measurement module, a pulse extraction module, an arrival time measurement module, a pulse width measurement module and an absolute frequency measurement module, which are shown in figure 1. The first 8 modules are described with a one-way channelization structure and the 9 th module is described with a multi-way channelization structure.
1) Frequency mixing module
The frequency mixing module has the functions of: multiplying the input signal by a random Bernoulli sequence distributed at random of +/-1, performing convolution operation on a frequency domain in reality, performing frequency spectrum shifting, and shifting the sparse input signal on the frequency domain to a baseband.
The signal to be tested is a complex exponential signal with the sampling frequency of 200MHz, the signal-to-noise ratio of 15dB, the carrier frequency of 41MHz, the sampling point of 4000 points and the pulse width of 18 mu s, and the mixing sequence is 4 paths of 4000 points +1, -1 Bernoulli pseudorandom signals PN1, PN2, PN3 and PN4 which are randomly distributed. The FPGA implementation process is as follows.
1. Firstly, inputting a complex signal to be detected into an FPGA;
2. then inputting the real part, the imaginary part and the pseudorandom series into the FPGA respectively and simultaneously;
3. multiplying the signal and the bernoulli pseudorandom number on the rising edge of each clock;
4. and obtaining a signal which is mixed with 24-bit width and then is transferred to a baseband, and outputting the signal to a low-pass filtering module.
The FPGA simulation result graph is shown in FIG. 2.
2) Low pass filter module
The low-pass filtering module has the functions of: the signal mixed to baseband is extracted.
The input of the module is mixed data with 24 bit width. The low-pass filter adopts an FIR filter, and the parameters of the filter need to be designed in consideration of sampling frequency, passband ripple, stopband attenuation, passband length and stopband length. The number of sub-bands is set to 20 to ensure the system implementation, so that various parameters of the FIR filter can be designed. In the invention, the base band bandwidth is designed to be 10MHz, so the design is carried outThe initial frequency of the transition band is 5MHz, and the cut-off frequency is 10 MHz. The order of the prototype low-pass filter is 43 order, rp＝3dB，rsAnd (4) carrying out quantization, truncation and rounding on the obtained filter coefficient, converting the obtained filter coefficient into a 16-system number, and writing the 16-system number into an FPGA program to construct the low-pass filter required by the design.
And writing the polyphase form of the low-pass filter in a low-pass filtering module by adopting a Verilog language and realizing a low-pass FIR filter. The polyphase form of the low-pass filter is shown below.
Let the low-pass FIR filter be
Where h (n) is the unit impulse response of the low-pass filter, the polyphase representation is shown in formula (1).
Wherein the content of the first and second substances,m is the number of the extracted multiphase structure, and the multiphase structure diagram is shown in FIG. 3.
It can be seen that the polyphase structure of the low-pass FIR filter is essentially the multiplication of the signal delays by the filter coefficients, respectively, and then summing them together. The FPGA implementation of the low pass filter module is as follows.
1. Writing the low-pass filter coefficients into a low-pass filter module;
2. performing 43-pipeline delay processing by sequentially performing pipeline assignment on 43 24-bit registers, wherein each register is delay of one clock cycle;
3. inputting the mixed signals into a first register to form input signal delay in a multiphase structure;
4. multiplying each register by the corresponding quantized 13-bit filter coefficient and adding the multiplied results in an assign statement;
5. and outputting the result of the assign statement to the speed reduction extraction module.
The simulation results obtained after the mixed signal passes through the low-pass filter are shown in fig. 4.
3) Speed reduction extraction module
The speed reduction extraction module has the following functions: and performing speed reduction processing of extracting one data per 20 clock periods on the signal data output by the low-pass filtering module to obtain baseband compressed sampling data, wherein the sampling rate is 10MHz, the number of the output compressed sampling signal points of each path is reduced to 200 points, and the data volume is reduced. The method provides convenience for subsequent FPGA processing and reduces the occupation of hardware resources. The FPGA implementation method is as follows.
1. Inputting the signal output by the low-pass filtering module;
2. writing a counter in the always block, and counting once every clock period;
3. when the count reaches 20, storing the input signal into a new register, and setting the counter to be 1;
4. intercepting the 11 th bit to the 25 th bit after the speed reduction extraction to form an output with the bit width of 15 bits
5. And outputting the intercepted signal to a CORDIC module.
The FPGA simulation results are shown in fig. 5.
4) CORDIC module
The CORDIC module has the functions of: and (4) approximating and calculating to obtain the amplitude and phase output of the signal by using the real part and the imaginary part of the input signal.
The Y-axis value obtained by the 9-level 2-division pipelining operation is already sufficiently close to 0, and therefore 9 coordinate system rotation operations are determined to be performed. The FPGA implementation method is as follows.
1. Newly building 9 register groups containing X-axis, Y-axis and phase;
2. respectively inputting the real part signal data and the imaginary part signal data into an X-axis register and a Y-axis register to judge whether the highest bit of the Y-axis register is a positive number;
3. rotating counterclockwise if the highest bit is a positive number, and rotating clockwise if the highest bit is a negative number;
4. rotating for 9 times by utilizing the idea of the 2-division method;
5. calculating and updating data in a register corresponding to the pipelining group by using the rotated X-axis and Y-axis coordinates by using the rotated angle;
6. judging the output of the Y axis, and if the low-order output of the Y axis is equal to 0, proving that the CORDIC operation is completed;
7. the amplitude of the signal in the X-axis register and the phase of the signal in the phase register are output.
The output simulation waveform of the FPGA is shown in fig. 6.
5) Phase difference frequency measuring module
The phase difference frequency measurement module has the functions of: and 4-point phase difference averaging is carried out by utilizing the 10-bit wide phase output by the CORDIC module, and the signal frequency in the sub-band is measured by utilizing a phase difference frequency measurement principle. In the digital domain the frequency and phase are first order differential relationships. The required frequency can be obtained by calculating the phase obtained by the CORDIC algorithm according to equation (2). The FPGA implementation process is as follows.
In the formula fsFor the sampling frequency, Δ φ (n) is the phase difference, and f is the subband relative frequency.
1. Inputting the phase output in the CORDIC module;
2. performing a pipeline delay process on the phase by using 2 registers, and solving the phase difference;
3. judging that 2 pi is subtracted from the phase difference when the phase difference is larger than + pi, and 2 pi is added to the phase difference when the phase difference is smaller than-pi;
4. 4-point accumulation average is carried out on the phase difference;
5. and multiplying the obtained average value by the sampling frequency and dividing by 2 pi to obtain and output the frequency in the signal sub-band.
The FPGA simulation diagram is shown in FIG. 7. As can be seen from the figure, the measured sub-band frequency is 0.9 MHz.
6) Pulse extraction module and pulse width measurement module
The pulse extraction module has the functions of: and comparing the amplitude output by the CORDIC module with a corresponding threshold value, regarding the signal exceeding the threshold value as an effective pulse, extracting the pulse, and calculating according to the arrival time and the disappearance time to obtain the pulse width. The system realizes the calculation and selection of the threshold value through the formula (3).
In the formula, PfFor false alarm probability, Q (x) is a standard normal distribution function,
is the noise variance and N is the data length. Its FPGA implementation is as follows.
1. Inputting the amplitude output by the CORDIC module into a pulse extraction module;
2. calculating to obtain a threshold value, wherein the threshold value in the test of the invention is decimal 37;
3. comparing the amplitude value with a threshold value, setting the amplitude value to be 1 when the amplitude value is larger than the threshold value, and simultaneously using accumulation operation to make a counter;
4. and calculating and outputting the pulse width through the counter value.
The FPGA simulation result graph is shown in FIG. 8. It can be seen from fig. 8 that 182 pulse amplitudes are above the threshold, 5ns per clock, due to the sampling frequency of 200 MHz. After the down sampling the clock becomes 100 ns. Therefore, the pulse width is 182 × 0.1 μ s — 18.2 μ s.
7) Time of arrival measurement module
The function of the time measurement module is achieved: the measurement obtains the time taken from the start of the system to the time the rising edge of the pulse is extracted. The FPGA implementation method is as follows.
1. At the beginning of the system, a counter is constructed, and the counter counts once every clock period;
2. in a pulse extraction module, two registers are newly built and carry out 1-level pipeline processing;
3. judging that the pulse extraction value inverted at the next moment is one, and proving that the rising edge of the pulse is captured;
4. the counter is stopped and the time of arrival is calculated.
8) Absolute frequency measuring module
The absolute frequency measurement module has the functions of: and calculating the actual carrier frequency of the signal by using the ratio of the DTFT of the two adjacent channels to obtain the number of the sub-band where the signal is located and matching with the relative frequency of the sub-band.
We design the subband bandwidth to be larger than the bandwidth of the input signal. It is therefore assumed that the carrier frequency of the input signal is only present in the l' th sub-band of each branch of the MWC wideband digital receiver. To find the absolute frequency, multi-channel signal detection is required and mixing is performed using a cyclic shifted periodic pseudo-random sequence. The relation between the sequence of the mth path and the sequence of the first path is shown in formula (4), and the fourier series form is shown in formula (5).
In the formula
Representing the sequence of principal values p1[n]With MpPeriodic pseudorandom sequence obtained by periodic prolongation of period
Rectangular function
When n is more than or equal to 0 and less than or equal to MpAnd 1 is 1.
The DTFT transform of the mth mixed signal can be written as equation (6).
The ratio of the DTFT transforms of the m +1 th path and the m-th path can be derived as equation (7).
Simplifying equation (7) results in an estimate for subband l' as in equation (8).
The final absolute frequency estimate can be derived from equation (9), where Δ f is the relative frequency in the subband.
f′c＝l′·fp+Δf (9)
The experimental results are as follows:
from the conclusion obtained in fig. 7, the frequency of the subband obtained by frequency measurement is 0.9MHz, and if the signal obtained by calculation of the absolute frequency module is on the 5 th subband, the absolute frequency of the signal obtained by calculation is 40.9MHz, and the input signal is 41MHz, so that the result of frequency measurement of the subband is correct.
From the conclusion of fig. 8, the measured pulse width is 18.2 mus, while the input signal pulse width is 18 mus. Thus, the pulse width measurement is correct.
Therefore, the conclusion can be drawn that the MWC compression sampling receiver built on the FPGA platform in the invention has a correct structure and can correctly output PDW data such as carrier frequency, pulse width, arrival time and the like.
The parameters and results set in the embodiments are only used for verifying the feasibility of the method provided by the invention, the method provided by the invention is not limited to the parameters and results set in the embodiments, and non-essential modifications of the invention still belong to the protection scope of the invention.
Claims (1)
1. A PDW forming method of an MWC compression sampling broadband digital receiver based on an FPGA is characterized in that: (1) the signal is input into a frequency mixing module and multiplied by a Bernoulli pseudo-random sequence and then output to a low-pass filtering module; (2) extracting a baseband signal from the low-pass filtering module and outputting the baseband signal to a speed reduction extraction module; (3) performing corresponding multiple extraction on the signals in the speed reduction extraction module to reduce the data volume and outputting the signals to the CORDIC module; (4) calculating the amplitude and the phase of the signal in a CORDIC module; (5) outputting the amplitude to a pulse extraction module for pulse extraction and outputting to an arrival time measurement module for measuring the arrival time of the pulse; (6) then outputting the amplitude to a pulse width measurement module, and calculating the pulse width in the pulse width measurement module; (7) outputting the phase to a phase difference frequency measurement module, and measuring the relative frequency of a sub-band; (8) inputting the DTFT of each sub-channel signal into an absolute frequency measurement module to calculate the sub-channel number of the signal, thereby calculating the true carrier frequency of the signal;
the frequency mixing module FPGA is realized by (1) firstly inputting a complex signal to be detected into the FPGA; (2) then inputting the real part, the imaginary part and the pseudorandom series into the FPGA respectively and simultaneously; (3) multiplying the signal and the bernoulli pseudorandom number on the rising edge of each clock; (4) obtaining a signal which is transferred to a baseband after the frequency mixing of the 24-bit wide, and outputting the signal to a low-pass filtering module;
the FPGA of the low-pass filtering module is realized by writing a multiphase form of the FPGA in a Verilog language in the low-pass filtering module and realizing a low-pass FIR filter, wherein the multiphase form of the low-pass filter is as follows, and the low-pass FIR filter is designed as
Where h (n) is the unit impulse response of the low-pass filter, the polyphase representation is shown in formula (1)
Wherein the content of the first and second substances,
m is a multiphase structure extraction number, and the FPGA of the low-pass filter module is realized as shown in the following (1) writing a low-pass filter coefficient into the low-pass filter module; (2) performing 43-pipeline delay processing by sequentially performing pipeline assignment on 43 24-bit registers, wherein each register is delay of one clock cycle; (3) inputting the mixed signal to a first registerTo form an input signal delay in a polyphase structure; (4) multiplying each register by the corresponding quantized 13-bit filter coefficient and adding the multiplied results in an assign statement; (5) outputting the result of the assign statement to a speed reduction extraction module;
the FPGA is implemented in the process that (1) a signal output by the low-pass filtering module is input; (2) writing a counter in the always block, and counting once every clock period; (3) when the count reaches 20, storing the input signal into a new register, and setting the counter to be 1; (4) intercepting the 11 th bit to the 25 th bit after the speed reduction extraction to form an output with a 15-bit width; (5) outputting the intercepted signal to a CORDIC module;
the CORDIC module FPGA is realized by (1) newly building 9 register groups comprising an X axis, a Y axis and a phase; (2) respectively inputting the real part signal data and the imaginary part signal data into an X-axis register and a Y-axis register to judge whether the highest bit of the Y-axis register is a positive number; (3) rotating counterclockwise if the highest bit is a positive number, and rotating clockwise if the highest bit is a negative number; (4) rotating for 9 times by utilizing the idea of the 2-division method; (5) calculating and updating data in a register corresponding to the pipelining group by using the rotated X-axis and Y-axis coordinates by using the rotated angle; (6) judging the output of the Y axis, and if the low-order output of the Y axis is equal to 0, proving that the CORDIC operation is completed; (7) outputting the amplitude of the signal in the X-axis register and the phase of the signal in the phase register;
the phase difference frequency measurement module FPGA is realized by the following steps,
in the formula fsIs sampling frequency, delta phi (n) is phase difference, f is subband relative frequency, (1) phase input in CORDIC module; (2) performing a pipeline delay process on the phase by using 2 registers, and solving the phase difference; (3) judging that 2 pi is subtracted from the phase difference when the phase difference is larger than + pi, and 2 pi is added to the phase difference when the phase difference is smaller than-pi; (4) 4-point accumulation average is carried out on the phase difference; (5) multiplying the obtained average value by the sampling frequency and dividing by 2 pi to obtain and outputFrequency within a signal sub-band;
the pulse extraction module and the pulse width measurement module FPGA are realized in the process that the calculation and the selection of the threshold value are realized by the formula (3)
In the formula, PfFor false alarm probability, Q (x) is a standard normal distribution function,
the variance of the noise is taken as N is the data length, (1) the amplitude output in the CORDIC module is input into a pulse extraction module; (2) calculating to obtain a threshold value; (3) comparing the amplitude value with a threshold value, setting the amplitude value to be 1 when the amplitude value is larger than the threshold value, and simultaneously using accumulation operation to make a counter; (4) calculating and outputting pulse width through the counter value;
the FPGA measurement module is implemented in the process that (1) when a system starts, a counter is constructed, and the counting is carried out once in each clock period; (2) in a pulse extraction module, two registers are newly built and carry out 1-level pipeline processing; (3) judging that the pulse extraction value inverted at the next moment is one, and proving that the rising edge of the pulse is captured; (4) stopping the counter, and calculating the reaching time;
the absolute frequency measurement module FPGA is realized by assuming that the carrier frequency of an input signal only exists in the l' sub-band of each branch of the MWC broadband digital receiver, performing multi-channel signal detection, and performing frequency mixing by adopting a cyclic shift periodic pseudorandom sequence, so that the relation between the sequence of the m-th path and the sequence of the first path is shown in a formula (4), and the Fourier series form is shown in a formula (5),
in the formulaRepresenting the sequence of principal values p1[n]With MpPeriodic pseudorandom sequence obtained by periodic prolongation of period
Rectangular function
When n is more than or equal to 0 and less than or equal to MpWhen the value of-1 is 1,
the DTFT transform of the mth mixing signal can be written as equation (6),
the ratio of DTFT transforms for the m +1 th path and the m-th path can be derived as equation (7),
simplifying equation (7) yields an estimate of subband l' as in equation (8),
the final absolute frequency estimate can be obtained from equation (9),
fc′＝l′·fp+Δf (9)
where Δ f is the relative frequency in the subband.
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| CN104678364A (en) * | 2015-03-13 | 2015-06-03 | 哈尔滨工程大学 | S-band passive radar interception receiver and signal processing method thereof based on FPGA (Field Programmable Gate Array) |
| CN105515695A (en) * | 2015-12-04 | 2016-04-20 | 哈尔滨工程大学 | Compressed sampling signal detection method based on modulated wideband converter |
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