CN107634060A - Semiconductor devices and preparation method thereof, electronic installation - Google Patents
Semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic installation, the preparation method includes providing Semiconductor substrate, nano-pillar is formed on the semiconductor substrate, the nano-pillar includes the bottom parallel to the Semiconductor substrate and the trunk portion perpendicular to the Semiconductor substrate, and the Semiconductor substrate and the nano-pillar conduction type are opposite；Form dielectric layer and the electrode layer on the dielectric layer respectively in the Semiconductor substrate of the trunk portion both sides, there is gap between the dielectric layer and electrode layer and the trunk portion；Silicide layer is formed on an electrode layer wherein, so that the electrode layer of the trunk portion both sides has different resistances.The preparation method can make the memory density of device improve 50%.The storage density of the semiconductor devices and electronic installation is higher.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the development of manufacture of semiconductor technology, various memories have been developed in terms of storage device, such as SRAM (quiet
State random access memory), DRAM (dynamic RAM), EEPOM (erasable read-only memory) and flash memory
(flash memory).The characteristics of these memories are according to being each provided with, have been widely used for various fields.Yet with waving
Hair property, speed, power consumption or area etc. reason, these memories are still not ideal enough in many occasions, need to develop newly for this
Memory with meet demand.
In recent years, people develop a kind of nano-machine electronic non-volatile memory (Nano-Electro-
Mechanical Non-volatile Memory), Figure 1A and Figure 1B schematically show the structure and principle of this memory.Such as
Shown in Figure 1A, this memory includes P type substrate 100, in the centre position of substrate 100 formed with N-type nano-pillar (nano-
Pillar) 101, dielectric layer 102 and the electrode layer 103 on dielectric layer 102 are provided with the both sides of N-type nano-pillar 101, is situated between
Gap be present between matter layer 102 and electrode layer 103 and N-type nano-pillar 101, applied when on substrate 100 and one of electrode layer
Add ground voltage GND, when applying attraction voltage Vpi in N-type nano-pillar 101 and another electrode layer, N-type nano-pillar 101 is in electricity
The electrode layer for applying ground voltage is bent towards under field force effect, realizes conducting.When applying loss of voltage, the Yin Fande of N-type nano-pillar 101
Magnificent power effect is still connected with grounding electrode, shape invariance, realizes the non-volatility memorizer that storage state maintains after powering off
Effect.When applying reverse bias voltage, the shape of nano-pillar 101 is recovered, and state is realized and blocked.Find after tested, this structure
Device ON state current and off-state current ratio be 1000 than 10nA, thus may be used as memory.
However, the memory of this device architecture only has the resistance of two states, i.e. Figure 1A and the state shown in Figure 1B,
Be only capable of realizing single level cell (single-level-cell, SLC), storage density is relatively low during as memory, cost compared with
Height, it is, therefore, desirable to provide a kind of new semiconductor devices and preparation method thereof, to solve the above problems at least in part.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to overcome the problem of presently, there are, the preparation method that one aspect of the present invention provides semiconductor device, it includes
Following step：Semiconductor substrate is provided, forms nano-pillar on the semiconductor substrate, the nano-pillar is included parallel to described
The bottom of Semiconductor substrate and the trunk portion perpendicular to the Semiconductor substrate, the Semiconductor substrate and the nano-pillar are conductive
Type is opposite；Dielectric layer and the electricity on the dielectric layer are formed respectively in the Semiconductor substrate of the trunk portion both sides
Pole layer, there is gap between the dielectric layer and electrode layer and the trunk portion；Wherein silicon is formed on an electrode layer
Compound layer, so that the electrode layer of the trunk portion both sides has different resistances.
Further, the step of forming the nano-pillar on the semiconductor substrate includes：Semiconductor substrate is provided,
Formed in the Semiconductor substrate has the first conductive-type perpendicular to the Semiconductor substrate lug boss, the Semiconductor substrate
Type；Formed and cover the Semiconductor substrate and the subregional hard mask layer of lug boss surface element, described in the hard mask layer definition
The shapes and sizes of nano-pillar；Using the hard mask layer as mask, selective oxidation is carried out, not covered by the hard mask layer
Region on form oxide layer；The hard mask layer is removed, to expose the nano-pillar, the nano-pillar is included parallel to described
The bottom of Semiconductor substrate and the trunk portion perpendicular to the Semiconductor substrate；The nano-pillar is doped, so that described
Nano-pillar has the second conduction type.
Further, the conduction type of the Semiconductor substrate is p-type, and the conduction type of the nano-pillar is N-type.
Further, dielectric layer is formed respectively in the Semiconductor substrate of the trunk portion both sides and positioned at the dielectric layer
On electrode layer the step of include：Form the dielectric layer for covering the nano-pillar and the oxide layer；On the dielectric layer
Electrode layer is formed, the height of the electrode layer is highly consistent with the nano-pillar；On the electrode layer of the nano-pillar side
Form silicide；The dielectric layer between the electrode layer is removed, retains the dielectric layer below the electrode layer.
Further, include in the step of formation silicide on the electrode layer of the side of the nano-pillar：Formation is covered
Cover the sacrifice layer of the electrode layer of the nano-pillar and the nano-pillar opposite side；In the sacrifice layer and the nano-pillar side
Metal level is formed on surface；Remove the sacrifice layer；Technology for Heating Processing is performed, with the electrode of the side of the nano-pillar
Silicide is formed on layer.
Further, the metal level on the sacrifice layer is removed while removing the sacrifice layer in the lump.
Further, the sacrifice layer is photoresist layer.
The preparation method of semiconductor devices proposed by the present invention, the electrode layer different by forming two resistances, be receives
Rice electric mechanical memory has three kinds of resistance value states, so as to realize more level cell (multi-level-cell
MLC), and memory density is improved 50%, correspondingly reduce memory cost.
Another aspect of the invention provides a kind of semiconductor devices, and the semiconductor devices includes：Semiconductor substrate, described half
Formed with nano-pillar on conductor substrate, the nano-pillar is included parallel to the bottom of the Semiconductor substrate and perpendicular to described half
The trunk portion of conductor substrate；Dielectric layer is respectively formed with the Semiconductor substrate of the trunk portion both sides and positioned at the dielectric
Electrode layer on layer, has gap, wherein the nano-pillar between the dielectric layer and the electrode layer and the trunk portion
Conduction type with the Semiconductor substrate is on the contrary, the electrode layer of the trunk portion both sides has different resistances.
Further, the electrode layer uses polycrystalline silicon material, and formed with silicon in a wherein electrode layer
Compound.
Further, the conduction type of the Semiconductor substrate is p-type, and the conduction type of the nano-pillar is N-type.
Semiconductor devices proposed by the present invention has three kinds of resistance value states, it is possible to achieve more level cell (multi-
Level-cell MLC), and memory density improves 50%.
Further aspect of the present invention provides a kind of electronic installation, it include semiconductor devices as described above and with it is described partly
The electronic building brick that conductor device is connected.
Electronic installation proposed by the present invention, due to above-mentioned semiconductor device, thus with it is similar the advantages of.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A~Figure 1B schematically shows the current a kind of structure and principle schematic of nano-electro mechanical memory；
Fig. 2 shows the step flow chart of the preparation method of semiconductor devices according to an embodiment of the present invention；
The preparation method that Fig. 3 A~Fig. 3 I schematically show semiconductor devices according to an embodiment of the present invention is real successively
Apply the top view that each step obtains semiconductor devices；
Fig. 4 A~Fig. 4 I show the preparation method for schematically showing semiconductor devices according to an embodiment of the present invention
Implement the sectional view that each step obtains semiconductor devices successively, wherein Fig. 4 A~Fig. 4 I are respectively Fig. 3 A~Fig. 3 I along A-A side
To sectional view；
Fig. 5 A~Fig. 5 D show that the structural representation of semiconductor devices according to an embodiment of the present invention and work are former
Reason figure；
Fig. 6 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated phase from beginning to end
Identical element is represented with reference.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
As it was previously stated, current nano-electro mechanical memory is only capable of realizing single level cell (single level
Storage density is relatively low when cell), as memory, and cost is higher.To solve the above problems, the present invention proposes a kind of semiconductor
The preparation method of device, for making nano-electro mechanical memory, to realize more level cell (multi-level-
Cell MLC), memory density is improved, as shown in Fig. 2 the preparation method includes：Step 201：Semiconductor substrate is provided, in institute
State and nano-pillar is formed in Semiconductor substrate, the nano-pillar is included parallel to the bottom of the Semiconductor substrate and perpendicular to institute
The trunk portion of Semiconductor substrate is stated, the Semiconductor substrate and the nano-pillar conduction type are opposite；Step 202：In the post
Form dielectric layer and the electrode layer on the dielectric layer in the Semiconductor substrate of body portion both sides respectively, the dielectric layer and
There is gap between electrode layer and the trunk portion；Step S203：Silicide layer is formed on an electrode layer wherein, with
Make the electrode layer of the trunk portion both sides there are different resistance layers.
The preparation method of semiconductor devices proposed by the present invention, the electrode layer different by forming two resistances, be receives
Rice electric mechanical memory has three kinds of resistance value states, so as to realize more level cell (multi-level-cell
MLC), and memory density is improved 50%, correspondingly reduce memory cost.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this hair
The technical scheme of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
System below with reference to Fig. 3 A~Fig. 3 I and Fig. 4 A~Fig. 4 I to the semiconductor devices of an embodiment of the present invention
It is described in detail as method.Wherein, Fig. 4 A~Fig. 4 I are respectively sectional views of Fig. 3 A~Fig. 3 I along A-A directions.
First, as shown in Figure 3 A and 4 A, there is provided Semiconductor substrate 300, the Semiconductor substrate 300 formed perpendicular to
The lug boss 301 of shown Semiconductor substrate 300.
Wherein, Semiconductor substrate 300 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, Semiconductor substrate 300
Constituent material select p type single crystal silicon.
Lug boss 301 is formed by chemical wet etching method, such as forms mask layer in Semiconductor substrate 300 first.Should
Mask layer defines the shapes and sizes of lug boss 301, then performs etch-back (etch back) by mask of the mask layer, from
And formed and lug boss is formed in Semiconductor substrate 300, it is so even to remove mask layer.The mask layer can be with photoresist layer, can also
For such as hard mask layer of oxide, nitride or nitrogen oxides.
Then, as shown in Fig. 3 B and Fig. 4 B, formed and cover the Semiconductor substrate 300 and the surface element subregion of lug boss 301
The hard mask layer 302 in domain, the hard mask layer 302 are used for the shapes and sizes for defining nano-pillar.
Specifically, the process may include steps of：
First, the hard mask layer for covering the Semiconductor substrate 300 and lug boss 301 is initially formed,
Then the hard mask layer is patterned by Lithography Etching technique, to define the shape of nano-pillar and big
It is small, obtain the structure as shown in Fig. 3 B and Fig. 4 B.
Exemplary, in the present embodiment, hard mask layer 302 uses nitride, such as silicon nitride.
Then, carry out selective oxidation as shown in Fig. 3 C and Fig. 4 C, with the Semiconductor substrate 300 and lug boss 301 not
The part covered by hard mask layer 302 forms oxide layer 303, then removes the hard mask layer 302 and forms nano-pillar 304.
Specifically, it is that mask carries out selective oxidation first with hard mask layer 302, with the Semiconductor substrate 300 and convex
Play the part that portion 301 is not covered by hard mask layer 302 and form oxide layer 303.The method for oxidation can be thermal oxidation method or
The conventional deposition process such as PVD, CVD, ALD.After selective oxidation is completed, hard mask layer 302 is removed.Specifically, can pass through
Suitable wet-etching technology or dry etch process remove hard mask layer 302.Wherein, the wet-etching technology is included such as
The wet-etching technology of the various appropriate solutions such as phosphoric acid, hydrofluoric acid, nitric acid, the dry method etch technology include but is not limited to：Instead
Answer ion(ic) etching (RIE), ion beam milling, plasma etching or laser cutting.
After hard mask layer 302 are removed, the part exposed is nano-pillar 304, the nano-pillar 304 include parallel to
The bottom of substrate 300 and the trunk portion perpendicular to substrate 300.After hard mask layer 302 are removed, it can be carried out with nano-pillar 304
Doping, so that its conduction type is opposite with the conduction type of substrate 300.Exemplarily, in the present embodiment, to nano-pillar 304
N-type doping is carried out, such as adulterates phosphonium ion.Doping process can select the conventional doping process such as ion implanting, doping
Dosage and energy etc. are arranged as required to, no longer specific herein to limit.
Then, as shown in Fig. 3 D and Fig. 4 D, the dielectric layer for covering the nano-pillar 304 and the oxide layer 303 is formed
305。
Dielectric layer 305 can use conventional dielectric layer material, such as oxide, nitride, nitrogen oxides etc..It can be with
Pass through the conventional sides such as thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (ald)
Method is formed.Exemplarily, in the present embodiment, dielectric layer 305 is oxide, and it uses LPCVD TEOS techniques to be formed.
Then, as shown in Fig. 3 E and Fig. 4 E, electrode layer 306 is formed on the dielectric layer 305.
Specifically, such as thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD are passed through first
Common methods such as (alds) forms electrode layer 306 on dielectric layer 305；
Then, electrode is removed by flatening process such as CMP (chemical-mechanical planarization), machinery planarization, grindings
Floor height makes to expose at the top of nano-pillar in the part of nano-pillar 304 by planarization.
Exemplarily, in the present embodiment, electrode layer 306 is polysilicon layer, and it can be by by selecting outside molecular beam
Prolong (MBE), metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD)
A kind of and formation in selective epitaxy growth (SEG).
Then, as shown in Fig. 3 F and Fig. 4 F, the electrode for covering the nano-pillar 304 and the side of the nano-pillar 304 is formed
The sacrifice layer 307 of layer 306.
Specifically, sacrifice layer 307 is formed on the device architecture surface shown in Fig. 3 E and Fig. 4 E, then passes through chemical wet etching etc.
Technique is patterned, so that sacrifice layer 307 covers the electrode layer 306 of nano-pillar 304 and the nano-pillar 304 side,
And expose the electrode layer 306 of the opposite side of nano-pillar 304.Exemplarily, in the present embodiment, the electricity on the right side of nano-pillar 304 is exposed
Pole layer 306.
Exemplarily, in the present embodiment, sacrifice layer uses photoresist layer, and it can be entered by the technique such as expose, develop
Row is graphical.Certainly, in other embodiments, other suitable materials can also be used.
Then, as shown in Fig. 3 G and Fig. 4 G, metal is formed on the surface of the electrode layer exposed and the sacrifice layer
Layer 308.
Metal level 308 can use the suitable metal material such as nickel, cobalt, its can with PVD, CVD, magnetron sputtering, splash
The techniques such as plating are formed.
Then, as shown in Fig. 3 H and Fig. 4 H, the sacrifice layer 307 is removed.
Specifically, sacrifice layer 307 is removed by suitable wet method or dry process, while removes the table of sacrifice layer 307 in the lump
The metal level 308 in face, referred to as " lift off " techniques, it can be specific due to that need not be performed etching to metal level for this technique
Metal level is formed on region, or realizes the graphical of metal level, damage when can avoid the metal level from etching to device, thus make
For the selection process of this implementation.Certainly, in other embodiments, also can be using suitable method come in the side of nano-pillar 304
Metal level is formed on electrode layer.
Exemplarily, in the present embodiment, because sacrifice layer 307 uses photoresist layer, thus it can be by suitable
Photoresist removes solvent or ashing method removes, and will not be repeated here.
Finally, Technology for Heating Processing is performed, to form silicide 309 on the electrode layer 306 of the side of nano-pillar 304,
Then the dielectric layer 305 between electrode layer 306 is removed, obtains the structure as shown in Fig. 3 H and Fig. 4 H.
The Technology for Heating Processing is the Technology for Heating Processing of low-temperature rapid thermal annealing, high-temperature quick thermal annealing etc., is passed through
The Technology for Heating Processing, metal level 308 and the electrode layer 306 of lower section are reacted so as to form silicide, because silicide tissue is relatively low,
So cause the electrode layer of the both sides of nano-pillar 304 that there is different resistances.
After silicide 309 are formed, Jie between electrode layer 306 is removed by suitable wet method or dry etching etching
Electric layer 305.Exemplarily, in the present embodiment, the dielectric between electrode layer 306 is removed by the hydrogen fluoride vapor etch of timing
Layer 305, and retain the dielectric layer 305 positioned at the lower section of electrode layer 306.
So far, the processing step that method according to embodiments of the present invention is implemented is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs afterwards
The step of, such as the step of formation interconnection structure, isolation structure etc..
The preparation method for the semiconductor devices that the present embodiment proposes, the electrode layer different by forming two resistances, yes
Nano-electro mechanical memory has three kinds of resistance value states, so as to realize more level cell (multi-level-cell
MLC), and memory density is improved 50%, correspondingly reduce memory cost.
Embodiment two
The present invention also provides a kind of semiconductor devices made using the above method, and as fig. 5 a and fig. 5b, this is partly led
Body device includes：Semiconductor substrate 500, wrapped in the Semiconductor substrate 500 formed with nano-pillar 501, the nano-pillar 501
Include the bottom parallel to the Semiconductor substrate 500 and the trunk portion perpendicular to the Semiconductor substrate 500；In the trunk portion
Dielectric layer 502 and the electrode layer 503 on the dielectric layer 502 are respectively formed with the Semiconductor substrate of both sides, it is described
There is gap, wherein the nano-pillar 501 and described partly leading between dielectric layer 502 and the electrode layer 503 and the trunk portion
The conduction type of body substrate 500 is on the contrary, the electrode layer of the trunk portion both sides has different resistances.
Wherein, Semiconductor substrate 500 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.Device, such as NMOS are could be formed with Semiconductor substrate
And/or PMOS etc..Equally, in Semiconductor substrate can also formed with conductive member, conductive member can be transistor grid,
Source electrode or drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..In the present embodiment, Semiconductor substrate
500 constituent material selects p type single crystal silicon.The nano-pillar 501 is n-type doping.
Dielectric layer 502 can use the conventional dielectric materials such as oxide, nitride, nitrogen oxides, and it can pass through
The methods of such as thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (ald), is formed.
Electrode layer 503 uses polycrystalline silicon material, and formed with silicide 504 in wherein one electrode layer 503,
Because polysilicon and silicide have different resistances, the electrode layer of such both sides of nano-pillar 501 just has different resistances.
The operation principle of the semiconductor devices of the present embodiment is as follows：
As shown in Figure 5 B, when no voltage is applied, the trunk portion of nano-pillar 501 is perpendicular to substrate 500, due to nano-pillar
There is gap between 501 trunk portion and electrode layer, thus device is in and blocks state.
When applying ground voltage GND on substrate 500 and left electrodes layer, apply in nano-pillar 501 and right electrodes layer
During the first attraction voltage V1pi, nano-pillar 501 bends towards left electrodes layer under electric field force effect, realizes conducting.
When applying ground voltage GND on substrate 500 and right electrodes layer, apply in nano-pillar 501 and left electrodes layer
During the second attraction voltage V1pi, nano-pillar 501 bends towards right electrodes layer under electric field force effect, realizes conducting.
When applying loss of voltage, nano-pillar 501 is because van der Waals interaction is still connected with grounding electrode, shape invariance,
Realize the effect of the non-volatility memorizer that storage state maintains after powering off.When applying reverse bias voltage, the shape of nano-pillar 501
Shape recovers, and state is realized and blocked.
Because left electrodes layer and right electrodes layer have different resistances, thus the semiconductor devices of the present embodiment has
Three kinds of resistance value states, it is possible to achieve more level cells (multi-level-cell MLC), and memory density improves
50%.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic installation, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, the semiconductor devices includes：Semiconductor substrate, on the semiconductor substrate formed with receiving
Meter Zhu, the nano-pillar include the bottom parallel to the Semiconductor substrate and the trunk portion perpendicular to the Semiconductor substrate；
Dielectric layer and the electrode layer on the dielectric layer, institute are respectively formed with the Semiconductor substrate of the trunk portion both sides
Giving an account of has gap between electric layer and the electrode layer and the trunk portion, wherein the nano-pillar and the Semiconductor substrate
Conduction type is on the contrary, the electrode layer of the trunk portion both sides has different resistances.
Further, the electrode layer uses polycrystalline silicon material, and formed with silicon in a wherein electrode layer
Compound.
Further, the conduction type of the Semiconductor substrate is p-type, and the conduction type of the nano-pillar is N-type.
Wherein Semiconductor substrate can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.Device, such as NMOS are could be formed with Semiconductor substrate
And/or PMOS etc..Equally, in Semiconductor substrate can also formed with conductive member, conductive member can be transistor grid,
Source electrode or drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..In addition, may be used also in the semiconductor substrate
So that formed with isolation structure, the isolation structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure is as example.In the present embodiment, the constituent material of Semiconductor substrate selects monocrystalline silicon.
Tunnel oxide is illustratively silicon oxide layer, and it can be by the way that such as (physical vapor be sunk for thermal oxidation method, PVD
Product), CVD (chemical vapor deposition), ALD (ald) the methods of formed.Floating boom is exemplarily used such as polysilicon
Semi-conducting material, and by selecting molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure chemical phase
Deposit (LPCVD), one kind that laser ablation deposition (LAD) and selective epitaxy are grown in (SEG) is formed.Gate dielectric is such as
For dielectric materials such as oxide, nitride, it is preferable that in the present embodiment, gate dielectric (that is, is aoxidized using ONO structure
Thing-Nitride Oxide), so both there is good interface performance, it may have good dielectric properties and suitable thickness.
Control gate exemplarily uses the semi-conducting material such as polysilicon, and by selecting molecular beam epitaxy (MBE), Organometallic
Learn vapour deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth
(SEG) a kind of formation in.Control gate hard mask layer is such as the conventional hard mask material layer such as oxide, nitride, and it can be with
Pass through shape the methods of such as thermal oxidation method, PVD (physical vapour deposition (PVD)), CVD (chemical vapor deposition), ALD (ald)
Into.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products including the semiconductor devices.
Wherein, Fig. 6 shows the example of mobile phone.The outside of mobile phone 600 is provided with the display portion being included in shell 601
602nd, operation button 603, external connection port 604, loudspeaker 605, microphone 606 etc..
The electronic installation of the embodiment of the present invention, by the semiconductor devices included has three kinds of resistance value states, Ke Yishi
Now more level cells (multi-level-cell MLC), and memory density improves 50%.Therefore the electronic installation
It is same that there is the advantages of similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of preparation method of semiconductor devices, it is characterised in that comprise the steps：
Semiconductor substrate is provided, forms nano-pillar on the semiconductor substrate, the nano-pillar includes partly leading parallel to described
The bottom of body substrate and the trunk portion perpendicular to the Semiconductor substrate, the Semiconductor substrate and the nano-pillar conduction type
Conversely；
Dielectric layer and the electrode layer on the dielectric layer are formed respectively in the Semiconductor substrate of the trunk portion both sides,
There is gap between the dielectric layer and electrode layer and the trunk portion；
Silicide layer is formed on an electrode layer wherein, so that the electrode layer of the trunk portion both sides has different resistances
Value.
2. the preparation method of semiconductor devices according to claim 1, it is characterised in that shape on the semiconductor substrate
Include into the step of nano-pillar：
Semiconductor substrate is provided, formed on the semiconductor substrate perpendicular to the Semiconductor substrate lug boss, it is described partly to lead
Body substrate has the first conduction type；
Formed and cover the Semiconductor substrate and the subregional hard mask layer of lug boss surface element, described in the hard mask layer definition
The shapes and sizes of nano-pillar；
Using the hard mask layer as mask, selective oxidation is carried out, to form oxygen on the region not covered by the hard mask layer
Change layer；
The hard mask layer is removed, to expose the nano-pillar, the nano-pillar includes the bottom parallel to the Semiconductor substrate
Portion and the trunk portion perpendicular to the Semiconductor substrate；
The nano-pillar is doped, so that the nano-pillar has the second conduction type.
3. the preparation method of semiconductor devices according to claim 2, it is characterised in that the conduction of the Semiconductor substrate
Type is p-type, and the conduction type of the nano-pillar is N-type.
4. the preparation method of semiconductor devices according to claim 2, it is characterised in that half in the trunk portion both sides
The step of forming dielectric layer and electrode layer on the dielectric layer on conductor substrate respectively includes：
Form the dielectric layer for covering the nano-pillar and the oxide layer；
Electrode layer is formed on the dielectric layer, the height of the electrode layer is highly consistent with the nano-pillar；
Silicide is formed on the electrode layer of the nano-pillar side；
The dielectric layer between the electrode layer is removed, retains the dielectric layer below the electrode layer.
5. the preparation method of semiconductor devices according to claim 4, it is characterised in that described the one of the nano-pillar
The step of silicide is formed on the electrode layer of side includes：
Form the sacrifice layer for the electrode layer for covering the nano-pillar and the nano-pillar opposite side；
Metal level is formed on the surface of the sacrifice layer and the nano-pillar side；
Remove the sacrifice layer；
Technology for Heating Processing is performed, to form silicide on the electrode layer of the side of the nano-pillar.
6. the preparation method of semiconductor devices according to claim 5, it is characterised in that while removing the sacrifice layer
The metal level on the sacrifice layer is removed in the lump.
7. the preparation method of the semiconductor devices according to claim 5 or 6, it is characterised in that the sacrifice layer is photoetching
Glue-line.
A kind of 8. semiconductor devices, it is characterised in that including：Semiconductor substrate, on the semiconductor substrate formed with nanometer
Post, the nano-pillar include the bottom parallel to the Semiconductor substrate and the trunk portion perpendicular to the Semiconductor substrate；
Dielectric layer and the electrode layer on the dielectric layer are respectively formed with the Semiconductor substrate of the trunk portion both sides, it is described
There is gap, wherein the nano-pillar and the Semiconductor substrate are led between dielectric layer and the electrode layer and the trunk portion
Electric type is on the contrary, the electrode layer of the trunk portion both sides has different resistances.
9. semiconductor devices according to claim 8, it is characterised in that the electrode layer uses polycrystalline silicon material, and
Formed with silicide in a wherein electrode layer.
10. semiconductor devices according to claim 8, it is characterised in that the conduction type of the Semiconductor substrate is P
Type, the conduction type of the nano-pillar is N-type.
11. a kind of electronic installation, it is characterised in that including the semiconductor devices as described in any one in claim 8-10
And the electronic building brick being connected with the semiconductor devices.
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