CN107623037A - 制作场效晶体管的方法 - Google Patents

制作场效晶体管的方法 Download PDF

Info

Publication number
CN107623037A
CN107623037A CN201610937094.4A CN201610937094A CN107623037A CN 107623037 A CN107623037 A CN 107623037A CN 201610937094 A CN201610937094 A CN 201610937094A CN 107623037 A CN107623037 A CN 107623037A
Authority
CN
China
Prior art keywords
fin type
type structure
laser
layer
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610937094.4A
Other languages
English (en)
Inventor
吕芳谅
刘致为
刘继文
黄仕贤
翁翊轩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107623037A publication Critical patent/CN107623037A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

于制作场效晶体管的方法中，由第一半导体材料所制成的鳍片式结构是形成，以使鳍片式结构从设置于基材上的隔离绝缘层突伸出。栅极结构是形成于鳍片式结构的一部分上，而定义出通道区域、源极区域和漏极区域于鳍片式结构中。于栅极结构形成后，激光退火是进行于鳍片式结构上。

Description

制作场效晶体管的方法
技术领域
本揭露是有关一种包含场效晶体管(Field Effect Transistors；FETs)的半导体装置及其制作方法，且特别是提供一种使用n型锗或SiGe的FETs与使用激光退火的方法。
背景技术
相较于Si，锗(Ge)和SiGe是具有较高的电荷迁移率的材料。掺杂剂是导入锗和SiGe，且是通过各种方法活化。于包含各种热制程的制程操作的期间，活性掺杂剂的浓度可能降低。
发明内容
根据本揭露的一态样，于制作场效晶体管的方法中，由第一半导体材料所制成的鳍片式结构是被形成。此鳍片式结构从设置于基材上的隔离绝缘层突伸出。栅极结构是形成于鳍片式结构的一部分上，而定义出通道区域、源极区域和漏极区域于鳍片式结构中。于栅极结构形成后，激光退火是进行于鳍片式结构。
附图说明
从以下结合所附附图所做的详细描述，可对本揭露的态样有更佳的了解。需注意的是，根据业界的标准实务，各特征并未依比例绘示。事实上，为了使讨论更为清楚，各特征的尺寸可任意地增加或减少。
图1是显示根据本揭露的一实施例所绘示的场效晶体管的连续制程的流程图；
图2A至图6是显示根据本揭露的一实施例所绘示的场效晶体管的连续制程的示意图；
图7A是显示激光退火装置的示意图；
图7B是显示激光光点的形状；
图8至图10是显示根据本揭露的一实施例所绘示的场效晶体管的连续制程的剖视图；
图11是显示活性掺杂剂浓度与电荷迁移率间的关系；
图12是显示活性掺杂剂浓度与退火温度间的关系；
图13是显示活性掺杂剂浓度与电荷迁移率间的关系；
图14是显示场效晶体管的ID-VGS特性。
具体实施方式
以下的揭露提供了许多不同的实施例或例子，以实施发明的不同特征。以下所描述的构件与安排的特定例子是用以简化本揭露。当然这些仅为例子，并非用以作为限制。举例而言，在描述中，第一特征形成于第二特征上方或上，可能包含第一特征与第二特征以直接接触的方式形成的实施例，而也可能包含额外特征可能形成在第一特征与第二特征之间的实施例，如此第一特征与第二特征可能不会直接接触。此外，本揭露可能会在各例子中重复参考数字及/或文字。这样的重复是基于简单与清楚的目的，以其本身而言并非用以指定所讨论的各实施例及/或配置之间的关系。
另外，在此可能会使用空间相对用语，例如“向下(beneath)”、“下方(below)”、“较低(lower)”、“上方(above)”、“较高(upper)”等等，以方便描述来说明如附图所绘示的一元件或一特征与另一(另一些)元件或特征的关系。除了在图中所绘示的方向外，这些空间相对用词意欲含括元件在使用或操作中的不同方位。设备可能以不同方式定位(旋转90度或在其他方位上)，因此可利用同样的方式来解释在此所使用的空间相对描述符号。此外，“所制成(made of)”的用语可指为“包含(comprising)”或“所组成(consisting of)”等用语。
图1是显示绘示场效晶体管(Field Effect Transistor；FET)的连续制程的流程图，且图2A至图6是显示根据本揭露的一实施例所绘示的FET的连续制程的示意图。图2A、3A、4A和5A是显示配置图(上视图)，图2B、3B、4B和5B显示沿着图2A或图5A的剖面线X1-X1剖切的剖视图，且图5C显示沿着图5A的剖面线Y1-Y1剖切的剖视图。可了解的是，额外的操作可于图1至图6所显示的制程之前、期间与之后被提供，而且下述操作的一些可被替换或省略，对于此方法额外的实施例而言。这些操作/制程的次序可被替换。
于图1的步骤S110中，于隔离绝缘层20中的空间或开口22是形成于基材10上，如图2A和2B所示。基材是由Si、Si(1-x)Gex(其中0＜x＜1，且以下称之为SiGe)或Ge所制成。在一实施例中，硅基材是被使用。此隔离绝缘层20是由一或多层的绝缘材料所制成，如SiO2、SiN或SiON。隔离绝缘层20可通过热氧化、化学汽相沉积(Chemical Vapor Deposition；CVD)、原子层沉积(Atomic Layer Deposition；ALD)，或者包含溅镀的物理汽相沉积形成。于开口22的底部，基材10是被暴露出。开口22可通过光微影和蚀刻操作形成。开口的宽度的范围是实质为从10nm至100nm，在一些实施例中。
于图1的步骤S120中，鳍片式结构30形成于开口22中，如图3A和3B所示。鳍片式结构30是由第一半导体材料所制成，如Si、Si(1-x)Gex(其中0＜x＜1)与Ge。在某些实施例中，Si(1-x)Gex且0.2＜x≦1是作为第一半导体材料。此第一半导体材料是以如磷、砷及/或锑n型掺杂。在一实施例中，n型锗是作为第一半导体材料。
第一半导体材料是利用CVD、ALD或分子束磊晶(Molecular Beam Epitaxy；MBE)磊晶形成于开口22中。对于锗磊晶成长，基材是于实质为300℃至400℃的温度加热。于磊晶成长的期间，掺杂可采用于鳍片式结构30中。在某些实施例中，其他掺杂制程，如离子布植制程或固相掺杂，是被使用。在一些实施例中，于鳍片式结构30中的掺杂剂的化学浓度的范围是实质为从1.0×1020cm-3至5.0×1020cm-3。
在一些实施例中，鳍片式结构30的厚度的范围是实质为从50nm至500nm。在其他实施例中，鳍片式结构30的厚度的范围是实质为从100nm至200nm。
在一些实施例中，第一半导体材料形成于开口22中，并与隔离绝缘层20的表面达至相同高度。在其他实施例中，第一半导体材料是形成于隔离绝缘层20的表面之下或之上。若第一半导体材料形成于隔离绝缘层20的表面之下时，平坦化制程，如化学机械抛光，可被进行以移除第一半导体材料的上部分。
于图1的步骤S130中，隔离绝缘层20是被凹陷，以使鳍片式结构30的上部分从隔离绝缘层20被暴露出(突伸出)，如图4A和4B所示。隔离绝缘层20是利用干式蚀刻及/或湿式蚀刻凹陷。在一些实施例中，借着凹陷蚀刻，鳍片式结构30从隔离绝缘层20以高度T1突伸，其中高度T1的范围是实质为从1nm至200nm。在其他实施例中，高度T1的范围是实质为从10nm至50nm。
于隔离绝缘层20被凹陷后，于图1的步骤S140中，第一退火操作是被进行。第一退火操作包含快速热退火(Rapid Thermal Annealing；RTA)操作及/或激光退火操作。步骤S140的第一退火操作是被进行，以改善鳍片式结构30的结晶性。在一些实施例中，当RTA进行时，基材是于范围是实质为从300℃至850℃的温度加热，且实质为30秒至15分钟。在某些实施例中，基材是于范围是实质为从800℃至850℃的温度加热，且实质为8分钟至12分钟。激光退火的条件容后再述。
在一些实施例中，步骤S140的第一退火操作是被省略。在其他实施例中，步骤S140的第一退火操作是于步骤S130的凹陷蚀刻前进行。
于图1的步骤S150中，包含栅极介电层和栅极电极层(均未绘示)的栅极堆叠40是形成于鳍片式结构30的一部分上，如图5A至5C所示。
栅极介电层包含一或多层的介电材料，如SiO2、SiON、SiN、HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3。栅极介电层可通过CVD、ALD或PVD形成。在一些实施例中，于介电层形成后，快速热氧化(Rapid Thermal Oxidation；RTO)是于实质为300℃至700℃的温度下，实质进行1分钟至5分钟。在一些实施例中，通过RTO，如由氧化硅及/或氧化锗所制成的层间介电层(未绘示)是形成于鳍片式结构30与栅极介电层之间。
栅极介电层包含一或多层的传导材料，例如多晶硅、Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi或CoSi。在一些实施例中，一或多个功函数调整层是插入栅极介电层和栅极电极层之间。功函数调整层是由传导材料所制成，如单层的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC，或者这些材料的二者或多者的复数层。栅极电极层是以此厚度和材料形成，且于栅极堆叠生成后的激光退火(步骤S160)中，栅极电极层反射至少90％的激光辐射线。在一些实施例中，栅极电极层的厚度的范围是实质为从10nm至300nm。
于对栅极介电层和栅极电极层的覆盖层形成于图4A和4B的结构上之后，包含光微影与蚀刻的图案化操作是被进行，以获得栅极堆叠40需要的形状。
于栅极堆叠40形成后，于步骤S160中，第二退火操作是被进行。第二退火操作包含如图6所示的激光退火50。
图7A是显示激光退火装置100的示意图。从激光源(未绘示)发射出的激光束110是经由光学元件115导向基材120(晶圆)，举例而言，此光学元件115包含一或多个透镜及/或一或多个镜子。基材120是放置于平台130上，且此平台130可于方向X和Y二维地移动。借着移动平台，激光束110的光点110S扫描基材。在一实施例中，当平台130不移动或平台130亦是移动，激光束110是利用镜子扫描。
在一些实施例中，基材120和激光束110的光点110S间的相对速度的范围是实质为从0.1cm/s至100cm/s。在一实施例中，此相对速度的范围是实质为从1cm/s至10cm/s。
激光束110的波长是相等于或大于193nm且相等于或小于1878nm，且此波长是相应于锗的能隙。在一些实施例中，激光束110的波长的范围是实质为从193nm至1080nm。使用于激光退火的激光源包含氦-氖激光(波长为1152nm、994nm或543nm)、氩离子激光(波长为351nm至1092nm)、掺钕钇铝石榴石(Nd:YAG)激光(波长为1064nm)、二极管激发(Diode-Pumped Solid State；DPSS)绿光激光(波长为532nm)、氪氟激光(波长为248nm)和氩氟激光(波长为193nm)。半导体激光亦可使用。
在一些实施例中，激光束110的功率密度的范围是实质为从0.1J/cm2至0.9J/cm2。在某些实施例中，激光束110的功率密度的范围是实质为从0.3J/cm2至0.7J/cm2。
在一些实施例中，激光束110可为脉冲激光，且其半高宽(Full-Width-at Half-Maximum；FWHM)的范围是实质为从0.1nsec至1000nsec。在其他实施例中，FWHM的范围是实质为从1nsec至50nsec。在一些实施例中，脉冲重复率(频率)的范围是实质为从0.1kHz至1MHz。在某些实施例中，脉冲重复率(频率)的范围是实质为从1kHz至100kHz。
图7B是显示激光光点110S的形状。激光光点110S的形状可为如图7B所示的(a)线形、(b)椭圆形或(c)圆形。在一些实施例中，激光光点110S的最大光点尺寸D1的范围是实质为从5μm至500μm。在某些实施例中，光点尺寸D1的范围是实质为从10μm至100μm。
图8至图10是显示根据本揭露的一实施例所绘示的场效晶体管的连续制程的剖视图。可了解的是，额外的操作可于图8至图10所显示的制程之前、期间与之后被提供，而且下述操作的一些可被替换或省略，对于此方法额外的实施例而言。这些操作/制程的次序可被替换。相似于或相同于如图1至图6所描述的型态、结构、材料、制程及/或操作可应用于此实施例中，且上述的详细描述可被省略。
图8至图10是显示以另一方法所绘示的鳍片式结构的连续制程的剖视图。
如图8所示，第一半导体层31的覆盖层是被磊晶形成于基材10上。然后，光罩层60形成于第一半导体层31上。举例而言，光罩层60包含光阻层及/或一或多个介电层，作为硬式光罩。
借着使用光罩层60作为蚀刻光罩，第一半导体层31是通道蚀刻，以形成鳍片式结构30，如图9所示。
于鳍片式结构30形成后，隔离绝缘层20是被形成，如图10所示。随的，相同或相似于图4A至图6所示的操作是被进行。
第二退火操作的功效和优点将被说明。
图11是显示活性掺杂剂浓度与刚成长的锗层的电荷迁移率间的关系，且锗层是以不同的退火制程处理。图12是显示锗层中的活性掺杂剂浓度与退火温度间的关系，其中退火温度是指激光退火后另一热处理(如RTA)的退火温度。横轴是显示于另一RTA制程中的退火温度，其中此另一RTA制程可于锗基场效晶体管的制作流程中进行；且纵轴是显示n型锗层中的电活性掺杂剂浓度。
于锗层磊晶形成之后，锗层(包含基材)是被施加不同的操作，以活化掺杂剂。如图11所示，当温度为700℃且时间为60秒，并于氢气环境中的内退火(in-situ annealing)进行时，这些电活性掺杂剂的浓度是实质为2.5×1018cm-3。当温度为700℃且时间为60秒，并于氮气环境中的RTA进行时，这些电活性掺杂剂的浓度是实质为1.7×1019cm-3。前述两操作的活化的掺杂剂浓度是小于1.0×1020cm-3。相较之下，通过使用激光退火，超过2.0×1020cm-3的活化的掺杂剂浓度可被获得，如图11所示。于图11中，Tgrowth代表锗层成长制程中的温度。
于锗层是磊晶形成且以激光退火处理之后，锗层(包含基材)是被施加RTA操作，以研究掺杂剂的去活化。如图12所示，当退火温度是等于或小于350℃时，这些电活性掺杂剂的浓度实质仍是3.0×1020cm-3。换言之，将进100％的掺杂剂仍是活化的。然而，对于退火温度大于350℃而言，活性掺杂剂浓度下降低于1.0×1020cm-3。
如前所述，于作为鳍片式结构(通道和源极/漏极)的锗层形成后，仍具有一或多个热制程(如包含RTO的栅极形成)，且这些热处理须等于或大于400℃的温度。一旦锗层是被施加具有等于或大于400℃的温度的RTA时，活性掺杂剂的部分是被去活化。此是显示于图12和图13中。本揭露已发现激光退火可再活化掺杂剂，即使掺杂剂是被热制程去活化。
如图13所示，磊晶成长后的n型锗层是被施加第一激光退火，以实质地完全活化掺杂剂(请参照图13的“第一激光退火活化后”)。通过第一激光退火，实质为2.0×1020cm-3的活化的掺杂剂浓度可获得。
随后，锗层是被施加RTO制程于550℃的温度，并经过3分钟。由于RTO制程，活化的掺杂剂浓度是下降至实质为1.2×1019cm-3。
然而，借着施加第二激光退火，RTO之前的活化掺杂剂浓度是被复原(增加)。特别地，对于0.3J/cm2至0.5J/cm2的激光能量而言，活化的掺杂剂浓度是增加至大于1.0×1020cm-3。
第二激光退火的功效亦可从FETs的ID-VGS特性观察到。如图14所示，通过第二激光退火的使用，漏极电流是增加多达12％。
在此实施例中，于需要超过400℃的热制程的栅极堆叠形成后，第二激光退火是被进行。如图6所示，激光退火50是不但施加于源极和漏极，且施加栅极堆叠。然而，由于栅极电极层是由可反射超过90％的激光束的材料所制成，故当源极和漏极是完全地退火时，位于栅极堆叠下的通道实质并未退火。
据此，在一些实施例中，源极和漏极的活性掺杂剂浓度的范围是实质为从1.0×1020cm-3至5.0×1020cm-3，当通道的活性掺杂剂浓度是低于源及与漏极的活性掺杂剂浓度，且小于1.0×1020cm-3。在某些实施例中，通道的活性掺杂剂浓度的范围是实质为从1.0×1018cm-3至9.0×1019cm-3。须注意的是，于源极和漏极，以及通道之间，掺杂剂的化学浓度实质是相同的。由于激光退火，源极和漏极可具有相似于带状或粗糙的表面。
须注意的是，于第二激光退火之后，未进行超过400℃的热处理。另外或额外地，在一些实施例中，于需要加热至超过400℃，以形成源极和漏极的磊晶层之后，第二激光退火是被进行。
在某些实施例中，激光退火是被闪光退火、动态表面退火、或其他超快速与高温退火方法替换。于此超快速与高温退火方法中，包含激光退火，锗层(于源极和漏极)是局部地被加热至接近或超过其熔点，实质大约小于1秒。
当鳍片式结构是由SiGe所制成时，相较于锗制成的鳍片式结构，较多的热能是通过激光退火(如较高的能量、较高的脉冲频率及/或较低的扫描速度)施加。
再者，栅极替换制程可被使用。此外，本方法可实施于环绕式栅极(Gate-All-Around；GAA)形式的FETs。
在此实施例中，于栅极堆叠形成后，激光退火是进行于n型锗(或SiGe)鳍片式结构。借着使用激光退火，于栅极形成的期间，已被一或多个热制程去活化的掺杂剂可被再活化。据此，于n型锗层中，获得较高浓度的电活化掺杂剂是可能的，例如大于1.0×1020cm-3的浓度。
熟悉此技艺者应了解到，并非所有优点须已于此讨论，对于所有实施例或例子，没有特定的优点是必须的，且其他实施例或例子可提供不同的优点。
根据本揭露的一态样，于制作场效晶体管的方法中，由第一半导体材料所制成的鳍片式结构是被形成。此鳍片式结构从设置于基材上的隔离绝缘层突伸出。栅极结构是形成于鳍片式结构的一部分上，而定义出通道区域、源极区域和漏极区域于鳍片式结构中。于栅极结构形成后，激光退火是进行于鳍片式结构上。
依据本揭露的一实施例，第一半导体材料为Si(1-x)Gex，且0.2＜x≦1。
依据本揭露的另一实施例，第一半导体材料为n型锗。
依据本揭露的又一实施例，激光退火中的激光的波长的范围是实质为从193奈米至1878奈米。
依据本揭露的再一实施例，激光退火中的激光的功率密度的范围是实质为从0.1J/cm2至0.9J/cm2。
依据本揭露的又另一实施例，基材与激光退火中的激光的光点间的相对速度的范围是实质为从0.1cm/s至100cm/s。
依据本揭露的再另一实施例，激光退火中的激光为具有0.1nsec至1000nsec脉冲的半高宽的脉冲激光。
依据本揭露的更另一实施例，于激光退火后，于源极和漏极中的电活性掺杂剂的浓度的范围是实质为从1.0×1020cm-3至5.0×1020cm-3。
依据本揭露的更另一实施例，栅极结构包含由一材料所制成的栅极电极，此材料于激光退火进行的期间反射超过90％的激光辐射。
依据本揭露的更另一实施例，于激光退火后，未进行温度超过400℃的热处理。
依据本揭露的更另一实施例，激光退火是在用以形成源极和漏极的磊晶层形成后被进行。
根据本揭露的另一态样，于制作场效晶体管的方法中，由第一半导体材料所制成的鳍片式结构是被形成。此鳍片式结构从设置于基材上的隔离绝缘层突伸出。第一退火是进行于鳍片式结构上。栅极结构是形成于鳍片式结构的一部分上，而定义出通道区域、源极区域和漏极区域于鳍片式结构中。于栅极结构形成后，第二退火是进行于鳍片式结构。第一半导体材料是n型锗，且第二退火是激光退火。
依据本揭露的一实施例，n型锗是被磷、砷和锑其中至少一者所掺杂。
依据本揭露的另一实施例，基材为硅，且n型锗是被磊晶地形成于基材上。
依据本揭露的又一实施例，形成鳍片式结构的操作包含形成隔离绝缘层于基材上；图案化隔离绝缘层，而形成开口，且基材是于开口的底部被暴露出；形成第一半导体材料于开口中的被暴露出的基材上；以及凹陷隔离绝缘层，以使由第一半导体材料所制成的鳍片式结构从隔离绝缘层突伸出。
依据本揭露的再一实施例，第一退火是于凹陷隔离绝缘层的操作前被进行。
依据本揭露的又另一实施例，形成鳍片式结构的操作包含形成由第一半导体材料所制成的磊晶层于基材上；图案化磊晶层至鳍片式结构中；形成隔离绝缘层，以使鳍片式结构嵌入至隔离绝缘层中；以及凹陷隔离绝缘层，以使由第一半导体材料所制成的鳍片式结构从隔离绝缘层突伸出。
依据本揭露的再另一实施例，第一退火是于凹陷隔离绝缘层的操作前被进行。
根据本揭露的又一态样，半导体装置包含场效晶体管。此场效晶体管包含鳍片式结构和栅极堆叠。鳍片式结构是由n型锗所制成，且具有通道、源极与漏极。栅极堆叠包含栅极介电层和栅极电极，且栅极堆叠设置于鳍片式结构的一部分上。栅极介电层是形成于超过400℃的温度。于源极和漏极中的复数个电活性掺杂剂的浓度的范围是实质为从1.0×1020cm-3至5.0×1020cm-3。
依据本揭露的一实施例，在通道中的电活性掺杂剂的浓度的范围是实质为从1.0×1018cm-3至9.0×1019cm-3。
上述已概述数个实施例的特征，因此熟悉此技艺者可更了解本揭露的态样。熟悉此技艺者应了解到，其可轻易地利用本揭露作为基础，来设计或润饰其他制程与结构，以实现与在此所介绍的实施例相同的目的及/或达到相同的优点。熟悉此技艺者也应了解到，这类对等架构并未脱离本揭露的精神和范围，且熟悉此技艺者可在不脱离本揭露的精神和范围下，在此进行各种的更动、取代与修改。

Claims (1)

1.一种制作场效晶体管的方法，其特征在于，该制作场效晶体管的方法包含：
形成由第一半导体材料所制成的一鳍片式结构，其中该鳍片式结构从设置于一基材上的一隔离绝缘层突伸出；
形成一栅极结构于该鳍片式结构的一部分上，而定义出一通道区域、一源极区域和一漏极区域于该鳍片式结构中；以及
于该栅极结构形成后，进行激光退火于该鳍片式结构上。
CN201610937094.4A 2016-07-14 2016-10-25 制作场效晶体管的方法 Pending CN107623037A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/210,388 2016-07-14
US15/210,388 US10068995B2 (en) 2016-07-14 2016-07-14 Semiconductor device including field effect transistor and a method for fabricating the same

Publications (1)

Publication Number Publication Date
CN107623037A true CN107623037A (zh) 2018-01-23

Family

ID=60941315

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610937094.4A Pending CN107623037A (zh) 2016-07-14 2016-10-25 制作场效晶体管的方法

Country Status (3)

Country Link
US (1) US10068995B2 (zh)
CN (1) CN107623037A (zh)
TW (1) TW201802949A (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11296227B2 (en) * 2019-10-16 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
TW202143333A (zh) 2020-05-08 2021-11-16 台灣積體電路製造股份有限公司 半導體元件之製造方法
US11404322B2 (en) * 2020-05-08 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8310013B2 (en) * 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US9159552B2 (en) * 2013-12-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a germanium-containing FinFET

Also Published As

Publication number Publication date
US20180019326A1 (en) 2018-01-18
TW201802949A (zh) 2018-01-16
US10068995B2 (en) 2018-09-04

Similar Documents

Publication Publication Date Title
US11955553B2 (en) Source/drain structure
US10868178B2 (en) Field effect transistor contact with reduced contact resistance using implantation process
TWI599037B (zh) 半導體結構與其製作方法
CN105097546B (zh) 用于FinFET器件的方法
US7094639B2 (en) Method for fabricating semiconductor device
TW201916118A (zh) 負電容結構的形成方法
US20070267660A1 (en) Method and apparatus for forming a semiconductor substrate with a layer structure of activated dopants
JP2009302373A (ja) 半導体装置の製造方法
US6812106B1 (en) Reduced dopant deactivation of source/drain extensions using laser thermal annealing
US20140159120A1 (en) Conformal Doping
CN107623037A (zh) 制作场效晶体管的方法
US7737036B2 (en) Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation
US11676867B2 (en) Method for manufacturing semiconductor structure
US10879371B2 (en) Thermal treatment for gate dielectrics
US9099412B2 (en) Selective laser anneal on semiconductor material
US20090042353A1 (en) Integrated circuit fabrication process for a high melting temperature silicide with minimal post-laser annealing dopant deactivation
US7863193B2 (en) Integrated circuit fabrication process using a compression cap layer in forming a silicide with minimal post-laser annealing dopant deactivation
US20220051905A1 (en) Formation of low-temperature and high-temperature in-situ doped source and drain epitaxy using selective heating for wrap-around contact and vertically stacked device architectures
US20150311090A1 (en) Method of manufacturing a semiconductor device
US20170148726A1 (en) Semiconductor processing method and semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180123

WD01 Invention patent application deemed withdrawn after publication