CN107621974B - Interrupt request distribution device and method for operating same - Google Patents
Interrupt request distribution device and method for operating same Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Abstract
The invention relates to an interrupt request distribution device, in particular for a computing unit having at least one computing core, wherein the interrupt request distribution device has at least one input for receiving an input interrupt request signal and at least one output for outputting an output interrupt request signal, in particular to the computing unit, wherein the interrupt request distribution device is designed to form at least one output interrupt request signal from the at least one input interrupt request signal, characterized in that the interrupt request distribution device has a delay device which is designed to delay the input interrupt request signal by a predefinable delay time in order to obtain a delayed interrupt request signal and to output the delayed interrupt request signal as an output interrupt request signal to the at least one output.
Description
Technical Field
The invention relates to an interrupt request distribution device, in particular for a computing unit having at least one computing core, wherein the interrupt request distribution device has at least one input for receiving an input interrupt request signal and at least one output for outputting an output interrupt request signal, in particular to the computing unit, wherein the interrupt request distribution device is designed to form at least one output interrupt request signal as a function of the at least one input interrupt request signal.
The invention also relates to a method for operating such an interrupt request distribution device.
The invention also relates to an electronic functional component which is designed to generate at least one interrupt request signal for at least one further component, in particular a computing core of a computing unit, and to a method for operating such an electronic functional component.
Background
Interrupt request distribution devices of the type mentioned before are known and are also referred to as "interrupt routers" in the english language region. Interrupts (interrupt requests) are used, for example, to interrupt or interrupt a program currently running on a computing unit and to perform other time-critical/short-lived operations that are defined or programmed in a so-called interrupt routine. The program that was previously interrupted continues to be implemented after the interrupt routine is completed. The interrupt may be forwarded to the corresponding computing unit by the interrupt request distribution means, for example. Since a plurality of different interrupt requests can be triggered by a plurality of sources simultaneously or temporally following one another in the system, it is proposed that: the priority is predefined and assigned for each interrupt request in the interrupt request distribution means. Whereby high priority interrupt requests can disadvantageously extrude low priority interrupt requests. If a certain interrupt request is not implemented within a predefined time, for example due to a priority, the necessary processes in the interrupt routine involved may not be implemented. This is particularly disadvantageous because it can lead to complete system crashes.
Disclosure of Invention
The problem on which the invention is based is solved by an interrupt request distribution arrangement according to claim 1 and by a method according to the parallel claim 10. Other aspects of the problem on which the invention is based are solved by an electronic functional assembly according to claim 8 and a method according to the parallel claim 13. Advantageous developments are specified in the dependent claims. Features which are essential for the invention are also found in the following description and in the drawings, wherein the features can be essential for the invention not only individually but also in different combinations, which are not explicitly pointed out again.
The invention relates to an interrupt request distribution device, in particular for a computing unit having at least one computing core, wherein the interrupt request distribution device has at least one input for receiving an input interrupt request signal and at least one output for outputting an output interrupt request signal, in particular to the computing unit, wherein the interrupt request distribution device is designed to form at least one output interrupt request signal as a function of the at least one input interrupt request signal. According to the invention, the interrupt request distribution device has a delay device which is designed to delay an input interrupt request signal by a predefinable delay time in order to obtain a delayed interrupt request signal and to output the delayed interrupt request signal as an output interrupt request signal to at least one output. The principles according to the present invention advantageously enable improved time control of interrupt requests and their output to other units, such as computing units. In particular, the accumulation of interrupt requests can be corrected and distributed better in time with the delay that can be achieved according to the invention, which makes full use of the interrupt request signals, which is advantageous in particular when at least a part of the interrupt requests are associated with a process to be carried out periodically, tasks such as computer programs, which are carried out periodically (for example in frames of 10 milliseconds or the like) on a computing unit, or with a communication period of a communication module, which can be used instead of or in addition to the computing unit as a source or sink of the interrupt request. In some embodiments, it is also conceivable that the predefinable delay time is zero. It is generally conceivable that the predefinable delay time is in the range between approximately 0 μs (microseconds) and approximately 100000 seconds (or more), particularly preferably between approximately 0 μs and approximately 1000ms (milliseconds), and even more particularly preferably between approximately 0 μs and approximately 50 ms.
In one embodiment, the output interrupt request signal may be output directly to a computing unit or communication module, which may then, for example, introduce a corresponding reaction (complete the interrupt routine, send a message over a communication bus, etc.). Alternatively or additionally, the output interrupt request signal may also be output to a multiplexer device for interrupt requests or to other distribution devices for interrupt requests (which may be constructed according to the invention or conventionally), whereby a cascading of the components involved may be achieved, which further increases the flexibility in processing interrupt requests.
In another embodiment, the step of forming the output interrupt request signal from the at least one input interrupt request signal may comprise a simple forwarding. I.e. the "formed" interrupt request signal directly corresponds to at least one input interrupt request signal. Alternatively, the formation may also comprise a continued signal processing (e.g. buffering and/or inverting) or an input of an interrupt request signal, e.g. with a release signal or a clock signal or similar (logical) connection.
In a further embodiment, it is provided that the interrupt request distribution device has m inputs for receiving input interrupt request signals, wherein m is greater than 1, and/or that the interrupt request distribution device has n outputs for outputting output interrupt request signals, wherein n is greater than 1. Other possible variants are: m=1 (only one input), m=n (as many inputs as outputs), m </SUB > n (more or fewer inputs than outputs), n=1 (only one output). Hereby a flexible allocation of interrupt request signals of one or more sources to one or more sinks may be achieved, wherein the advantage of delaying interrupt request signals is to provide the following additional degrees of freedom in accordance with the principles of the present invention.
In a further embodiment, it is provided that the interrupt request distribution device has a plurality of delay devices which are designed to delay the input interrupt request signals by respectively the same or different delay times, so that the flexibility is further increased and in particular an effective adaptation of the delay of the interrupt request signal, for example of the typical cycle times of the source or sink of the interrupt request signal n, can be achieved.
In a further embodiment, it is provided that at least one timer device (timer, in english) is provided in order to determine or predefine one or more delay times. For example, the timer device can be realized in a manner known per se by means of a counter element and a reference clock signal. According to a further embodiment, it is also conceivable to provide a common reference clock signal for interrupt request distribution devices with a plurality of delay devices and to provide individual counter elements for the plurality of delay devices. In general, the delay time according to the invention can be determined or implemented, for example, by means of a timer function (timer) integrated in the interrupt request distribution device.
In a further embodiment, provision is made for the interrupt request distribution device to be designed to receive configuration information from an external component and/or to store the configuration information at least temporarily locally, wherein the configuration information characterizes in particular the delay time or the delay time. The operation of the interrupt request distribution device can thus be effectively controlled by an external unit, such as a computing unit or a microcontroller, in particular also with respect to the delay time to be provided.
In another embodiment, the configuration information may include at least one of the following information: information of which (delayed) input signals should be directed to which outputs, priority information, e.g. indicating that the input signals of some inputs are to be processed preferentially with respect to the input signals of other inputs, one or more delay times.
In a further embodiment, provision is made for the interrupt request distribution device to be designed to interrupt a currently running delay time, wherein the interrupt request distribution device is designed in particular to receive an interrupt instruction during the currently running delay time and to interrupt the currently running delay time in response to the receipt of the interrupt instruction. The delay of the operation can thus advantageously be interrupted and the interrupt request concerned is output without further delay. In the case of a delay of such an interruption of operation, the actual delay time of the interruption request signal concerned is thus finally derived, which is smaller than the initially specified delay time.
According to further embodiments, such interrupt instructions may be output, for example, by a source (e.g., computing unit, communication module) or sink (e.g., computing unit, communication module) assigned to the interrupt request distribution device and/or also by the interrupt request distribution device itself.
In a further embodiment, it is provided that the interrupt request distribution device is at least partially, but preferably completely, configured as a hardware circuit, preferably, for example, in the case of a semiconductor process having a structural size in the range of approximately 16nm (nanometers) and approximately 60 nm. In some embodiments, the interrupt request distribution means may be integrated directly on a semiconductor substrate of the computing unit or communication module, for example, or the like.
A further solution to the task of the invention is to specify a method according to claim 10. Comparable advantages are derived here as already described above with respect to the interrupt request distribution means.
Another solution to the task of the present invention is also illustrated by an electronic functional component. The electronic functional module is designed to generate at least one interrupt request signal for at least one further module, in particular a computing core (or, for example, a communication module) of a computing unit, and is characterized in that the functional module has an input for receiving an input signal and an interrupt request signal generation device, wherein the interrupt request signal generation device is designed to generate at least one interrupt request signal as a function of the input signal, and the functional module has a delay device which is designed to delay the at least one interrupt request signal by a predefinable delay time in order to obtain a delayed interrupt request signal and to output the delayed interrupt request signal as an output interrupt request signal to the at least one further module.
The electronic functional component can thus advantageously implement a delay of the interrupt request signal directly locally in the functional component. Alternatively, the electronic functional component may also be combined with the aforementioned interrupt request distribution means.
In a further embodiment, it is provided that the electronic functional component is a communication module, an SPI (english: serial peripheral interface, serial peripheral interface) or an MSC (micro bus) interface or another data source which is designed to request or signal the transmission of data or other actions or events by means of an interrupt request signal. Accordingly, the electronic functional module contains, in addition to the above, communication components corresponding to the components relating to the processing and delay of interrupt requests.
In a further embodiment of the electronic functional component, it is provided that at least one timer device (for example comparable to that described above with reference to the embodiment of the interrupt request distribution device) is provided in order to determine or predetermine the delay time.
In a further embodiment of the electronic functional component, the electronic functional component is configured for receiving configuration information from an external component and/or for at least temporarily storing the configuration information locally, wherein the configuration information characterizes in particular a delay time, for example in comparison with the embodiments described previously with reference to the interrupt request distribution device.
In a further embodiment of the electronic functional component, the electronic functional component is configured for interrupting a delay time of the current operation, wherein the electronic functional component is in particular configured for receiving an interrupt instruction during the delay time of the current operation and interrupting the delay time of the current operation in response to the receipt of the interrupt instruction, for example in comparison with the embodiment previously described with reference to the interrupt request distribution means.
In a further embodiment of the electronic functional component, the electronic functional component is at least partially, but preferably completely, configured as a hardware circuit, preferably, for example, in the case of semiconductor processes having structural dimensions in the range of approximately 16nm (nanometers) and approximately 60 nm.
The interrupt request distribution device and/or the electronic functional components can particularly advantageously be integrated into a further unit, such as a computing unit, for example a microcontroller with at least one computing core, or into a communication module (for example of the SPI or MSC type), in particular also arranged on the same semiconductor substrate as the further unit.
A further solution to the task of the invention is to specify a method according to claim 13.
Drawings
Exemplary embodiments of the present invention are explained below with reference to the accompanying drawings. In the drawings:
figure 1 schematically shows a block diagram of a first embodiment of an interrupt request distribution arrangement according to the invention,
figure 2 schematically shows a block diagram of a second embodiment of an interrupt request distribution arrangement according to the invention,
figure 3 schematically shows a time diagram of an embodiment,
figure 4 schematically shows a simplified flow chart of an embodiment of the method according to the invention,
figure 5 schematically shows a block diagram of a first embodiment of an electronic functional component according to the invention,
fig. 6 to 8 schematically show further embodiments of the invention, and
fig. 9 schematically shows a simplified flow chart of another embodiment of the method according to the invention.
Detailed Description
Fig. 1 schematically shows a block diagram of a first embodiment of an interrupt request distribution device 100 according to the invention, also referred to below simply as "distribution device 100" and english also as interrupt router. The dispensing device 100 has: an input 102 on which the distribution means can receive an input interrupt request signal irq_i from the source 10; and at least one output 112 for outputting an output interrupt request signal irq_o to a sink 200, which may be in particular a computing unit 200, such as a microcontroller with a computing core 202.
The source 10 may be, for example, a communication module of the SPI or MCS type or similar type, which outputs an input interrupt request signal irq_i to the distribution device 100, for example, when it has received data from an external unit (not shown). The distribution device 100 may then form a corresponding output interrupt request signal irq_o from the at least one input interrupt request signal irq_i and output to the computing unit 200 in a manner described later.
According to the invention, the interrupt request distribution device 100 has a delay device 120 which is designed to delay the input interrupt request signal irq_i by a predefinable delay time in order to obtain a delayed interrupt request signal irq_d and to output the delayed interrupt request signal irq_d as an output interrupt request signal irq_o to the output 112. The improved time control of the interrupt request irq _ i and its output to other units 200 can advantageously be achieved in accordance with the principles of the present invention. In particular, the accumulation of interrupt requests can be corrected and distributed better in time with the delay that can be achieved according to the invention, which makes full use of the interrupt request signals, which is advantageous in particular when at least a part of the interrupt requests are associated with a process to be carried out periodically, tasks such as computer programs, which are carried out periodically (for example in frames of 10 milliseconds or the like) on the computing unit 200, or with a communication period of the communication module 10, which can be used instead of or in addition to the computing unit 200 as a source or sink of the interrupt request. In some embodiments, it is also conceivable that the predefinable delay time is zero. It is generally conceivable that the predefinable delay time is in the range between approximately 0 μs (microseconds) and approximately 100000 seconds (or more), particularly preferably between approximately 0 μs and approximately 1000ms (milliseconds), and even more particularly preferably between approximately 0 μs and approximately 50 ms.
In one embodiment, the output interrupt request signal irq_o may be output directly to the computing unit 200 (or communication module) as depicted in fig. 1 and described previously, which may then for example introduce a corresponding reaction (complete the interrupt routine, send a message over the communication bus, etc.). Alternatively or additionally, the output interrupt request signal irq_o may also be output to multiplexer means (not shown) for interrupt requests or other distribution means for interrupt requests, which may be constructed according to the invention or conventional, whereby cascading of the components involved may be achieved, which further increases flexibility in handling interrupt requests.
Fig. 4 shows a flow chart for elucidating an embodiment of the method according to the invention. An incoming interrupt request signal irq _ i from source 10 is received in step 400, see fig. 1. In step 410 of fig. 4, the received input interrupt request signal irq_i is delayed by a predefinable delay time in order to obtain a delayed interrupt request signal irq_d, and in step 420 the delayed interrupt request signal irq_d is finally output as output interrupt request signal irq_o to at least one output 112.
In one embodiment, the formed output interrupt request signal irq_o may correspond to the input interrupt request signal irq_i except for the time delay performed as necessary in step 410 (i.e., the predetermined delay time is zero as long as no exception is made). In further embodiments, the formation of the output interrupt request signal irq_o may comprise, in addition to the time delay in step 410, a continued signal processing (e.g. buffering (e.g. in the sense of regeneration of the signal level) and/or inverting) or an input interrupt request signal irq_i, e.g. in connection with a release signal or a clock signal or similar (logic).
In a further embodiment, which is schematically shown in fig. 2, it is provided that the interrupt request distribution device 100 'has m inputs 102a, …, 102d for receiving input interrupt request signals irq_i1, …, irq_i4, where m is greater than 1, according to fig. 2 m =4, and/or that the interrupt request distribution device 100' has n outputs 112a, …, 112d for outputting output interrupt request signals irq_o1, …, irq_o4, where n is greater than 1, according to fig. 2 n =4.
Other possible variants are: m=1 (only one input), m=n (as many inputs as outputs), see fig. 2, m </SUB > n (more or fewer inputs than outputs), n=1 (only one output). Hereby a flexible distribution of the interrupt request signals irq_i, irq_i1, …, irq_i4 of one or more sources 10 (fig. 1) to one or more sinks 200, 200' may be achieved, wherein the advantage of delaying the interrupt request signals is to provide the following additional degrees of freedom in accordance with the principles of the present invention.
Currently, the interrupt request distribution device 100 'has, as already described, a total of 4 outputs 112a, 112b, 112c, 112d, via which the respective output interrupt request signals irq_o1, …, irq_o4 can be output to the four computing cores 202a, 202b, 202c, 202d of the computing unit 200'.
In a further embodiment, it is provided that the interrupt request distribution device 100' has a plurality of delay devices 120a, 120b, 120c, which are designed to delay the input interrupt request signals irq_i1, irq_i2, irq_i3, irq_i4 by respectively the same or different delay times, as a result of which the flexibility is further increased and in particular an effective adaptation of the delay of the interrupt request signal, for example a typical cycle time of the source or sink of the interrupt request signal n, can be achieved. In one embodiment, a plurality of delay devices 120a, 120b, 120c may be statically assigned to a certain input 102a, …, 102d. Alternatively, dynamic allocation of a plurality of delay means 120a, 120b, 120c to different inputs is also conceivable.
In a further embodiment, it is provided that at least one timer device (timer) 130 is provided in order to determine or predetermine one or more delay times. For example, the timer means 130 may be realized in a manner known per se by means of a counter part and a reference clock signal. According to a further embodiment, it is also conceivable to provide a common reference clock signal for an interrupt request distribution device 100' having a plurality of delay devices 120a, 120b, 120c and to provide individual counter elements for the plurality of delay devices. In general, the delay time according to the invention can be determined or implemented, for example, by means of a timer function (timer) 130 integrated in the interrupt request distribution device 100'.
Fig. 3 schematically shows a time diagram illustrating the delay according to the invention of an input interrupt request signal. At time t0, the distribution device 100' according to fig. 2 receives a first input interrupt request signal irq_i1 at its first input 102. The first input interrupt request signal is delayed by the first delay unit 120a by, for example, a previously configured first delay time T1, thereby obtaining a delayed first interrupt request signal, which is then output as a first output interrupt request signal irq_o1 to the computing unit 200' via the output 112a, i.e., after the end of the first delay time T1, i.e., at the time point T1. The second input interrupt request signal arriving at the time point T0 is delayed by a second delay time T2 by means of the second delay unit 120b according to fig. 3 until the time point T2 and thereafter output as a second output interrupt request signal irq_o2 to the calculation unit 200' via the output 112 b. The third input interrupt request signal arriving at the time point T01 is delayed by a third delay time T3 by means of the third delay unit 120c according to fig. 3 until the time point T3 and thereafter output as a third output interrupt request signal irq_o3 to the calculation unit 200' via the output 112 c.
In a further embodiment, provision is made for the interrupt request distribution device 100, 100 'to be configured for receiving configuration information from the external component 10, 200' and/or for at least temporarily storing the configuration information locally, see reference numeral 140 in fig. 2, wherein the configuration information 140 characterizes in particular the delay time or delay time. The operation of the interrupt request distribution device 100 'can thus be effectively controlled by an external unit 200', such as a computing unit or a microcontroller, in particular also with respect to the delay times T1, T2, T3 to be provided.
In another embodiment, the configuration information 140 may include at least one of the following information: information of which (delayed) input signals should be directed to which outputs 112a, 112b, 112c, 112d for delay times T1, T2, T3, priority information, e.g. specifying that the input signals of some inputs 102a, 102b are to be processed preferentially with respect to the input signals of other inputs 102c, 102d.
In a further embodiment, provision is made for the interrupt request distribution device 100, 100' to be designed to interrupt the currently running delay time T1, wherein the interrupt request distribution device is designed in particular to receive an interrupt command HLT (fig. 2) during the currently running delay time T1 and to interrupt the currently running delay time T1 in response to the receipt of the interrupt command HLT. The delay of the operation can thus advantageously be interrupted and the interrupt request concerned is output without further delay. In the case of a delay of such an interruption of operation, the actual delay time of the interruption request signal concerned is thus finally derived, which is smaller than the initially specified delay time.
According to further embodiments, such interrupt instructions may be output, for example, by the source 10 (e.g., computing unit, communication module) or sink 200, 200 '(e.g., computing unit, communication module) assigned to the interrupt request distribution device and/or also by the interrupt request distribution device 100, 100' itself.
In a further embodiment, it is provided that the interrupt request distribution device 100, 100' is at least partially, but preferably completely, configured as a hardware circuit, preferably, for example, in the case of a semiconductor process having a structural size in the range of approximately 16nm (nanometers) and approximately 60 nm. In some embodiments, the interrupt request distribution device 100, 100 'may be integrated directly on a semiconductor substrate or the like of the computing unit 200, 200' or the communication module 10, for example.
Fig. 5 schematically shows a block diagram of a first embodiment of an electronic functional component 500, which is another aspect of the invention.
The electronic functional component 500 is designed to generate at least one interrupt request signal for at least one further component, in particular a computing core (or, for example, a communication module) of a computing unit, and is characterized in that the functional component 500 has an input 502 for receiving an input signal i and an interrupt request signal generating means 510, wherein the interrupt request signal generating means 510 is designed to generate at least one interrupt request signal irq as a function of the input signal i, and the functional component 500 has a delay means 520 which is designed to delay the at least one interrupt request signal irq by a predefinable delay time T1 in order to obtain a delayed interrupt request signal irq_d and to output the delayed interrupt request signal irq_d as an output interrupt request signal irq_o to the at least one further component 100″ via an output 504.
The electronic functional component 500 can thus advantageously implement a delay of the interrupt request signal irq directly locally in the functional component 500. Alternatively, the electronic function assembly 500 may also be combined with the previously described interrupt request distribution device 100, 100'.
In another embodiment, it is provided that the electronic functional component 500 is a communication module, an SPI (english: serial peripheral interface, serial peripheral interface) or an MSC (micro bus) interface or other data source, which is designed to request or signal the transmission of data or other actions or events by means of an interrupt request signal. Accordingly, the electronic functional module 500 comprises, in addition to the above, a communication component 530 corresponding to the components 510, 520 relating to the processing and delay of the interrupt request irq.
In another embodiment, instead of an input signal that can be supplied from the outside, it is also possible to form the "input signal" I' internally in the electronic functional module 500, for example by means of the communication module 530 or the module 508 triggering the generation of the interrupt request signal irq. In these cases, the input 502 may be omitted if necessary.
For example, a flag (e.g., a signal bit) in the interrupt request signal generation means may be set after the determination operation is performed in the communication component 530, the flag signaling the end of the operation. The setting of the flag starts a timer (timer) of the delay means 520 configured with the desired delay time T1 and is signaled by the timer after the end of the delay time T1, for example, a switch 506 may be operated, which may correspond to an "off on/off bit" according to an embodiment. Currently, the output interrupt request signal irq_o is therefore output to the sink 100″ only when the switch 506 is closed.
The sink 100″ may be a computing unit or a further component, for example also a conventional or according to the invention interrupt request distribution device 100, 100' (interrupt router).
In another embodiment, electronic functional components 500 may also be integrated into an (existing) communication module 1000', see fig. 7, fig. 7 showing an SPI communication module 1000', into which at least one electronic functional component 500 is integrated. With this configuration, for example, the internal operating variables of SPI communication module 1000' can be supplied as input signal i to input 502 of functional module 500, which functional module 500 causes the aforementioned formation of interrupt request signal irq and its delay.
In a further embodiment of the electronic functional component 500, it is provided that at least one timer device (for example comparable to that described previously with reference to the embodiment of the interrupt request distribution device 100') is provided in order to determine or predefine the delay time T1.
In another embodiment of the electronic functional component 500, the electronic functional component 500 is configured to receive configuration information from an external component and/or to at least temporarily store the configuration information 540 locally, wherein the configuration information characterizes in particular the delay time.
In a further embodiment of the electronic functional component 500, the electronic functional component 500 is configured for interrupting a currently running delay time, wherein the electronic functional component 500 is in particular configured for receiving an interruption instruction HLT during the currently running delay time (currently exemplarily from the computing unit 100 ") and interrupting the currently running delay time in response to the reception of the interruption instruction HLT, for example in comparison with the embodiment previously described with reference to the interruption request distribution means 100'.
In a further embodiment of the electronic functional component 500, the electronic functional component is at least partially, but preferably completely, configured as a hardware circuit, preferably for example in the case of semiconductor processes having structural dimensions in the range of approximately 16nm (nanometers) and approximately 60 nm.
The interrupt request distribution device 100, 100' and/or the electronic functional component 500 may particularly advantageously be integrated into a further unit, such as a computing unit, for example a microcontroller with at least one computing core, or into a communication module (for example of the SPI or MSC type), in particular also arranged on the same semiconductor substrate as the further unit.
Fig. 6 shows a microcontroller 1000 for this purpose, into which microcontroller 1000 the interrupt request distribution device 100 is integrated, and fig. 8 shows a further microcontroller 2000 for this purpose, into which microcontroller 2000 the electronic functional components are integrated.
Fig. 9 schematically shows a simplified flow chart of an embodiment of the operating method according to the invention for an electronic functional component 500. The input signal i (fig. 5) is received in step 600, whereby at least one interrupt request signal irq (fig. 5) is generated in step 610 (fig. 9), the interrupt request signal irq is delayed in step 620, and the delayed interrupt request signal irq_o is output in step 630.
The principle according to the invention can advantageously be combined with any interrupt source and/or interrupt sink as occurs, for example, in the field of microcontroller technology. By means of a suitable advance of the delay times, it is advantageously possible to compensate for the high time rate of the incoming interrupt requests or to correct the corresponding interrupt requests in time, which provides more free space for the running interrupt request-based applications (tasks). Systems that fully exploit the principles according to the present invention may be better balanced over internal time and thus achieve improved stability. In particular, it is possible to prevent a plurality of interrupt requests which occur simultaneously in time from blocking each other.
The principles according to the present invention may also be particularly advantageous in systems in which interrupt requests are used as triggers (enable signals) for direct memory access (direct memory access, direct memory access, simply "DMA"). In some communication modules (e.g., SPI, MSC), the communication may run external bus users (e.g., slaves) in consecutive time frames (e.g., every 10 ms). Here, the communication or data transmission task is set by the computing unit into a buffer (queue) at the beginning of a time frame of, for example, 10 ms. All tasks must be transmitted within 10ms because the queue is refilled in the next 10ms frame. The task is advantageously completed gradually by the computing unit by means of interrupt requests (interrupts), for example of the type "transmission complete", "new task start", etc. Very high interrupt loads may occur for the system at the beginning of the 10ms frame because the transmission is almost back-to-back (Bursts). Since 10ms frames are typically not completely filled from a temporal perspective, a relatively long rest is formed after transmission until the next 10ms period begins. A high full load at the beginning results in other running tasks not ending in time. A high task jitter is here discussed, which makes the whole system unstable. These disadvantages can be avoided by using the principle according to the invention in that, for example, interrupt requests that occur cumulatively at the beginning of a time frame of 10ms are corrected in time by a suitable choice of the different delay times T1, T2, T3 and are thus distributed more evenly over the time frame.
Claims (12)
1. Interrupt request distribution device (100), in particular for a computing unit (200) having at least one computing core (202), wherein the interrupt request distribution device (100) has at least one input (102) for receiving (400) an input interrupt request signal (irq_i) and at least one output (112) for outputting an output interrupt request signal (irq_o), in particular to the computing unit (200), wherein the interrupt request distribution device (100) is designed to form at least one output interrupt request signal (irq_o) as a function of the at least one input interrupt request signal (irq_i), characterized in that the interrupt request distribution device (100) has a delay device (120) which is designed to delay (410) the input interrupt request signal (irq_i) by a predefinable delay time (T1) in order to obtain a delayed interrupt request signal (irq_d) and to output (420) the delayed interrupt request signal (irq_d) as an output interrupt request signal (irq_o) to the at least one output (420), wherein the interrupt request distribution device (100) has a plurality of delay devices (120 a ) and (120 a) which are not configured to delay each other by the delay device (120 a, respectively T3) such that the delay of the interrupt request signal effectively matches the typical cycle time of the source or sink of the interrupt request signal.
2. Interrupt request distribution arrangement (100) according to claim 1, wherein the interrupt request distribution arrangement (100) has m inputs (102 a, 102b, 102c, 102 d) for receiving input interrupt request signals (irq_i1, irq_i2, irq_i3, irq_i4), wherein m is greater than 1, and/or wherein the interrupt request distribution arrangement (100) has n outputs (112 a, 112b, 112c, 112 d) for outputting output interrupt request signals (irq_o), wherein n is greater than 1.
3. Interrupt request distribution arrangement (100) according to one of the preceding claims, wherein at least one timer means (130) is provided for determining or predetermining one or more delay times.
4. Interrupt request distribution arrangement (100) according to one of the preceding claims, wherein the interrupt request distribution arrangement (100) is configured for receiving configuration information from an external component (10; 200') and/or for at least temporarily storing configuration information, wherein the configuration information characterizes in particular the delay time (T1) or the delay times (T1, T2, T3).
5. Interrupt request distribution arrangement (100) according to one of the preceding claims, wherein the interrupt request distribution arrangement (100) is configured for interrupting a currently running delay time (T1, T2, T3), wherein the interrupt request distribution arrangement (100) is in particular configured for receiving an interrupt instruction (HLT) during the currently running delay time (T1, T2, T3) and interrupting the currently running delay time (T1, T2, T3) in response to the receipt of the interrupt instruction (HLT).
6. Interrupt request distribution device (100) according to one of the preceding claims, wherein the interrupt request distribution device (100) is at least partially, but preferably completely, constructed as a hardware circuit.
7. An electronic functional component (500) configured for generating at least one interrupt request signal (irq_o) for at least one further component (100), in particular for a computing core (202) of a computing unit (200), characterized in that the functional component (500) has an input (502) for receiving (600) an input signal (i) and an interrupt request signal generating means (510), wherein the interrupt request signal generating means (510) is configured for generating (610) at least one interrupt request signal (irq) from the input signal (i), and the functional component (500) has a delay means (520) configured for delaying (620) the at least one interrupt request signal (irq) by a predefinable delay time (T1) in order to obtain a delayed interrupt request signal (irq_d) and for outputting (630) the delayed interrupt request signal (irq_d) as an output interrupt request signal (irq_o) to the at least one further component (100'; 202), wherein the functional component (500) has a plurality of delay means (500) which are not configured for delaying (1) the interrupt request signal (i) by the same delay time (T1) or (T1), such that the delay of the interrupt request signal effectively matches the typical cycle time of the source or sink of the interrupt request signal.
8. A computing unit (1000; 1000'; 2000), in particular a microcontroller, has at least one computing core, wherein the computing unit (1000; 1000'; 2000) has at least one interrupt request distribution device (100; 100 ') according to one of claims 1 to 6 and/or at least one electronic functional component (500) according to claim 7.
9. Method for operating an interrupt request distribution device (100), in particular for a computing unit (200) having at least one computing core (202), wherein the interrupt request distribution device (100) has at least one input (102) for receiving (400) an input interrupt request signal (irq_i) and at least one output (112) for outputting an output interrupt request signal (irq_o), in particular to the computing unit (200), wherein the interrupt request distribution device (100) is designed to form at least one output interrupt request signal (irq_o) as a function of the at least one input interrupt request signal (irq_i), characterized in that the interrupt request distribution device (100) delays (410) the input interrupt request signal (irq_i) by means of a delay device (120) by a predefinable delay time (T1) in order to obtain a delayed interrupt request signal (irq_d) and to output (420) the delayed interrupt request signal (irq_d) as an output interrupt request signal (irq_o) to the at least one output (420), wherein the interrupt request distribution device (100) has a plurality of delay devices (120 a ) and (120 a) are designed to delay the interrupt request signal (1) by means (120 a) and (120 a) respectively, such that the delay of the interrupt request signal effectively matches the typical cycle time of the source or sink of the interrupt request signal.
10. The method according to claim 9, wherein configuration information (140) is received from an external component (10; 200') and/or configuration information (140) is stored locally at least temporarily, wherein the configuration information (140) characterizes in particular the delay time (T1) or the delay time (T1, T2, T3).
11. Method according to claim 9 or 10, wherein an interrupt instruction (HLT) is generated in and/or received by the interrupt request distribution means during the delay time of the current operation, and wherein the delay time of the current operation is interrupted in response to the generation and/or reception of an interrupt instruction (HLT).
12. Method for operating an electronic functional component (500) which is designed to generate at least one interrupt request signal (irq) for at least one further component (100 "), in particular a computing core (202) of a computing unit (200), characterized in that: the functional component (500) has an input (502) for receiving an input signal (i) and an interrupt request signal generating means (510), wherein the interrupt request signal generating means (510) generates at least one interrupt request signal (irq) as a function of the input signal (i); and is characterized in that: the functional module (500) has a delay device (520) which delays at least one interrupt request signal (irq) by a predefinable delay time (T1) in order to obtain a delayed interrupt request signal (irq_d) and outputs the delayed interrupt request signal (irq_d) as an output interrupt request signal (irq_o) to at least one further module (100'; 202), wherein the functional module (500) has a plurality of delay devices which are designed to delay the input interrupt request signal (irq_i) by delay times (T1, T2, T3) which are identical or different from one another, respectively, in such a way that the delay of the interrupt request signal effectively matches the typical cycle time of the source or sink of the interrupt request signal.
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