CN107611117A - A kind of process and PIP capacitor for generating PIP capacitor - Google Patents
A kind of process and PIP capacitor for generating PIP capacitor Download PDFInfo
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- CN107611117A CN107611117A CN201710733270.7A CN201710733270A CN107611117A CN 107611117 A CN107611117 A CN 107611117A CN 201710733270 A CN201710733270 A CN 201710733270A CN 107611117 A CN107611117 A CN 107611117A
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- polysilicon
- pip capacitor
- electric capacity
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Abstract
The invention discloses a kind of process and PIP capacitor for generating PIP capacitor, including depositing first layer polysilicon, defined by photoresistance and etch the first layer polysilicon and form the first polysilicon layer, deposit second layer polysilicon, defined by photoresistance and etch the second layer polysilicon and form several the second discrete polysilicon layers independent of one another, and first polysilicon layer and several second polysilicon layers collectively constitute electric capacity bottom crown, then dielectric substance layer and electric capacity top crown are formed, form capacitance structure, the setting that the present invention passes through second layer polysilicon, the area of bottom crown is extended in the case where not increasing capacitance size, so as to add the capacitance of PIP capacitor, the entire area of electric capacity is not increased while the area of capacitor plate is increased, and controllability and designability are good, suitable for batch production.
Description
Technical field
The present invention relates to semiconductor components and devices technology field, especially a kind of process for generating PIP capacitor, Yi Jisuo
The PIP capacitor structure of generation.
Background technology
PIP capacitor is the passive device commonly used in IC chip, and in existing practice or formerly technology, PIP capacitor is
The passive device commonly used in integrated circuit, it is usually used in noise emission and warbled device in radio frequency and analog circuit.PIP electricity
Container has the bottom electrode formed by polysilicon and a Top electrode, and dielectric medium is made up of silicon nitride or silica between upper/lower electrode.
In the case that device needs bulky capacitor, generally realized by increasing the area of upper bottom crown, referring to accompanying drawing 1-5, easy steps
And flow is as follows：
(1) the superficial growth polysilicon layer P2 of Si substrates 1；
(2) defined by photoresistance and use dry etching polysilicon layer P2, the polysilicon layer P2 of reservation is as pole under electric capacity
Plate region；
(3) boiler tube growing silicon oxide adds silicon nitride layer 3, as dielectric substance layer；
And then growth second layer polysilicon layer P1 and silicon tungsten compound (4)；
(5) dry etching, redundance is removed, the second layer polysilicon layer P1 of reservation is as electric capacity top crown part.
But in existing process, if necessary to increase capacitance, often use polar plate area above and below increasing and Jie is thinned
The thickness of electric matter layer, because dielectric substance layer is under certain thickness, uniformity is deteriorated, so general use increases polar plate area
Method.Increase polar plate area, the area of integrated circuit can be significantly increased so as to constrain the miniaturization of semiconductor devices.Therefore
The problem of capacitance for lifting PIP capacitor unit area, becomes extremely urgent.Therefore, a kind of new generation PIP capacitor is invented
Process solve the above problems it is necessary.
The content of the invention
A kind of technique side for generating PIP capacitor is provided the invention aims to solve above-mentioned the deficiencies in the prior art
Method.
To achieve these goals, the process of a kind of generation PIP capacitor designed by the present invention, including deposition first
Layer polysilicon, defined by photoresistance and etch the first polysilicon layer of the first layer polysilicon formation, deposit second layer polysilicon,
Defined by photoresistance and etch the second layer polysilicon and form several the second discrete polysilicon layers independent of one another, and first
Polysilicon layer and several second polysilicon layers collectively constitute electric capacity bottom crown, then form dielectric substance layer and third layer polycrystalline
Silicon, form capacitance structure.
The production technology specifically includes following step：
Step 1：First layer polysilicon is deposited on substrate；
Step 2：Defined by photoresistance and use first layer polysilicon described in dry etching, form the first polysilicon layer；
Step 3：Second layer polysilicon is deposited on the first polysilicon layer surface；
Step 4：Defined by photoresistance and use second layer polysilicon described in dry etching, formed above the first polysilicon layer
Several the second polysilicon layers separate；First polysilicon layer and several second polysilicon layers are collectively as electric capacity
Bottom crown region；
Step 5：In the first polysilicon layer and several the second polysilicon layer surface silicon oxide layer depositeds and silicon nitride layer shape
Into capacitor dielectric layer；
Step 6：Third layer polysilicon is deposited in capacitor dielectric layer；
Step 7：Defined by photoresistance and use third layer polysilicon described in dry etching, form electric capacity top crown region.
Preferably, the backing material is Si.
Preferably, it is 1000A-2000A first layer polysilicon thickness to be deposited in the step 1.
Preferably, it is 300A-500A second layer polysilicon thickness to be deposited in the step 3.
Preferably, deposited oxide silicon thickness is 50A-100A in the step 5, and cvd nitride silicon thickness is 100A-200A.
Preferably, it is 1200-2000A third layer polysilicon thickness to be deposited in the step 6.
The present invention and then provide a kind of PIP capacitor structure, including electric capacity bottom crown region, capacitor dielectric layer, electric capacity
Top crown region；Characterized in that, the electric capacity bottom crown region includes the first polysilicon layer, and it is formed at more than described first
Crystal silicon layer top and several second polysilicon layers separate.
Preferably, first polysilicon layer thicknesses are 1000A-2000A.
Preferably, the second layer polysilicon layer thicknesses are 300A-500A.
Preferably, the electric capacity top crown region is polysilicon layer, and the thickness of the polysilicon layer is 1200-2000A.
Preferably, the capacitor dielectric layer includes silicon oxide layer and silicon nitride layer.It may further be preferable that the oxidation
Silicon layer thickness is 50A-100A, and silicon nitride layer thickness is 100A-200A.
The advantage of the invention is that：By the setting of the second polysilicon layer, the area of bottom crown is extended, so as to increase
The capacitance of PIP capacitor, while do not increase the entire area of capacity cell, and controllability and designability are good, be applied to
Batch production.
Brief description of the drawings
Fig. 1-5 is existing process schematic diagram of the present invention.
Fig. 6 is first layer polysilicon deposition figure of the present invention.
Fig. 7 is first layer polysilicon etch figure of the present invention.
Fig. 8 is second layer polysilicon deposition figure of the present invention.
Fig. 9 is second layer polysilicon etch figure of the present invention.
Figure 10 is third layer polysilicon deposition figure of the present invention.
Figure 11 is third layer polysilicon etch figure of the present invention.
Embodiment
With reference to embodiment, the present invention is further described.
Embodiment 1：
The present embodiment provides a kind of process and PIP capacitor for generating PIP capacitor.；
The production technology specifically includes following step：
Step 1：As shown in fig. 6,1000A first layers polysilicon 2 is deposited on substrate 1；
Step 2：As shown in fig. 7, being defined by photoresistance and using first layer polysilicon described in dry etching, the first polycrystalline is formed
Silicon layer 2；
Step 3：As shown in figure 8, deposit 300A second layer polysilicons on the surface of the first polysilicon layer 2；
Step 4：As shown in figure 9, defined by photoresistance and use second layer polysilicon described in dry etching, in the first polysilicon
The top of layer 2 forms several second polysilicon layers 3 separate；First polysilicon layer 2 and several second polysilicons
Layer 3 is collectively as electric capacity bottom crown region；
Step 5：As shown in Figure 10, in the first polysilicon layer 2 and the deposition 50A oxidations of several surfaces of the second polysilicon layer 3
The capacitor dielectric layer 4 that silicon layer and 100A silicon nitride layers are formed；
Step 6：As shown in Figure 10,1200A third layer polysilicon 5 is deposited on capacitor dielectric layer 4；
Step 7：As shown in figure 11, defined by photoresistance and use third layer polysilicon described in dry etching, formed on electric capacity
Plate regions.
Embodiment 2：
Present embodiments provide a kind of process and PIP capacitor for generating PIP capacitor.The production technology specifically includes
Following step：
Step 1：1500A first layer polysilicons are deposited on substrate；
Step 2：Defined by photoresistance and use first layer polysilicon described in dry etching, form the first polysilicon layer；
Step 3：400A second layer polysilicons are deposited on the first polysilicon layer surface；
Step 4：Defined by photoresistance and use second layer polysilicon described in dry etching, formed above the first polysilicon layer
Several the second polysilicon layers separate；First polysilicon layer and several second polysilicon layers are collectively as electric capacity
Bottom crown region；
Step 5：In the first polysilicon layer and several the second polysilicon layer surfaces deposition 75A silicon oxide layers and 150A nitridations
The capacitor dielectric layer that silicon layer is formed；
Step 6：1600A third layer polysilicons are deposited in capacitor dielectric layer；
Step 7：Defined by photoresistance and use third layer polysilicon described in dry etching, form electric capacity top crown region.
Embodiment 3：
Present embodiments provide a kind of process and PIP capacitor for generating PIP capacitor；
The production technology specifically includes following step：
Step 1：2000A first layer polysilicons are deposited on substrate；
Step 2：Defined by photoresistance and use first layer polysilicon described in dry etching, form the first polysilicon layer；
Step 3：500A second layer polysilicons are deposited on the first polysilicon layer surface；
Step 4：Defined by photoresistance and use second layer polysilicon described in dry etching, formed above the first polysilicon layer
Several the second polysilicon layers separate；First polysilicon layer and several second polysilicon layers are collectively as electric capacity
Bottom crown region；
Step 5：In the first polysilicon layer and several the second polysilicon layer surfaces deposition 100A silicon oxide layers and 200A nitrogen
The capacitor dielectric layer that SiClx layer is formed；
Step 6：2000A third layer polysilicons are deposited in capacitor dielectric layer；
Step 7：Defined by photoresistance and use third layer polysilicon described in dry etching, form electric capacity top crown region.
It can be obtained according to embodiment 1-3：When first layer polysilicon deposition thickness is 1500A, second layer polysilicon deposition thickness
For 400A, nitride deposition thickness be 150A and when third layer polysilicon deposition thickness is 1200-2000A, do not increasing electric capacity
It is more beneficial for extending the area of bottom crown in the case of size, so as to significantly increase the capacitance of PIP capacitor.
Finally it should be noted that：The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention,
Although the present invention is described in detail with reference to the foregoing embodiments, for those skilled in the art, it still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic,
Within the spirit and principles of the invention, any modification, equivalent substitution and improvements made etc., it should be included in the present invention's
Within protection domain.
Claims (12)
- A kind of 1. process for generating PIP capacitor, it is characterised in that：Comprise the steps：Step 1：First layer polysilicon is deposited on substrate；Step 2：Defined by photoresistance and use first layer polysilicon described in dry etching, form the first polysilicon layer；Step 3：Second layer polysilicon is deposited on the first polysilicon layer surface；Step 4：Defined by photoresistance and use second layer polysilicon described in dry etching, formed above the first polysilicon layer some Individual second polysilicon layer separate；First polysilicon layer and several second polysilicon layers are collectively as pole under electric capacity Plate region；Step 5：Formed in the first polysilicon layer and several the second polysilicon layer surface silicon oxide layer depositeds and silicon nitride layer Capacitor dielectric layer；Step 6：Third layer polysilicon is deposited in capacitor dielectric layer；Step 7：Defined by photoresistance and use third layer polysilicon described in dry etching, form electric capacity top crown region.
- 2. the process of generation PIP capacitor according to claim 1, it is characterised in that：The backing material is Si.
- 3. the process of generation PIP capacitor according to claim 1, it is characterised in that：First is deposited in the step 1 Layer polysilicon thickness is 1000A-2000A.
- 4. the process of generation PIP capacitor according to claim 1, it is characterised in that deposit second in the step 3 Layer polysilicon thickness is 300A-500A.
- 5. the process of generation PIP capacitor according to claim 1, it is characterised in that deposited oxide in the step 5 Silicon thickness is 50A-100A, and cvd nitride silicon thickness is 100A-200A.
- 6. the process of generation PIP capacitor according to claim 1, it is characterised in that the 3rd is deposited in the step 6 Layer polysilicon thickness is 1200-2000A.
- 7. a kind of PIP capacitor structure, including electric capacity bottom crown region, capacitor dielectric layer, electric capacity top crown region；Its feature exists In the electric capacity bottom crown region includes the first polysilicon layer, and is formed above first polysilicon layer and divides each other Several vertical second polysilicon layers.
- 8. PIP capacitor structure according to claim 7, it is characterised in that first polysilicon layer thicknesses are 1000A- 2000A。
- 9. PIP capacitor structure according to claim 7, it is characterised in that the second layer polysilicon layer thicknesses are 300A- 500A。
- 10. PIP capacitor structure according to claim 7, it is characterised in that the electric capacity top crown region is polysilicon Layer, the thickness of the polysilicon layer is 1200-2000A.
- 11. PIP capacitor structure according to claim 7, it is characterised in that the capacitor dielectric layer includes silicon oxide layer And silicon nitride layer.
- 12. PIP capacitor structure according to claim 11, it is characterised in that the silicon oxide layer thickness is 50A-100A, Silicon nitride layer thickness is 100A-200A.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710733270.7A CN107611117A (en) | 2017-08-24 | 2017-08-24 | A kind of process and PIP capacitor for generating PIP capacitor |
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| CN201710733270.7A CN107611117A (en) | 2017-08-24 | 2017-08-24 | A kind of process and PIP capacitor for generating PIP capacitor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6057189A (en) * | 1997-12-22 | 2000-05-02 | United Microelectronics Corp. | Method of fabricating capacitor utilizing an ion implantation method |
| CN1467853A (en) * | 2002-06-21 | 2004-01-14 | ����ʿ�뵼������˾ | Capacitor with oxidation barrier layer and method for manufacturing the same |
| CN1988158A (en) * | 2005-12-23 | 2007-06-27 | 上海华虹Nec电子有限公司 | Flat plate capacitor and its realizing method |
| CN105632891A (en) * | 2014-11-28 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of PIP capacitor |
-
2017
- 2017-08-24 CN CN201710733270.7A patent/CN107611117A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6057189A (en) * | 1997-12-22 | 2000-05-02 | United Microelectronics Corp. | Method of fabricating capacitor utilizing an ion implantation method |
| CN1467853A (en) * | 2002-06-21 | 2004-01-14 | ����ʿ�뵼������˾ | Capacitor with oxidation barrier layer and method for manufacturing the same |
| CN1988158A (en) * | 2005-12-23 | 2007-06-27 | 上海华虹Nec电子有限公司 | Flat plate capacitor and its realizing method |
| CN105632891A (en) * | 2014-11-28 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of PIP capacitor |
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Application publication date: 20180119 |